projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| d9fda07a BC |
1 | /* |
| 2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | */ | |
| 8 | ||
| 9 | /* | |
| 10 | * Carveout for multimedia usecases | |
| 11 | * It should be the last 48MB of the first 512MB memory part | |
| 12 | * In theory, it should not even exist. That zone should be reserved | |
| 13 | * dynamically during the .reserve callback. | |
| 14 | */ | |
| 15 | /memreserve/ 0x9d000000 0x03000000; | |
| 16 | ||
| 17 | /include/ "skeleton.dtsi" | |
| 18 | ||
| 19 | / { | |
| 20 | compatible = "ti,omap4430", "ti,omap4"; | |
| 21 | interrupt-parent = <&gic>; | |
| 22 | ||
| 23 | aliases { | |
| 24 | }; | |
| 25 | ||
| 476b679a BC |
26 | cpus { |
| 27 | cpu@0 { | |
| 28 | compatible = "arm,cortex-a9"; | |
| 29 | }; | |
| 30 | cpu@1 { | |
| 31 | compatible = "arm,cortex-a9"; | |
| 32 | }; | |
| 33 | }; | |
| 34 | ||
| d9fda07a BC |
35 | /* |
| 36 | * The soc node represents the soc top level view. It is uses for IPs | |
| 37 | * that are not memory mapped in the MPU view or for the MPU itself. | |
| 38 | */ | |
| 39 | soc { | |
| 40 | compatible = "ti,omap-infra"; | |
| 476b679a BC |
41 | mpu { |
| 42 | compatible = "ti,omap4-mpu"; | |
| 43 | ti,hwmods = "mpu"; | |
| 44 | }; | |
| 45 | ||
| 46 | dsp { | |
| 47 | compatible = "ti,omap3-c64"; | |
| 48 | ti,hwmods = "dsp"; | |
| 49 | }; | |
| 50 | ||
| 51 | iva { | |
| 52 | compatible = "ti,ivahd"; | |
| 53 | ti,hwmods = "iva"; | |
| 54 | }; | |
| d9fda07a BC |
55 | }; |
| 56 | ||
| 57 | /* | |
| 58 | * XXX: Use a flat representation of the OMAP4 interconnect. | |
| 59 | * The real OMAP interconnect network is quite complex. | |
| 60 | * | |
| 61 | * MPU -+-- MPU_PRIVATE - GIC, L2 | |
| 62 | * | | |
| 63 | * +----------------+----------+ | |
| 64 | * | | | | |
| 65 | * + +- EMIF - DDR | | |
| 66 | * | | | | |
| 67 | * | + +--------+ | |
| 68 | * | | | | |
| 69 | * | +- L4_ABE - AESS, MCBSP, TIMERs... | |
| 70 | * | | | |
| 71 | * +- L3_MAIN --+- L4_CORE - IPs... | |
| 72 | * | | |
| 73 | * +- L4_PER - IPs... | |
| 74 | * | | |
| 75 | * +- L4_CFG -+- L4_WKUP - IPs... | |
| 76 | * | | | |
| 77 | * | +- IPs... | |
| 78 | * +- IPU ----+ | |
| 79 | * | | | |
| 80 | * +- DSP ----+ | |
| 81 | * | | | |
| 82 | * +- DSS ----+ | |
| 83 | * | |
| 84 | * Since that will not bring real advantage to represent that in DT for | |
| 85 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
| 86 | * hierarchy. | |
| 87 | */ | |
| 88 | ocp { | |
| ad8dfac6 | 89 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
| d9fda07a BC |
90 | #address-cells = <1>; |
| 91 | #size-cells = <1>; | |
| 92 | ranges; | |
| ad8dfac6 | 93 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
| d9fda07a BC |
94 | |
| 95 | gic: interrupt-controller@48241000 { | |
| 96 | compatible = "arm,cortex-a9-gic"; | |
| 97 | interrupt-controller; | |
| 98 | #interrupt-cells = <1>; | |
| 99 | reg = <0x48241000 0x1000>, | |
| 100 | <0x48240100 0x0100>; | |
| 101 | }; | |
| 102 | }; | |
| 103 | }; |