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[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / omap5.dtsi
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6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
98ef7957 14#include "skeleton.dtsi"
6b5de091
S		 15
16/ {
ba1829bc
SS		 17 #address-cells = <1>;
18 #size-cells = <1>;
19
6b5de091
S		 20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
20b80942
NM		 24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
6b5de091
S		 29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
eeb25fd5
LP		 38 #address-cells = <1>;
39 #size-cells = <0>;
40
b8981d71 41 cpu0: cpu@0 {
eeb25fd5 42 device_type = "cpu";
6b5de091 43 compatible = "arm,cortex-a15";
eeb25fd5 44 reg = <0x0>;
6c24894d
K		 45
46 operating-points = <
47 /* kHz uV */
48 500000 880000
49 1000000 1060000
50 1500000 1250000
51 >;
8d766fa2
NM		 52
53 clocks = <&dpll_mpu_ck>;
54 clock-names = "cpu";
55
56 clock-latency = <300000>; /* From omap-cpufreq driver */
57
2cd29f63
EV		 58 /* cooling options */
59 cooling-min-level = <0>;
60 cooling-max-level = <2>;
61 #cooling-cells = <2>; /* min followed by max */
6b5de091
S		 62 };
63 cpu@1 {
eeb25fd5 64 device_type = "cpu";
6b5de091 65 compatible = "arm,cortex-a15";
eeb25fd5 66 reg = <0x1>;
6b5de091
S		 67 };
68 };
69
1b761fc5
EV		 70 thermal-zones {
71 #include "omap4-cpu-thermal.dtsi"
72 #include "omap5-gpu-thermal.dtsi"
73 #include "omap5-core-thermal.dtsi"
74 };
75
b45ccc4e
SS		 76 timer {
77 compatible = "arm,armv7-timer";
8fea7d5a
FV		 78 /* PPI secure/nonsecure IRQ */
79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
b45ccc4e
SS		 83 };
84
ba1829bc
SS		 85 gic: interrupt-controller@48211000 {
86 compatible = "arm,cortex-a15-gic";
87 interrupt-controller;
88 #interrupt-cells = <3>;
89 reg = <0x48211000 0x1000>,
0129c16c
SS		 90 <0x48212000 0x1000>,
91 <0x48214000 0x2000>,
92 <0x48216000 0x2000>;
ba1829bc
SS		 93 };
94
6b5de091
S		 95 /*
96 * The soc node represents the soc top level view. It is uses for IPs
97 * that are not memory mapped in the MPU view or for the MPU itself.
98 */
99 soc {
100 compatible = "ti,omap-infra";
101 mpu {
102 compatible = "ti,omap5-mpu";
103 ti,hwmods = "mpu";
104 };
105 };
106
107 /*
108 * XXX: Use a flat representation of the OMAP3 interconnect.
109 * The real OMAP interconnect network is quite complex.
110 * Since that will not bring real advantage to represent that in DT for
111 * the moment, just use a fake OCP bus entry to represent the whole bus
112 * hierarchy.
113 */
114 ocp {
115 compatible = "ti,omap4-l3-noc", "simple-bus";
116 #address-cells = <1>;
117 #size-cells = <1>;
118 ranges;
119 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 120 reg = <0x44000000 0x2000>,
121 <0x44800000 0x3000>,
122 <0x45000000 0x4000>;
8fea7d5a
FV		 123 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 125
85dc74e9
TK		 126 prm: prm@4ae06000 {
127 compatible = "ti,omap5-prm";
128 reg = <0x4ae06000 0x3000>;
129
130 prm_clocks: clocks {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 };
134
135 prm_clockdomains: clockdomains {
136 };
137 };
138
139 cm_core_aon: cm_core_aon@4a004000 {
140 compatible = "ti,omap5-cm-core-aon";
141 reg = <0x4a004000 0x2000>;
142
143 cm_core_aon_clocks: clocks {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 };
147
148 cm_core_aon_clockdomains: clockdomains {
149 };
150 };
151
152 scrm: scrm@4ae0a000 {
153 compatible = "ti,omap5-scrm";
154 reg = <0x4ae0a000 0x2000>;
155
156 scrm_clocks: clocks {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 };
160
161 scrm_clockdomains: clockdomains {
162 };
163 };
164
165 cm_core: cm_core@4a008000 {
166 compatible = "ti,omap5-cm-core";
167 reg = <0x4a008000 0x3000>;
168
169 cm_core_clocks: clocks {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 };
173
174 cm_core_clockdomains: clockdomains {
175 };
176 };
177
3b3132f7
JH		 178 counter32k: counter@4ae04000 {
179 compatible = "ti,omap-counter32k";
180 reg = <0x4ae04000 0x40>;
181 ti,hwmods = "counter_32k";
182 };
183
5da6a2d5
PU		 184 omap5_pmx_core: pinmux@4a002840 {
185 compatible = "ti,omap4-padconf", "pinctrl-single";
186 reg = <0x4a002840 0x01b6>;
187 #address-cells = <1>;
188 #size-cells = <0>;
189 pinctrl-single,register-width = <16>;
190 pinctrl-single,function-mask = <0x7fff>;
191 };
192 omap5_pmx_wkup: pinmux@4ae0c840 {
193 compatible = "ti,omap4-padconf", "pinctrl-single";
194 reg = <0x4ae0c840 0x0038>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197 pinctrl-single,register-width = <16>;
198 pinctrl-single,function-mask = <0x7fff>;
199 };
200
cd042fe5
B		 201 omap5_padconf_global: tisyscon@4a002da0 {
202 compatible = "syscon";
203 reg = <0x4A002da0 0xec>;
204 };
205
206 pbias_regulator: pbias_regulator {
207 compatible = "ti,pbias-omap";
208 reg = <0x60 0x4>;
209 syscon = <&omap5_padconf_global>;
210 pbias_mmc_reg: pbias_mmc_omap5 {
211 regulator-name = "pbias_mmc_omap5";
212 regulator-min-microvolt = <1800000>;
213 regulator-max-microvolt = <3000000>;
214 };
215 };
216
2c2dc545
JH		 217 sdma: dma-controller@4a056000 {
218 compatible = "ti,omap4430-sdma";
219 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 220 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 224 #dma-cells = <1>;
225 #dma-channels = <32>;
226 #dma-requests = <127>;
227 };
228
6b5de091
S		 229 gpio1: gpio@4ae10000 {
230 compatible = "ti,omap4-gpio";
f4b224f2 231 reg = <0x4ae10000 0x200>;
8fea7d5a 232 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 233 ti,hwmods = "gpio1";
e4b9b9f3 234 ti,gpio-always-on;
6b5de091
S		 235 gpio-controller;
236 #gpio-cells = <2>;
237 interrupt-controller;
ff5c9059 238 #interrupt-cells = <2>;
6b5de091
S		 239 };
240
241 gpio2: gpio@48055000 {
242 compatible = "ti,omap4-gpio";
f4b224f2 243 reg = <0x48055000 0x200>;
8fea7d5a 244 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 245 ti,hwmods = "gpio2";
246 gpio-controller;
247 #gpio-cells = <2>;
248 interrupt-controller;
ff5c9059 249 #interrupt-cells = <2>;
6b5de091
S		 250 };
251
252 gpio3: gpio@48057000 {
253 compatible = "ti,omap4-gpio";
f4b224f2 254 reg = <0x48057000 0x200>;
8fea7d5a 255 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 256 ti,hwmods = "gpio3";
257 gpio-controller;
258 #gpio-cells = <2>;
259 interrupt-controller;
ff5c9059 260 #interrupt-cells = <2>;
6b5de091
S		 261 };
262
263 gpio4: gpio@48059000 {
264 compatible = "ti,omap4-gpio";
f4b224f2 265 reg = <0x48059000 0x200>;
8fea7d5a 266 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 267 ti,hwmods = "gpio4";
268 gpio-controller;
269 #gpio-cells = <2>;
270 interrupt-controller;
ff5c9059 271 #interrupt-cells = <2>;
6b5de091
S		 272 };
273
274 gpio5: gpio@4805b000 {
275 compatible = "ti,omap4-gpio";
f4b224f2 276 reg = <0x4805b000 0x200>;
8fea7d5a 277 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 278 ti,hwmods = "gpio5";
279 gpio-controller;
280 #gpio-cells = <2>;
281 interrupt-controller;
ff5c9059 282 #interrupt-cells = <2>;
6b5de091
S		 283 };
284
285 gpio6: gpio@4805d000 {
286 compatible = "ti,omap4-gpio";
f4b224f2 287 reg = <0x4805d000 0x200>;
8fea7d5a 288 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 289 ti,hwmods = "gpio6";
290 gpio-controller;
291 #gpio-cells = <2>;
292 interrupt-controller;
ff5c9059 293 #interrupt-cells = <2>;
6b5de091
S		 294 };
295
296 gpio7: gpio@48051000 {
297 compatible = "ti,omap4-gpio";
f4b224f2 298 reg = <0x48051000 0x200>;
8fea7d5a 299 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 300 ti,hwmods = "gpio7";
301 gpio-controller;
302 #gpio-cells = <2>;
303 interrupt-controller;
ff5c9059 304 #interrupt-cells = <2>;
6b5de091
S		 305 };
306
307 gpio8: gpio@48053000 {
308 compatible = "ti,omap4-gpio";
f4b224f2 309 reg = <0x48053000 0x200>;
8fea7d5a 310 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 311 ti,hwmods = "gpio8";
312 gpio-controller;
313 #gpio-cells = <2>;
314 interrupt-controller;
ff5c9059 315 #interrupt-cells = <2>;
6b5de091
S		 316 };
317
1c7dbb55
JH		 318 gpmc: gpmc@50000000 {
319 compatible = "ti,omap4430-gpmc";
320 reg = <0x50000000 0x1000>;
321 #address-cells = <2>;
322 #size-cells = <1>;
8fea7d5a 323 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 324 gpmc,num-cs = <8>;
325 gpmc,num-waitpins = <4>;
326 ti,hwmods = "gpmc";
7b8b6af1
FV		 327 clocks = <&l3_iclk_div>;
328 clock-names = "fck";
1c7dbb55
JH		 329 };
330
6e6a9a50
SP		 331 i2c1: i2c@48070000 {
332 compatible = "ti,omap4-i2c";
d7118bbd 333 reg = <0x48070000 0x100>;
8fea7d5a 334 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 335 #address-cells = <1>;
336 #size-cells = <0>;
337 ti,hwmods = "i2c1";
338 };
339
340 i2c2: i2c@48072000 {
341 compatible = "ti,omap4-i2c";
d7118bbd 342 reg = <0x48072000 0x100>;
8fea7d5a 343 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 344 #address-cells = <1>;
345 #size-cells = <0>;
346 ti,hwmods = "i2c2";
347 };
348
349 i2c3: i2c@48060000 {
350 compatible = "ti,omap4-i2c";
d7118bbd 351 reg = <0x48060000 0x100>;
8fea7d5a 352 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 353 #address-cells = <1>;
354 #size-cells = <0>;
355 ti,hwmods = "i2c3";
356 };
357
d7118bbd 358 i2c4: i2c@4807a000 {
6e6a9a50 359 compatible = "ti,omap4-i2c";
d7118bbd 360 reg = <0x4807a000 0x100>;
8fea7d5a 361 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 362 #address-cells = <1>;
363 #size-cells = <0>;
364 ti,hwmods = "i2c4";
365 };
366
d7118bbd 367 i2c5: i2c@4807c000 {
6e6a9a50 368 compatible = "ti,omap4-i2c";
d7118bbd 369 reg = <0x4807c000 0x100>;
8fea7d5a 370 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 371 #address-cells = <1>;
372 #size-cells = <0>;
373 ti,hwmods = "i2c5";
374 };
375
fe0e09e4
SA		 376 hwspinlock: spinlock@4a0f6000 {
377 compatible = "ti,omap4-hwspinlock";
378 reg = <0x4a0f6000 0x1000>;
379 ti,hwmods = "spinlock";
34054213 380 #hwlock-cells = <1>;
fe0e09e4
SA		 381 };
382
43286b11
FB		 383 mcspi1: spi@48098000 {
384 compatible = "ti,omap4-mcspi";
385 reg = <0x48098000 0x200>;
8fea7d5a 386 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 387 #address-cells = <1>;
388 #size-cells = <0>;
389 ti,hwmods = "mcspi1";
390 ti,spi-num-cs = <4>;
2c2dc545
JH		 391 dmas = <&sdma 35>,
392 <&sdma 36>,
393 <&sdma 37>,
394 <&sdma 38>,
395 <&sdma 39>,
396 <&sdma 40>,
397 <&sdma 41>,
398 <&sdma 42>;
399 dma-names = "tx0", "rx0", "tx1", "rx1",
400 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 401 };
402
403 mcspi2: spi@4809a000 {
404 compatible = "ti,omap4-mcspi";
405 reg = <0x4809a000 0x200>;
8fea7d5a 406 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 407 #address-cells = <1>;
408 #size-cells = <0>;
409 ti,hwmods = "mcspi2";
410 ti,spi-num-cs = <2>;
2c2dc545
JH		 411 dmas = <&sdma 43>,
412 <&sdma 44>,
413 <&sdma 45>,
414 <&sdma 46>;
415 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 416 };
417
418 mcspi3: spi@480b8000 {
419 compatible = "ti,omap4-mcspi";
420 reg = <0x480b8000 0x200>;
8fea7d5a 421 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 422 #address-cells = <1>;
423 #size-cells = <0>;
424 ti,hwmods = "mcspi3";
425 ti,spi-num-cs = <2>;
2c2dc545
JH		 426 dmas = <&sdma 15>, <&sdma 16>;
427 dma-names = "tx0", "rx0";
43286b11
FB		 428 };
429
430 mcspi4: spi@480ba000 {
431 compatible = "ti,omap4-mcspi";
432 reg = <0x480ba000 0x200>;
8fea7d5a 433 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 434 #address-cells = <1>;
435 #size-cells = <0>;
436 ti,hwmods = "mcspi4";
437 ti,spi-num-cs = <1>;
2c2dc545
JH		 438 dmas = <&sdma 70>, <&sdma 71>;
439 dma-names = "tx0", "rx0";
43286b11
FB		 440 };
441
6b5de091
S		 442 uart1: serial@4806a000 {
443 compatible = "ti,omap4-uart";
8e80f660 444 reg = <0x4806a000 0x100>;
8fea7d5a 445 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 446 ti,hwmods = "uart1";
447 clock-frequency = <48000000>;
448 };
449
450 uart2: serial@4806c000 {
451 compatible = "ti,omap4-uart";
8e80f660 452 reg = <0x4806c000 0x100>;
8fea7d5a 453 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 454 ti,hwmods = "uart2";
455 clock-frequency = <48000000>;
456 };
457
458 uart3: serial@48020000 {
459 compatible = "ti,omap4-uart";
8e80f660 460 reg = <0x48020000 0x100>;
8fea7d5a 461 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 462 ti,hwmods = "uart3";
463 clock-frequency = <48000000>;
464 };
465
466 uart4: serial@4806e000 {
467 compatible = "ti,omap4-uart";
8e80f660 468 reg = <0x4806e000 0x100>;
8fea7d5a 469 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 470 ti,hwmods = "uart4";
471 clock-frequency = <48000000>;
472 };
473
474 uart5: serial@48066000 {
8e80f660
SG		 475 compatible = "ti,omap4-uart";
476 reg = <0x48066000 0x100>;
8fea7d5a 477 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 478 ti,hwmods = "uart5";
479 clock-frequency = <48000000>;
480 };
481
482 uart6: serial@48068000 {
8e80f660
SG		 483 compatible = "ti,omap4-uart";
484 reg = <0x48068000 0x100>;
8fea7d5a 485 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 486 ti,hwmods = "uart6";
487 clock-frequency = <48000000>;
488 };
5dd18b01
B		 489
490 mmc1: mmc@4809c000 {
491 compatible = "ti,omap4-hsmmc";
9a642362 492 reg = <0x4809c000 0x400>;
8fea7d5a 493 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 494 ti,hwmods = "mmc1";
495 ti,dual-volt;
496 ti,needs-special-reset;
2c2dc545
JH		 497 dmas = <&sdma 61>, <&sdma 62>;
498 dma-names = "tx", "rx";
cd042fe5 499 pbias-supply = <&pbias_mmc_reg>;
5dd18b01
B		 500 };
501
502 mmc2: mmc@480b4000 {
503 compatible = "ti,omap4-hsmmc";
9a642362 504 reg = <0x480b4000 0x400>;
8fea7d5a 505 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 506 ti,hwmods = "mmc2";
507 ti,needs-special-reset;
2c2dc545
JH		 508 dmas = <&sdma 47>, <&sdma 48>;
509 dma-names = "tx", "rx";
5dd18b01
B		 510 };
511
512 mmc3: mmc@480ad000 {
513 compatible = "ti,omap4-hsmmc";
9a642362 514 reg = <0x480ad000 0x400>;
8fea7d5a 515 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 516 ti,hwmods = "mmc3";
517 ti,needs-special-reset;
2c2dc545
JH		 518 dmas = <&sdma 77>, <&sdma 78>;
519 dma-names = "tx", "rx";
5dd18b01
B		 520 };
521
522 mmc4: mmc@480d1000 {
523 compatible = "ti,omap4-hsmmc";
9a642362 524 reg = <0x480d1000 0x400>;
8fea7d5a 525 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 526 ti,hwmods = "mmc4";
527 ti,needs-special-reset;
2c2dc545
JH		 528 dmas = <&sdma 57>, <&sdma 58>;
529 dma-names = "tx", "rx";
5dd18b01
B		 530 };
531
532 mmc5: mmc@480d5000 {
533 compatible = "ti,omap4-hsmmc";
9a642362 534 reg = <0x480d5000 0x400>;
8fea7d5a 535 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 536 ti,hwmods = "mmc5";
537 ti,needs-special-reset;
2c2dc545
JH		 538 dmas = <&sdma 59>, <&sdma 60>;
539 dma-names = "tx", "rx";
5dd18b01 540 };
5449fbc2 541
2dcfa56e
SA		 542 mmu_dsp: mmu@4a066000 {
543 compatible = "ti,omap4-iommu";
544 reg = <0x4a066000 0x100>;
545 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
546 ti,hwmods = "mmu_dsp";
547 };
548
549 mmu_ipu: mmu@55082000 {
550 compatible = "ti,omap4-iommu";
551 reg = <0x55082000 0x100>;
552 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
553 ti,hwmods = "mmu_ipu";
554 ti,iommu-bus-err-back;
555 };
556
5449fbc2
SP		 557 keypad: keypad@4ae1c000 {
558 compatible = "ti,omap4-keypad";
8cc8b89f 559 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 560 ti,hwmods = "kbd";
561 };
ffd5db24 562
cbb57f07
PU		 563 mcpdm: mcpdm@40132000 {
564 compatible = "ti,omap4-mcpdm";
565 reg = <0x40132000 0x7f>, /* MPU private access */
566 <0x49032000 0x7f>; /* L3 Interconnect */
567 reg-names = "mpu", "dma";
8fea7d5a 568 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 569 ti,hwmods = "mcpdm";
4e4ead73
SG		 570 dmas = <&sdma 65>,
571 <&sdma 66>;
572 dma-names = "up_link", "dn_link";
f15534ea 573 status = "disabled";
cbb57f07
PU		 574 };
575
576 dmic: dmic@4012e000 {
577 compatible = "ti,omap4-dmic";
578 reg = <0x4012e000 0x7f>, /* MPU private access */
579 <0x4902e000 0x7f>; /* L3 Interconnect */
580 reg-names = "mpu", "dma";
8fea7d5a 581 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 582 ti,hwmods = "dmic";
4e4ead73
SG		 583 dmas = <&sdma 67>;
584 dma-names = "up_link";
f15534ea 585 status = "disabled";
cbb57f07
PU		 586 };
587
ffd5db24
PU		 588 mcbsp1: mcbsp@40122000 {
589 compatible = "ti,omap4-mcbsp";
590 reg = <0x40122000 0xff>, /* MPU private access */
591 <0x49022000 0xff>; /* L3 Interconnect */
592 reg-names = "mpu", "dma";
8fea7d5a 593 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 594 interrupt-names = "common";
ffd5db24
PU		 595 ti,buffer-size = <128>;
596 ti,hwmods = "mcbsp1";
4e4ead73
SG		 597 dmas = <&sdma 33>,
598 <&sdma 34>;
599 dma-names = "tx", "rx";
f15534ea 600 status = "disabled";
ffd5db24
PU		 601 };
602
603 mcbsp2: mcbsp@40124000 {
604 compatible = "ti,omap4-mcbsp";
605 reg = <0x40124000 0xff>, /* MPU private access */
606 <0x49024000 0xff>; /* L3 Interconnect */
607 reg-names = "mpu", "dma";
8fea7d5a 608 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 609 interrupt-names = "common";
ffd5db24
PU		 610 ti,buffer-size = <128>;
611 ti,hwmods = "mcbsp2";
4e4ead73
SG		 612 dmas = <&sdma 17>,
613 <&sdma 18>;
614 dma-names = "tx", "rx";
f15534ea 615 status = "disabled";
ffd5db24
PU		 616 };
617
618 mcbsp3: mcbsp@40126000 {
619 compatible = "ti,omap4-mcbsp";
620 reg = <0x40126000 0xff>, /* MPU private access */
621 <0x49026000 0xff>; /* L3 Interconnect */
622 reg-names = "mpu", "dma";
8fea7d5a 623 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 624 interrupt-names = "common";
ffd5db24
PU		 625 ti,buffer-size = <128>;
626 ti,hwmods = "mcbsp3";
4e4ead73
SG		 627 dmas = <&sdma 19>,
628 <&sdma 20>;
629 dma-names = "tx", "rx";
f15534ea 630 status = "disabled";
ffd5db24 631 };
df692a92
JH		 632
633 timer1: timer@4ae18000 {
002e1ec5 634 compatible = "ti,omap5430-timer";
df692a92 635 reg = <0x4ae18000 0x80>;
8fea7d5a 636 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 637 ti,hwmods = "timer1";
638 ti,timer-alwon;
639 };
640
641 timer2: timer@48032000 {
002e1ec5 642 compatible = "ti,omap5430-timer";
df692a92 643 reg = <0x48032000 0x80>;
8fea7d5a 644 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 645 ti,hwmods = "timer2";
646 };
647
648 timer3: timer@48034000 {
002e1ec5 649 compatible = "ti,omap5430-timer";
df692a92 650 reg = <0x48034000 0x80>;
8fea7d5a 651 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 652 ti,hwmods = "timer3";
653 };
654
655 timer4: timer@48036000 {
002e1ec5 656 compatible = "ti,omap5430-timer";
df692a92 657 reg = <0x48036000 0x80>;
8fea7d5a 658 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 659 ti,hwmods = "timer4";
660 };
661
662 timer5: timer@40138000 {
002e1ec5 663 compatible = "ti,omap5430-timer";
df692a92
JH		 664 reg = <0x40138000 0x80>,
665 <0x49038000 0x80>;
8fea7d5a 666 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 667 ti,hwmods = "timer5";
668 ti,timer-dsp;
8341613a 669 ti,timer-pwm;
df692a92
JH		 670 };
671
672 timer6: timer@4013a000 {
002e1ec5 673 compatible = "ti,omap5430-timer";
df692a92
JH		 674 reg = <0x4013a000 0x80>,
675 <0x4903a000 0x80>;
8fea7d5a 676 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 677 ti,hwmods = "timer6";
678 ti,timer-dsp;
679 ti,timer-pwm;
680 };
681
682 timer7: timer@4013c000 {
002e1ec5 683 compatible = "ti,omap5430-timer";
df692a92
JH		 684 reg = <0x4013c000 0x80>,
685 <0x4903c000 0x80>;
8fea7d5a 686 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 687 ti,hwmods = "timer7";
688 ti,timer-dsp;
689 };
690
691 timer8: timer@4013e000 {
002e1ec5 692 compatible = "ti,omap5430-timer";
df692a92
JH		 693 reg = <0x4013e000 0x80>,
694 <0x4903e000 0x80>;
8fea7d5a 695 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 696 ti,hwmods = "timer8";
697 ti,timer-dsp;
698 ti,timer-pwm;
699 };
700
701 timer9: timer@4803e000 {
002e1ec5 702 compatible = "ti,omap5430-timer";
df692a92 703 reg = <0x4803e000 0x80>;
8fea7d5a 704 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 705 ti,hwmods = "timer9";
8341613a 706 ti,timer-pwm;
df692a92
JH		 707 };
708
709 timer10: timer@48086000 {
002e1ec5 710 compatible = "ti,omap5430-timer";
df692a92 711 reg = <0x48086000 0x80>;
8fea7d5a 712 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 713 ti,hwmods = "timer10";
8341613a 714 ti,timer-pwm;
df692a92
JH		 715 };
716
717 timer11: timer@48088000 {
002e1ec5 718 compatible = "ti,omap5430-timer";
df692a92 719 reg = <0x48088000 0x80>;
8fea7d5a 720 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 721 ti,hwmods = "timer11";
722 ti,timer-pwm;
723 };
e6900ddf 724
55452197
LV		 725 wdt2: wdt@4ae14000 {
726 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
727 reg = <0x4ae14000 0x80>;
8fea7d5a 728 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 729 ti,hwmods = "wd_timer2";
730 };
731
1a5fe3ca
AT		 732 dmm@4e000000 {
733 compatible = "ti,omap5-dmm";
734 reg = <0x4e000000 0x800>;
735 interrupts = <0 113 0x4>;
736 ti,hwmods = "dmm";
737 };
738
8906d654 739 emif1: emif@4c000000 {
e6900ddf
LV		 740 compatible = "ti,emif-4d5";
741 ti,hwmods = "emif1";
f12ecbe2 742 ti,no-idle-on-init;
e6900ddf
LV		 743 phy-type = <2>; /* DDR PHY type: Intelli PHY */
744 reg = <0x4c000000 0x400>;
8fea7d5a 745 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 746 hw-caps-read-idle-ctrl;
747 hw-caps-ll-interface;
748 hw-caps-temp-alert;
749 };
750
8906d654 751 emif2: emif@4d000000 {
e6900ddf
LV		 752 compatible = "ti,emif-4d5";
753 ti,hwmods = "emif2";
f12ecbe2 754 ti,no-idle-on-init;
e6900ddf
LV		 755 phy-type = <2>; /* DDR PHY type: Intelli PHY */
756 reg = <0x4d000000 0x400>;
8fea7d5a 757 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 758 hw-caps-read-idle-ctrl;
759 hw-caps-ll-interface;
760 hw-caps-temp-alert;
761 };
fedc428e 762
b297c292
RQ		 763 omap_control_usb2phy: control-phy@4a002300 {
764 compatible = "ti,control-phy-usb2";
765 reg = <0x4a002300 0x4>;
766 reg-names = "power";
767 };
768
769 omap_control_usb3phy: control-phy@4a002370 {
770 compatible = "ti,control-phy-pipe3";
771 reg = <0x4a002370 0x4>;
772 reg-names = "power";
fedc428e 773 };
e9831967 774
e3a412c9 775 usb3: omap_dwc3@4a020000 {
72f6f957
KVA		 776 compatible = "ti,dwc3";
777 ti,hwmods = "usb_otg_ss";
6f61ee23 778 reg = <0x4a020000 0x10000>;
8fea7d5a 779 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 780 #address-cells = <1>;
781 #size-cells = <1>;
782 utmi-mode = <2>;
783 ranges;
784 dwc3@4a030000 {
22a5aa17 785 compatible = "snps,dwc3";
6f61ee23 786 reg = <0x4a030000 0x10000>;
8fea7d5a 787 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
073addc8
KVA		 788 phys = <&usb2_phy>, <&usb3_phy>;
789 phy-names = "usb2-phy", "usb3-phy";
c47ee6ee 790 dr_mode = "peripheral";
72f6f957
KVA		 791 tx-fifo-resize;
792 };
793 };
794
b6731f78 795 ocp2scp@4a080000 {
e9831967
KVA		 796 compatible = "ti,omap-ocp2scp";
797 #address-cells = <1>;
798 #size-cells = <1>;
b6731f78 799 reg = <0x4a080000 0x20>;
e9831967
KVA		 800 ranges;
801 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 802 usb2_phy: usb2phy@4a084000 {
803 compatible = "ti,omap-usb2";
804 reg = <0x4a084000 0x7c>;
b297c292 805 ctrl-module = <&omap_control_usb2phy>;
073addc8 806 #phy-cells = <0>;
ae6a32d2
KVA		 807 };
808
809 usb3_phy: usb3phy@4a084400 {
810 compatible = "ti,omap-usb3";
811 reg = <0x4a084400 0x80>,
812 <0x4a084800 0x64>,
813 <0x4a084c00 0x40>;
814 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
b297c292 815 ctrl-module = <&omap_control_usb3phy>;
073addc8 816 #phy-cells = <0>;
ae6a32d2 817 };
e9831967 818 };
ed7f8e8a
RQ		 819
820 usbhstll: usbhstll@4a062000 {
821 compatible = "ti,usbhs-tll";
822 reg = <0x4a062000 0x1000>;
823 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
824 ti,hwmods = "usb_tll_hs";
825 };
826
827 usbhshost: usbhshost@4a064000 {
828 compatible = "ti,usbhs-host";
829 reg = <0x4a064000 0x800>;
830 ti,hwmods = "usb_host_hs";
831 #address-cells = <1>;
832 #size-cells = <1>;
833 ranges;
051fc06d
RQ		 834 clocks = <&l3init_60m_fclk>,
835 <&xclk60mhsp1_ck>,
836 <&xclk60mhsp2_ck>;
837 clock-names = "refclk_60m_int",
838 "refclk_60m_ext_p1",
839 "refclk_60m_ext_p2";
ed7f8e8a
RQ		 840
841 usbhsohci: ohci@4a064800 {
a2525e54 842 compatible = "ti,ohci-omap3";
ed7f8e8a
RQ		 843 reg = <0x4a064800 0x400>;
844 interrupt-parent = <&gic>;
845 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
846 };
847
848 usbhsehci: ehci@4a064c00 {
a2525e54 849 compatible = "ti,ehci-omap";
ed7f8e8a
RQ		 850 reg = <0x4a064c00 0x400>;
851 interrupt-parent = <&gic>;
852 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
853 };
854 };
cbad26db 855
1b761fc5 856 bandgap: bandgap@4a0021e0 {
cbad26db
EV		 857 reg = <0x4a0021e0 0xc
858 0x4a00232c 0xc
859 0x4a002380 0x2c
860 0x4a0023C0 0x3c>;
861 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
862 compatible = "ti,omap5430-bandgap";
1b761fc5
EV		 863
864 #thermal-sensor-cells = <1>;
cbad26db 865 };
6b5de091
S		 866 };
867};
85dc74e9
TK		 868
869/include/ "omap54xx-clocks.dtsi"
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