]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - arch/arm/boot/dts/omap5.dtsi
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
dt-bindings: arm,gic: Fix binding example for a virt-capable GIC
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / omap5.dtsi
CommitLineData
6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
6b5de091 14/ {
98cc4544
TL		 15 #address-cells = <2>;
16 #size-cells = <2>;
ba1829bc 17
6b5de091 18 compatible = "ti,omap5";
7136d457 19 interrupt-parent = <&wakeupgen>;
c9faa84c 20 chosen { };
6b5de091
S		 21
22 aliases {
20b80942
NM		 23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
6b5de091
S		 28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
eeb25fd5
LP		 37 #address-cells = <1>;
38 #size-cells = <0>;
39
b8981d71 40 cpu0: cpu@0 {
eeb25fd5 41 device_type = "cpu";
6b5de091 42 compatible = "arm,cortex-a15";
eeb25fd5 43 reg = <0x0>;
6c24894d
K		 44
45 operating-points = <
46 /* kHz uV */
6c24894d
K		 47 1000000 1060000
48 1500000 1250000
49 >;
8d766fa2
NM		 50
51 clocks = <&dpll_mpu_ck>;
52 clock-names = "cpu";
53
54 clock-latency = <300000>; /* From omap-cpufreq driver */
55
2cd29f63
EV		 56 /* cooling options */
57 cooling-min-level = <0>;
58 cooling-max-level = <2>;
59 #cooling-cells = <2>; /* min followed by max */
6b5de091
S		 60 };
61 cpu@1 {
eeb25fd5 62 device_type = "cpu";
6b5de091 63 compatible = "arm,cortex-a15";
eeb25fd5 64 reg = <0x1>;
6b5de091
S		 65 };
66 };
67
1b761fc5
EV		 68 thermal-zones {
69 #include "omap4-cpu-thermal.dtsi"
70 #include "omap5-gpu-thermal.dtsi"
71 #include "omap5-core-thermal.dtsi"
72 };
73
b45ccc4e
SS		 74 timer {
75 compatible = "arm,armv7-timer";
8fea7d5a
FV		 76 /* PPI secure/nonsecure IRQ */
77 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
78 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
7136d457 81 interrupt-parent = <&gic>;
b45ccc4e
SS		 82 };
83
69a126cb
NL		 84 pmu {
85 compatible = "arm,cortex-a15-pmu";
86 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
88 };
89
ba1829bc
SS		 90 gic: interrupt-controller@48211000 {
91 compatible = "arm,cortex-a15-gic";
92 interrupt-controller;
93 #interrupt-cells = <3>;
98cc4544
TL		 94 reg = <0 0x48211000 0 0x1000>,
95 <0 0x48212000 0 0x1000>,
96 <0 0x48214000 0 0x2000>,
97 <0 0x48216000 0 0x2000>;
7136d457
MZ		 98 interrupt-parent = <&gic>;
99 };
100
101 wakeupgen: interrupt-controller@48281000 {
102 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
103 interrupt-controller;
104 #interrupt-cells = <3>;
98cc4544 105 reg = <0 0x48281000 0 0x1000>;
7136d457 106 interrupt-parent = <&gic>;
ba1829bc
SS		 107 };
108
6b5de091 109 /*
5c5be9db 110 * The soc node represents the soc top level view. It is used for IPs
6b5de091
S		 111 * that are not memory mapped in the MPU view or for the MPU itself.
112 */
113 soc {
114 compatible = "ti,omap-infra";
115 mpu {
1306c08a 116 compatible = "ti,omap4-mpu";
6b5de091 117 ti,hwmods = "mpu";
1306c08a 118 sram = <&ocmcram>;
6b5de091
S		 119 };
120 };
121
122 /*
123 * XXX: Use a flat representation of the OMAP3 interconnect.
124 * The real OMAP interconnect network is quite complex.
b7ab524b 125 * Since it will not bring real advantage to represent that in DT for
6b5de091
S		 126 * the moment, just use a fake OCP bus entry to represent the whole bus
127 * hierarchy.
128 */
129 ocp {
e7309c26 130 compatible = "ti,omap5-l3-noc", "simple-bus";
6b5de091
S		 131 #address-cells = <1>;
132 #size-cells = <1>;
98cc4544 133 ranges = <0 0 0 0xc0000000>;
6b5de091 134 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
98cc4544
TL		 135 reg = <0 0x44000000 0 0x2000>,
136 <0 0x44800000 0 0x3000>,
137 <0 0x45000000 0 0x4000>;
8fea7d5a
FV		 138 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 140
ed8509ed
TK		 141 l4_cfg: l4@4a000000 {
142 compatible = "ti,omap5-l4-cfg", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 ranges = <0 0x4a000000 0x22a000>;
85dc74e9 146
ed8509ed
TK		 147 scm_core: scm@2000 {
148 compatible = "ti,omap5-scm-core", "simple-bus";
149 reg = <0x2000 0x1000>;
85dc74e9 150 #address-cells = <1>;
ed8509ed
TK		 151 #size-cells = <1>;
152 ranges = <0 0x2000 0x800>;
153
154 scm_conf: scm_conf@0 {
155 compatible = "syscon";
156 reg = <0x0 0x800>;
157 #address-cells = <1>;
158 #size-cells = <1>;
159 };
85dc74e9
TK		 160 };
161
ed8509ed
TK		 162 scm_padconf_core: scm@2800 {
163 compatible = "ti,omap5-scm-padconf-core",
164 "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges = <0 0x2800 0x800>;
168
169 omap5_pmx_core: pinmux@40 {
170 compatible = "ti,omap5-padconf",
171 "pinctrl-single";
172 reg = <0x40 0x01b6>;
173 #address-cells = <1>;
174 #size-cells = <0>;
be76fd31 175 #pinctrl-cells = <1>;
ed8509ed
TK		 176 #interrupt-cells = <1>;
177 interrupt-controller;
178 pinctrl-single,register-width = <16>;
179 pinctrl-single,function-mask = <0x7fff>;
180 };
181
182 omap5_padconf_global: omap5_padconf_global@5a0 {
70caac3f
KVA		 183 compatible = "syscon",
184 "simple-bus";
ed8509ed
TK		 185 reg = <0x5a0 0xec>;
186 #address-cells = <1>;
187 #size-cells = <1>;
9a5e3f27 188 ranges = <0 0x5a0 0xec>;
ed8509ed 189
308cfdaf 190 pbias_regulator: pbias_regulator@60 {
737f146f 191 compatible = "ti,pbias-omap5", "ti,pbias-omap";
ed8509ed
TK		 192 reg = <0x60 0x4>;
193 syscon = <&omap5_padconf_global>;
194 pbias_mmc_reg: pbias_mmc_omap5 {
195 regulator-name = "pbias_mmc_omap5";
196 regulator-min-microvolt = <1800000>;
197 regulator-max-microvolt = <3000000>;
198 };
199 };
200 };
85dc74e9 201 };
85dc74e9 202
ed8509ed
TK		 203 cm_core_aon: cm_core_aon@4000 {
204 compatible = "ti,omap5-cm-core-aon";
205 reg = <0x4000 0x2000>;
85dc74e9 206
ed8509ed
TK		 207 cm_core_aon_clocks: clocks {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 };
85dc74e9 211
ed8509ed
TK		 212 cm_core_aon_clockdomains: clockdomains {
213 };
85dc74e9 214 };
85dc74e9 215
ed8509ed
TK		 216 cm_core: cm_core@8000 {
217 compatible = "ti,omap5-cm-core";
218 reg = <0x8000 0x3000>;
85dc74e9 219
ed8509ed
TK		 220 cm_core_clocks: clocks {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 };
85dc74e9 224
ed8509ed
TK		 225 cm_core_clockdomains: clockdomains {
226 };
85dc74e9
TK		 227 };
228 };
229
ed8509ed
TK		 230 l4_wkup: l4@4ae00000 {
231 compatible = "ti,omap5-l4-wkup", "simple-bus";
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges = <0 0x4ae00000 0x2b000>;
85dc74e9 235
ed8509ed
TK		 236 counter32k: counter@4000 {
237 compatible = "ti,omap-counter32k";
238 reg = <0x4000 0x40>;
239 ti,hwmods = "counter_32k";
85dc74e9
TK		 240 };
241
ed8509ed
TK		 242 prm: prm@6000 {
243 compatible = "ti,omap5-prm";
244 reg = <0x6000 0x3000>;
245 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
246
247 prm_clocks: clocks {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 };
251
252 prm_clockdomains: clockdomains {
253 };
85dc74e9 254 };
85dc74e9 255
ed8509ed
TK		 256 scrm: scrm@a000 {
257 compatible = "ti,omap5-scrm";
258 reg = <0xa000 0x2000>;
3b3132f7 259
ed8509ed
TK		 260 scrm_clocks: clocks {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 };
5da6a2d5 264
ed8509ed
TK		 265 scrm_clockdomains: clockdomains {
266 };
267 };
cd042fe5 268
ed8509ed
TK		 269 omap5_pmx_wkup: pinmux@c840 {
270 compatible = "ti,omap5-padconf",
271 "pinctrl-single";
7472931f 272 reg = <0xc840 0x003c>;
ed8509ed
TK		 273 #address-cells = <1>;
274 #size-cells = <0>;
be76fd31 275 #pinctrl-cells = <1>;
ed8509ed
TK		 276 #interrupt-cells = <1>;
277 interrupt-controller;
278 pinctrl-single,register-width = <16>;
279 pinctrl-single,function-mask = <0x7fff>;
cd042fe5
B		 280 };
281 };
282
8b9a2810
RN		 283 ocmcram: ocmcram@40300000 {
284 compatible = "mmio-sram";
285 reg = <0x40300000 0x20000>; /* 128k */
286 };
287
2c2dc545
JH		 288 sdma: dma-controller@4a056000 {
289 compatible = "ti,omap4430-sdma";
290 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 291 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545 295 #dma-cells = <1>;
951c1c04
PU		 296 dma-channels = <32>;
297 dma-requests = <127>;
2c2dc545
JH		 298 };
299
6b5de091
S		 300 gpio1: gpio@4ae10000 {
301 compatible = "ti,omap4-gpio";
f4b224f2 302 reg = <0x4ae10000 0x200>;
8fea7d5a 303 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 304 ti,hwmods = "gpio1";
e4b9b9f3 305 ti,gpio-always-on;
6b5de091
S		 306 gpio-controller;
307 #gpio-cells = <2>;
308 interrupt-controller;
ff5c9059 309 #interrupt-cells = <2>;
6b5de091
S		 310 };
311
312 gpio2: gpio@48055000 {
313 compatible = "ti,omap4-gpio";
f4b224f2 314 reg = <0x48055000 0x200>;
8fea7d5a 315 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 316 ti,hwmods = "gpio2";
317 gpio-controller;
318 #gpio-cells = <2>;
319 interrupt-controller;
ff5c9059 320 #interrupt-cells = <2>;
6b5de091
S		 321 };
322
323 gpio3: gpio@48057000 {
324 compatible = "ti,omap4-gpio";
f4b224f2 325 reg = <0x48057000 0x200>;
8fea7d5a 326 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 327 ti,hwmods = "gpio3";
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-controller;
ff5c9059 331 #interrupt-cells = <2>;
6b5de091
S		 332 };
333
334 gpio4: gpio@48059000 {
335 compatible = "ti,omap4-gpio";
f4b224f2 336 reg = <0x48059000 0x200>;
8fea7d5a 337 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 338 ti,hwmods = "gpio4";
339 gpio-controller;
340 #gpio-cells = <2>;
341 interrupt-controller;
ff5c9059 342 #interrupt-cells = <2>;
6b5de091
S		 343 };
344
345 gpio5: gpio@4805b000 {
346 compatible = "ti,omap4-gpio";
f4b224f2 347 reg = <0x4805b000 0x200>;
8fea7d5a 348 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 349 ti,hwmods = "gpio5";
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
ff5c9059 353 #interrupt-cells = <2>;
6b5de091
S		 354 };
355
356 gpio6: gpio@4805d000 {
357 compatible = "ti,omap4-gpio";
f4b224f2 358 reg = <0x4805d000 0x200>;
8fea7d5a 359 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 360 ti,hwmods = "gpio6";
361 gpio-controller;
362 #gpio-cells = <2>;
363 interrupt-controller;
ff5c9059 364 #interrupt-cells = <2>;
6b5de091
S		 365 };
366
367 gpio7: gpio@48051000 {
368 compatible = "ti,omap4-gpio";
f4b224f2 369 reg = <0x48051000 0x200>;
8fea7d5a 370 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 371 ti,hwmods = "gpio7";
372 gpio-controller;
373 #gpio-cells = <2>;
374 interrupt-controller;
ff5c9059 375 #interrupt-cells = <2>;
6b5de091
S		 376 };
377
378 gpio8: gpio@48053000 {
379 compatible = "ti,omap4-gpio";
f4b224f2 380 reg = <0x48053000 0x200>;
8fea7d5a 381 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 382 ti,hwmods = "gpio8";
383 gpio-controller;
384 #gpio-cells = <2>;
385 interrupt-controller;
ff5c9059 386 #interrupt-cells = <2>;
6b5de091
S		 387 };
388
1c7dbb55
JH		 389 gpmc: gpmc@50000000 {
390 compatible = "ti,omap4430-gpmc";
391 reg = <0x50000000 0x1000>;
392 #address-cells = <2>;
393 #size-cells = <1>;
8fea7d5a 394 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
201c7e33
FCJ		 395 dmas = <&sdma 4>;
396 dma-names = "rxtx";
1c7dbb55
JH		 397 gpmc,num-cs = <8>;
398 gpmc,num-waitpins = <4>;
399 ti,hwmods = "gpmc";
7b8b6af1
FV		 400 clocks = <&l3_iclk_div>;
401 clock-names = "fck";
e99d413f
RQ		 402 interrupt-controller;
403 #interrupt-cells = <2>;
404 gpio-controller;
405 #gpio-cells = <2>;
1c7dbb55
JH		 406 };
407
6e6a9a50
SP		 408 i2c1: i2c@48070000 {
409 compatible = "ti,omap4-i2c";
d7118bbd 410 reg = <0x48070000 0x100>;
8fea7d5a 411 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 412 #address-cells = <1>;
413 #size-cells = <0>;
414 ti,hwmods = "i2c1";
415 };
416
417 i2c2: i2c@48072000 {
418 compatible = "ti,omap4-i2c";
d7118bbd 419 reg = <0x48072000 0x100>;
8fea7d5a 420 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 421 #address-cells = <1>;
422 #size-cells = <0>;
423 ti,hwmods = "i2c2";
424 };
425
426 i2c3: i2c@48060000 {
427 compatible = "ti,omap4-i2c";
d7118bbd 428 reg = <0x48060000 0x100>;
8fea7d5a 429 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 430 #address-cells = <1>;
431 #size-cells = <0>;
432 ti,hwmods = "i2c3";
433 };
434
d7118bbd 435 i2c4: i2c@4807a000 {
6e6a9a50 436 compatible = "ti,omap4-i2c";
d7118bbd 437 reg = <0x4807a000 0x100>;
8fea7d5a 438 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 439 #address-cells = <1>;
440 #size-cells = <0>;
441 ti,hwmods = "i2c4";
442 };
443
d7118bbd 444 i2c5: i2c@4807c000 {
6e6a9a50 445 compatible = "ti,omap4-i2c";
d7118bbd 446 reg = <0x4807c000 0x100>;
8fea7d5a 447 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 448 #address-cells = <1>;
449 #size-cells = <0>;
450 ti,hwmods = "i2c5";
451 };
452
fe0e09e4
SA		 453 hwspinlock: spinlock@4a0f6000 {
454 compatible = "ti,omap4-hwspinlock";
455 reg = <0x4a0f6000 0x1000>;
456 ti,hwmods = "spinlock";
34054213 457 #hwlock-cells = <1>;
fe0e09e4
SA		 458 };
459
43286b11
FB		 460 mcspi1: spi@48098000 {
461 compatible = "ti,omap4-mcspi";
462 reg = <0x48098000 0x200>;
8fea7d5a 463 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 464 #address-cells = <1>;
465 #size-cells = <0>;
466 ti,hwmods = "mcspi1";
467 ti,spi-num-cs = <4>;
2c2dc545
JH		 468 dmas = <&sdma 35>,
469 <&sdma 36>,
470 <&sdma 37>,
471 <&sdma 38>,
472 <&sdma 39>,
473 <&sdma 40>,
474 <&sdma 41>,
475 <&sdma 42>;
476 dma-names = "tx0", "rx0", "tx1", "rx1",
477 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 478 };
479
480 mcspi2: spi@4809a000 {
481 compatible = "ti,omap4-mcspi";
482 reg = <0x4809a000 0x200>;
8fea7d5a 483 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 484 #address-cells = <1>;
485 #size-cells = <0>;
486 ti,hwmods = "mcspi2";
487 ti,spi-num-cs = <2>;
2c2dc545
JH		 488 dmas = <&sdma 43>,
489 <&sdma 44>,
490 <&sdma 45>,
491 <&sdma 46>;
492 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 493 };
494
495 mcspi3: spi@480b8000 {
496 compatible = "ti,omap4-mcspi";
497 reg = <0x480b8000 0x200>;
8fea7d5a 498 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 499 #address-cells = <1>;
500 #size-cells = <0>;
501 ti,hwmods = "mcspi3";
502 ti,spi-num-cs = <2>;
2c2dc545
JH		 503 dmas = <&sdma 15>, <&sdma 16>;
504 dma-names = "tx0", "rx0";
43286b11
FB		 505 };
506
507 mcspi4: spi@480ba000 {
508 compatible = "ti,omap4-mcspi";
509 reg = <0x480ba000 0x200>;
8fea7d5a 510 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 511 #address-cells = <1>;
512 #size-cells = <0>;
513 ti,hwmods = "mcspi4";
514 ti,spi-num-cs = <1>;
2c2dc545
JH		 515 dmas = <&sdma 70>, <&sdma 71>;
516 dma-names = "tx0", "rx0";
43286b11
FB		 517 };
518
6b5de091
S		 519 uart1: serial@4806a000 {
520 compatible = "ti,omap4-uart";
8e80f660 521 reg = <0x4806a000 0x100>;
7136d457 522 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 523 ti,hwmods = "uart1";
524 clock-frequency = <48000000>;
525 };
526
527 uart2: serial@4806c000 {
528 compatible = "ti,omap4-uart";
8e80f660 529 reg = <0x4806c000 0x100>;
7136d457 530 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 531 ti,hwmods = "uart2";
532 clock-frequency = <48000000>;
533 };
534
535 uart3: serial@48020000 {
536 compatible = "ti,omap4-uart";
8e80f660 537 reg = <0x48020000 0x100>;
7136d457 538 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 539 ti,hwmods = "uart3";
540 clock-frequency = <48000000>;
541 };
542
543 uart4: serial@4806e000 {
544 compatible = "ti,omap4-uart";
8e80f660 545 reg = <0x4806e000 0x100>;
7136d457 546 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 547 ti,hwmods = "uart4";
548 clock-frequency = <48000000>;
549 };
550
551 uart5: serial@48066000 {
8e80f660
SG		 552 compatible = "ti,omap4-uart";
553 reg = <0x48066000 0x100>;
7136d457 554 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 555 ti,hwmods = "uart5";
556 clock-frequency = <48000000>;
557 };
558
559 uart6: serial@48068000 {
8e80f660
SG		 560 compatible = "ti,omap4-uart";
561 reg = <0x48068000 0x100>;
7136d457 562 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 563 ti,hwmods = "uart6";
564 clock-frequency = <48000000>;
565 };
5dd18b01
B		 566
567 mmc1: mmc@4809c000 {
568 compatible = "ti,omap4-hsmmc";
9a642362 569 reg = <0x4809c000 0x400>;
8fea7d5a 570 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 571 ti,hwmods = "mmc1";
572 ti,dual-volt;
573 ti,needs-special-reset;
2c2dc545
JH		 574 dmas = <&sdma 61>, <&sdma 62>;
575 dma-names = "tx", "rx";
cd042fe5 576 pbias-supply = <&pbias_mmc_reg>;
5dd18b01
B		 577 };
578
579 mmc2: mmc@480b4000 {
580 compatible = "ti,omap4-hsmmc";
9a642362 581 reg = <0x480b4000 0x400>;
8fea7d5a 582 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 583 ti,hwmods = "mmc2";
584 ti,needs-special-reset;
2c2dc545
JH		 585 dmas = <&sdma 47>, <&sdma 48>;
586 dma-names = "tx", "rx";
5dd18b01
B		 587 };
588
589 mmc3: mmc@480ad000 {
590 compatible = "ti,omap4-hsmmc";
9a642362 591 reg = <0x480ad000 0x400>;
8fea7d5a 592 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 593 ti,hwmods = "mmc3";
594 ti,needs-special-reset;
2c2dc545
JH		 595 dmas = <&sdma 77>, <&sdma 78>;
596 dma-names = "tx", "rx";
5dd18b01
B		 597 };
598
599 mmc4: mmc@480d1000 {
600 compatible = "ti,omap4-hsmmc";
9a642362 601 reg = <0x480d1000 0x400>;
8fea7d5a 602 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 603 ti,hwmods = "mmc4";
604 ti,needs-special-reset;
2c2dc545
JH		 605 dmas = <&sdma 57>, <&sdma 58>;
606 dma-names = "tx", "rx";
5dd18b01
B		 607 };
608
609 mmc5: mmc@480d5000 {
610 compatible = "ti,omap4-hsmmc";
9a642362 611 reg = <0x480d5000 0x400>;
8fea7d5a 612 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 613 ti,hwmods = "mmc5";
614 ti,needs-special-reset;
2c2dc545
JH		 615 dmas = <&sdma 59>, <&sdma 60>;
616 dma-names = "tx", "rx";
5dd18b01 617 };
5449fbc2 618
2dcfa56e
SA		 619 mmu_dsp: mmu@4a066000 {
620 compatible = "ti,omap4-iommu";
621 reg = <0x4a066000 0x100>;
622 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
623 ti,hwmods = "mmu_dsp";
c1b5d0f6 624 #iommu-cells = <0>;
2dcfa56e
SA		 625 };
626
627 mmu_ipu: mmu@55082000 {
628 compatible = "ti,omap4-iommu";
629 reg = <0x55082000 0x100>;
630 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
631 ti,hwmods = "mmu_ipu";
c1b5d0f6 632 #iommu-cells = <0>;
2dcfa56e
SA		 633 ti,iommu-bus-err-back;
634 };
635
5449fbc2
SP		 636 keypad: keypad@4ae1c000 {
637 compatible = "ti,omap4-keypad";
8cc8b89f 638 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 639 ti,hwmods = "kbd";
640 };
ffd5db24 641
cbb57f07
PU		 642 mcpdm: mcpdm@40132000 {
643 compatible = "ti,omap4-mcpdm";
644 reg = <0x40132000 0x7f>, /* MPU private access */
645 <0x49032000 0x7f>; /* L3 Interconnect */
646 reg-names = "mpu", "dma";
8fea7d5a 647 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 648 ti,hwmods = "mcpdm";
4e4ead73
SG		 649 dmas = <&sdma 65>,
650 <&sdma 66>;
651 dma-names = "up_link", "dn_link";
f15534ea 652 status = "disabled";
cbb57f07
PU		 653 };
654
655 dmic: dmic@4012e000 {
656 compatible = "ti,omap4-dmic";
657 reg = <0x4012e000 0x7f>, /* MPU private access */
658 <0x4902e000 0x7f>; /* L3 Interconnect */
659 reg-names = "mpu", "dma";
8fea7d5a 660 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 661 ti,hwmods = "dmic";
4e4ead73
SG		 662 dmas = <&sdma 67>;
663 dma-names = "up_link";
f15534ea 664 status = "disabled";
cbb57f07
PU		 665 };
666
ffd5db24
PU		 667 mcbsp1: mcbsp@40122000 {
668 compatible = "ti,omap4-mcbsp";
669 reg = <0x40122000 0xff>, /* MPU private access */
670 <0x49022000 0xff>; /* L3 Interconnect */
671 reg-names = "mpu", "dma";
8fea7d5a 672 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 673 interrupt-names = "common";
ffd5db24
PU		 674 ti,buffer-size = <128>;
675 ti,hwmods = "mcbsp1";
4e4ead73
SG		 676 dmas = <&sdma 33>,
677 <&sdma 34>;
678 dma-names = "tx", "rx";
f15534ea 679 status = "disabled";
ffd5db24
PU		 680 };
681
682 mcbsp2: mcbsp@40124000 {
683 compatible = "ti,omap4-mcbsp";
684 reg = <0x40124000 0xff>, /* MPU private access */
685 <0x49024000 0xff>; /* L3 Interconnect */
686 reg-names = "mpu", "dma";
8fea7d5a 687 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 688 interrupt-names = "common";
ffd5db24
PU		 689 ti,buffer-size = <128>;
690 ti,hwmods = "mcbsp2";
4e4ead73
SG		 691 dmas = <&sdma 17>,
692 <&sdma 18>;
693 dma-names = "tx", "rx";
f15534ea 694 status = "disabled";
ffd5db24
PU		 695 };
696
697 mcbsp3: mcbsp@40126000 {
698 compatible = "ti,omap4-mcbsp";
699 reg = <0x40126000 0xff>, /* MPU private access */
700 <0x49026000 0xff>; /* L3 Interconnect */
701 reg-names = "mpu", "dma";
8fea7d5a 702 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 703 interrupt-names = "common";
ffd5db24
PU		 704 ti,buffer-size = <128>;
705 ti,hwmods = "mcbsp3";
4e4ead73
SG		 706 dmas = <&sdma 19>,
707 <&sdma 20>;
708 dma-names = "tx", "rx";
f15534ea 709 status = "disabled";
ffd5db24 710 };
df692a92 711
84d89c31
SA		 712 mailbox: mailbox@4a0f4000 {
713 compatible = "ti,omap4-mailbox";
714 reg = <0x4a0f4000 0x200>;
715 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
716 ti,hwmods = "mailbox";
24df0453 717 #mbox-cells = <1>;
41ffada1
SA		 718 ti,mbox-num-users = <3>;
719 ti,mbox-num-fifos = <8>;
d27704d1
SA		 720 mbox_ipu: mbox_ipu {
721 ti,mbox-tx = <0 0 0>;
722 ti,mbox-rx = <1 0 0>;
723 };
724 mbox_dsp: mbox_dsp {
725 ti,mbox-tx = <3 0 0>;
726 ti,mbox-rx = <2 0 0>;
727 };
84d89c31
SA		 728 };
729
df692a92 730 timer1: timer@4ae18000 {
002e1ec5 731 compatible = "ti,omap5430-timer";
df692a92 732 reg = <0x4ae18000 0x80>;
8fea7d5a 733 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 734 ti,hwmods = "timer1";
735 ti,timer-alwon;
736 };
737
738 timer2: timer@48032000 {
002e1ec5 739 compatible = "ti,omap5430-timer";
df692a92 740 reg = <0x48032000 0x80>;
8fea7d5a 741 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 742 ti,hwmods = "timer2";
743 };
744
745 timer3: timer@48034000 {
002e1ec5 746 compatible = "ti,omap5430-timer";
df692a92 747 reg = <0x48034000 0x80>;
8fea7d5a 748 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 749 ti,hwmods = "timer3";
750 };
751
752 timer4: timer@48036000 {
002e1ec5 753 compatible = "ti,omap5430-timer";
df692a92 754 reg = <0x48036000 0x80>;
8fea7d5a 755 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 756 ti,hwmods = "timer4";
757 };
758
759 timer5: timer@40138000 {
002e1ec5 760 compatible = "ti,omap5430-timer";
df692a92
JH		 761 reg = <0x40138000 0x80>,
762 <0x49038000 0x80>;
8fea7d5a 763 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 764 ti,hwmods = "timer5";
765 ti,timer-dsp;
8341613a 766 ti,timer-pwm;
df692a92
JH		 767 };
768
769 timer6: timer@4013a000 {
002e1ec5 770 compatible = "ti,omap5430-timer";
df692a92
JH		 771 reg = <0x4013a000 0x80>,
772 <0x4903a000 0x80>;
8fea7d5a 773 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 774 ti,hwmods = "timer6";
775 ti,timer-dsp;
776 ti,timer-pwm;
777 };
778
779 timer7: timer@4013c000 {
002e1ec5 780 compatible = "ti,omap5430-timer";
df692a92
JH		 781 reg = <0x4013c000 0x80>,
782 <0x4903c000 0x80>;
8fea7d5a 783 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 784 ti,hwmods = "timer7";
785 ti,timer-dsp;
786 };
787
788 timer8: timer@4013e000 {
002e1ec5 789 compatible = "ti,omap5430-timer";
df692a92
JH		 790 reg = <0x4013e000 0x80>,
791 <0x4903e000 0x80>;
8fea7d5a 792 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 793 ti,hwmods = "timer8";
794 ti,timer-dsp;
795 ti,timer-pwm;
796 };
797
798 timer9: timer@4803e000 {
002e1ec5 799 compatible = "ti,omap5430-timer";
df692a92 800 reg = <0x4803e000 0x80>;
8fea7d5a 801 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 802 ti,hwmods = "timer9";
8341613a 803 ti,timer-pwm;
df692a92
JH		 804 };
805
806 timer10: timer@48086000 {
002e1ec5 807 compatible = "ti,omap5430-timer";
df692a92 808 reg = <0x48086000 0x80>;
8fea7d5a 809 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 810 ti,hwmods = "timer10";
8341613a 811 ti,timer-pwm;
df692a92
JH		 812 };
813
814 timer11: timer@48088000 {
002e1ec5 815 compatible = "ti,omap5430-timer";
df692a92 816 reg = <0x48088000 0x80>;
8fea7d5a 817 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 818 ti,hwmods = "timer11";
819 ti,timer-pwm;
820 };
e6900ddf 821
55452197
LV		 822 wdt2: wdt@4ae14000 {
823 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
824 reg = <0x4ae14000 0x80>;
8fea7d5a 825 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 826 ti,hwmods = "wd_timer2";
827 };
828
1a5fe3ca
AT		 829 dmm@4e000000 {
830 compatible = "ti,omap5-dmm";
831 reg = <0x4e000000 0x800>;
832 interrupts = <0 113 0x4>;
833 ti,hwmods = "dmm";
834 };
835
8906d654 836 emif1: emif@4c000000 {
e6900ddf
LV		 837 compatible = "ti,emif-4d5";
838 ti,hwmods = "emif1";
f12ecbe2 839 ti,no-idle-on-init;
e6900ddf
LV		 840 phy-type = <2>; /* DDR PHY type: Intelli PHY */
841 reg = <0x4c000000 0x400>;
8fea7d5a 842 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 843 hw-caps-read-idle-ctrl;
844 hw-caps-ll-interface;
845 hw-caps-temp-alert;
846 };
847
8906d654 848 emif2: emif@4d000000 {
e6900ddf
LV		 849 compatible = "ti,emif-4d5";
850 ti,hwmods = "emif2";
f12ecbe2 851 ti,no-idle-on-init;
e6900ddf
LV		 852 phy-type = <2>; /* DDR PHY type: Intelli PHY */
853 reg = <0x4d000000 0x400>;
8fea7d5a 854 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 855 hw-caps-read-idle-ctrl;
856 hw-caps-ll-interface;
857 hw-caps-temp-alert;
858 };
fedc428e 859
e3a412c9 860 usb3: omap_dwc3@4a020000 {
72f6f957
KVA		 861 compatible = "ti,dwc3";
862 ti,hwmods = "usb_otg_ss";
6f61ee23 863 reg = <0x4a020000 0x10000>;
8fea7d5a 864 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 865 #address-cells = <1>;
866 #size-cells = <1>;
867 utmi-mode = <2>;
868 ranges;
952a5db0 869 dwc3: dwc3@4a030000 {
22a5aa17 870 compatible = "snps,dwc3";
6f61ee23 871 reg = <0x4a030000 0x10000>;
8d33c093
RQ		 872 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
873 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
874 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
875 interrupt-names = "peripheral",
876 "host",
877 "otg";
073addc8
KVA		 878 phys = <&usb2_phy>, <&usb3_phy>;
879 phy-names = "usb2-phy", "usb3-phy";
c47ee6ee 880 dr_mode = "peripheral";
72f6f957
KVA		 881 };
882 };
883
b6731f78 884 ocp2scp@4a080000 {
e9831967
KVA		 885 compatible = "ti,omap-ocp2scp";
886 #address-cells = <1>;
887 #size-cells = <1>;
b6731f78 888 reg = <0x4a080000 0x20>;
e9831967
KVA		 889 ranges;
890 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 891 usb2_phy: usb2phy@4a084000 {
892 compatible = "ti,omap-usb2";
893 reg = <0x4a084000 0x7c>;
2338c76a 894 syscon-phy-power = <&scm_conf 0x300>;
c65d0ad5
RQ		 895 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
896 clock-names = "wkupclk", "refclk";
073addc8 897 #phy-cells = <0>;
ae6a32d2
KVA		 898 };
899
900 usb3_phy: usb3phy@4a084400 {
901 compatible = "ti,omap-usb3";
902 reg = <0x4a084400 0x80>,
903 <0x4a084800 0x64>,
904 <0x4a084c00 0x40>;
905 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
2338c76a 906 syscon-phy-power = <&scm_conf 0x370>;
ada76576
RQ		 907 clocks = <&usb_phy_cm_clk32k>,
908 <&sys_clkin>,
909 <&usb_otg_ss_refclk960m>;
910 clock-names = "wkupclk",
911 "sysclk",
912 "refclk";
073addc8 913 #phy-cells = <0>;
ae6a32d2 914 };
e9831967 915 };
ed7f8e8a
RQ		 916
917 usbhstll: usbhstll@4a062000 {
918 compatible = "ti,usbhs-tll";
919 reg = <0x4a062000 0x1000>;
920 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
921 ti,hwmods = "usb_tll_hs";
922 };
923
924 usbhshost: usbhshost@4a064000 {
925 compatible = "ti,usbhs-host";
926 reg = <0x4a064000 0x800>;
927 ti,hwmods = "usb_host_hs";
928 #address-cells = <1>;
929 #size-cells = <1>;
930 ranges;
051fc06d
RQ		 931 clocks = <&l3init_60m_fclk>,
932 <&xclk60mhsp1_ck>,
933 <&xclk60mhsp2_ck>;
934 clock-names = "refclk_60m_int",
935 "refclk_60m_ext_p1",
936 "refclk_60m_ext_p2";
ed7f8e8a
RQ		 937
938 usbhsohci: ohci@4a064800 {
a2525e54 939 compatible = "ti,ohci-omap3";
ed7f8e8a 940 reg = <0x4a064800 0x400>;
ed7f8e8a
RQ		 941 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
942 };
943
944 usbhsehci: ehci@4a064c00 {
a2525e54 945 compatible = "ti,ehci-omap";
ed7f8e8a 946 reg = <0x4a064c00 0x400>;
ed7f8e8a
RQ		 947 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
948 };
949 };
cbad26db 950
1b761fc5 951 bandgap: bandgap@4a0021e0 {
cbad26db
EV		 952 reg = <0x4a0021e0 0xc
953 0x4a00232c 0xc
954 0x4a002380 0x2c
955 0x4a0023C0 0x3c>;
956 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
957 compatible = "ti,omap5430-bandgap";
1b761fc5
EV		 958
959 #thermal-sensor-cells = <1>;
cbad26db 960 };
4f82952c 961
4f82952c
B		 962 /* OCP2SCP3 */
963 ocp2scp@4a090000 {
964 compatible = "ti,omap-ocp2scp";
965 #address-cells = <1>;
966 #size-cells = <1>;
967 reg = <0x4a090000 0x20>;
968 ranges;
969 ti,hwmods = "ocp2scp3";
970 sata_phy: phy@4a096000 {
971 compatible = "ti,phy-pipe3-sata";
972 reg = <0x4A096000 0x80>, /* phy_rx */
973 <0x4A096400 0x64>, /* phy_tx */
974 <0x4A096800 0x40>; /* pll_ctrl */
975 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
2338c76a 976 syscon-phy-power = <&scm_conf 0x374>;
a0182724
RQ		 977 clocks = <&sys_clkin>, <&sata_ref_clk>;
978 clock-names = "sysclk", "refclk";
4f82952c
B		 979 #phy-cells = <0>;
980 };
981 };
982
983 sata: sata@4a141100 {
984 compatible = "snps,dwc-ahci";
985 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
986 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
987 phys = <&sata_phy>;
988 phy-names = "sata-phy";
989 clocks = <&sata_ref_clk>;
990 ti,hwmods = "sata";
991 };
992
e7585c4f
TV		 993 dss: dss@58000000 {
994 compatible = "ti,omap5-dss";
995 reg = <0x58000000 0x80>;
996 status = "disabled";
997 ti,hwmods = "dss_core";
998 clocks = <&dss_dss_clk>;
999 clock-names = "fck";
1000 #address-cells = <1>;
1001 #size-cells = <1>;
1002 ranges;
1003
1004 dispc@58001000 {
1005 compatible = "ti,omap5-dispc";
1006 reg = <0x58001000 0x1000>;
1007 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1008 ti,hwmods = "dss_dispc";
1009 clocks = <&dss_dss_clk>;
1010 clock-names = "fck";
1011 };
1012
84ace674
TV		 1013 rfbi: encoder@58002000 {
1014 compatible = "ti,omap5-rfbi";
1015 reg = <0x58002000 0x100>;
1016 status = "disabled";
1017 ti,hwmods = "dss_rfbi";
1018 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1019 clock-names = "fck", "ick";
1020 };
1021
e7585c4f
TV		 1022 dsi1: encoder@58004000 {
1023 compatible = "ti,omap5-dsi";
1024 reg = <0x58004000 0x200>,
1025 <0x58004200 0x40>,
1026 <0x58004300 0x40>;
1027 reg-names = "proto", "phy", "pll";
1028 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1029 status = "disabled";
1030 ti,hwmods = "dss_dsi1";
1031 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1032 clock-names = "fck", "sys_clk";
1033 };
1034
1035 dsi2: encoder@58005000 {
1036 compatible = "ti,omap5-dsi";
1037 reg = <0x58009000 0x200>,
1038 <0x58009200 0x40>,
1039 <0x58009300 0x40>;
1040 reg-names = "proto", "phy", "pll";
1041 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1042 status = "disabled";
1043 ti,hwmods = "dss_dsi2";
1044 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1045 clock-names = "fck", "sys_clk";
1046 };
1047
1048 hdmi: encoder@58060000 {
1049 compatible = "ti,omap5-hdmi";
1050 reg = <0x58040000 0x200>,
1051 <0x58040200 0x80>,
1052 <0x58040300 0x80>,
1053 <0x58060000 0x19000>;
1054 reg-names = "wp", "pll", "phy", "core";
1055 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1056 status = "disabled";
1057 ti,hwmods = "dss_hdmi";
1058 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1059 clock-names = "fck", "sys_clk";
7d0fde39
JS		 1060 dmas = <&sdma 76>;
1061 dma-names = "audio_tx";
e7585c4f
TV		 1062 };
1063 };
07b9b3d9
AT		 1064
1065 abb_mpu: regulator-abb-mpu {
1066 compatible = "ti,abb-v2";
1067 regulator-name = "abb_mpu";
1068 #address-cells = <0>;
1069 #size-cells = <0>;
1070 clocks = <&sys_clkin>;
1071 ti,settling-time = <50>;
1072 ti,clock-cycles = <16>;
1073
1074 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1075 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1076 reg-names = "base-address", "int-address",
1077 "efuse-address", "ldo-address";
1078 ti,tranxdone-status-mask = <0x80>;
1079 /* LDOVBBMPU_MUX_CTRL */
1080 ti,ldovbb-override-mask = <0x400>;
1081 /* LDOVBBMPU_VSET_OUT */
1082 ti,ldovbb-vset-mask = <0x1F>;
1083
1084 /*
1085 * NOTE: only FBB mode used but actual vset will
1086 * determine final biasing
1087 */
1088 ti,abb_info = <
1089 /*uV ABB efuse rbb_m fbb_m vset_m*/
1090 1060000 0 0x0 0 0x02000000 0x01F00000
1091 1250000 0 0x4 0 0x02000000 0x01F00000
1092 >;
1093 };
1094
1095 abb_mm: regulator-abb-mm {
1096 compatible = "ti,abb-v2";
1097 regulator-name = "abb_mm";
1098 #address-cells = <0>;
1099 #size-cells = <0>;
1100 clocks = <&sys_clkin>;
1101 ti,settling-time = <50>;
1102 ti,clock-cycles = <16>;
1103
1104 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1105 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1106 reg-names = "base-address", "int-address",
1107 "efuse-address", "ldo-address";
1108 ti,tranxdone-status-mask = <0x80000000>;
1109 /* LDOVBBMM_MUX_CTRL */
1110 ti,ldovbb-override-mask = <0x400>;
1111 /* LDOVBBMM_VSET_OUT */
1112 ti,ldovbb-vset-mask = <0x1F>;
1113
1114 /*
1115 * NOTE: only FBB mode used but actual vset will
1116 * determine final biasing
1117 */
1118 ti,abb_info = <
1119 /*uV ABB efuse rbb_m fbb_m vset_m*/
1120 1025000 0 0x0 0 0x02000000 0x01F00000
1121 1120000 0 0x4 0 0x02000000 0x01F00000
1122 >;
1123 };
6b5de091
S		 1124 };
1125};
85dc74e9 1126
38f5c8ba
TK		 1127&cpu_thermal {
1128 polling-delay = <500>; /* milliseconds */
1129};
1130
85dc74e9 1131/include/ "omap54xx-clocks.dtsi"
Ubuntu Hirsute Linux kernel mirror