[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / omap5.dtsi

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

#include <dt-bindings/gpio/gpio.h>

#include "skeleton.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "ti,omap5";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a15";
		};
		cpu@1 {
			compatible = "arm,cortex-a15";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		/* PPI secure/nonsecure IRQ, active low level-sensitive */
		interrupts = <1 13 0x308>,
			     <1 14 0x308>,
			     <1 11 0x308>,
			     <1 10 0x308>;
		clock-frequency = <6144000>;
	};

	gic: interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48211000 0x1000>,
		      <0x48212000 0x1000>,
		      <0x48214000 0x2000>,
		      <0x48216000 0x2000>;
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
		reg = <0x44000000 0x2000>,
		      <0x44800000 0x3000>,
		      <0x45000000 0x4000>;
		interrupts = <0 9 0x4>,
			     <0 10 0x4>;

		counter32k: counter@4ae04000 {
			compatible = "ti,omap-counter32k";
			reg = <0x4ae04000 0x40>;
			ti,hwmods = "counter_32k";
		};

		omap5_pmx_core: pinmux@4a002840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4a002840 0x01b6>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};
		omap5_pmx_wkup: pinmux@4ae0c840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4ae0c840 0x0038>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};

		sdma: dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
			interrupts = <0 12 0x4>,
				     <0 13 0x4>,
				     <0 14 0x4>,
				     <0 15 0x4>;
			#dma-cells = <1>;
			#dma-channels = <32>;
			#dma-requests = <127>;
		};

		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4ae10000 0x200>;
			interrupts = <0 29 0x4>;
			ti,hwmods = "gpio1";
			ti,gpio-always-on;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <0 30 0x4>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <0 31 0x4>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <0 32 0x4>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <0 33 0x4>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <0 34 0x4>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48051000 0x200>;
			interrupts = <0 35 0x4>;
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48053000 0x200>;
			interrupts = <0 121 0x4>;
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,omap4430-gpmc";
			reg = <0x50000000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <0 20 0x4>;
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			ti,hwmods = "gpmc";
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <0 56 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <0 57 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <0 61 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		i2c4: i2c@4807a000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807a000 0x100>;
			interrupts = <0 62 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

		i2c5: i2c@4807c000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807c000 0x100>;
			interrupts = <0 60 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
			interrupts = <0 65 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
			dmas = <&sdma 35>,
			       <&sdma 36>,
			       <&sdma 37>,
			       <&sdma 38>,
			       <&sdma 39>,
			       <&sdma 40>,
			       <&sdma 41>,
			       <&sdma 42>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
			interrupts = <0 66 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 43>,
			       <&sdma 44>,
			       <&sdma 45>,
			       <&sdma 46>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
			interrupts = <0 91 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 15>, <&sdma 16>;
			dma-names = "tx0", "rx0";
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
			interrupts = <0 48 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
			dmas = <&sdma 70>, <&sdma 71>;
			dma-names = "tx0", "rx0";
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts = <0 72 0x4>;
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <0 73 0x4>;
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <0 74 0x4>;
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <0 70 0x4>;
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		uart5: serial@48066000 {
			compatible = "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <0 105 0x4>;
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
		};

		uart6: serial@48068000 {
			compatible = "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <0 106 0x4>;
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x4809c000 0x400>;
			interrupts = <0 83 0x4>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480b4000 0x400>;
			interrupts = <0 86 0x4>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480ad000 0x400>;
			interrupts = <0 94 0x4>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			dmas = <&sdma 77>, <&sdma 78>;
			dma-names = "tx", "rx";
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d1000 0x400>;
			interrupts = <0 96 0x4>;
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
			dmas = <&sdma 57>, <&sdma 58>;
			dma-names = "tx", "rx";
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d5000 0x400>;
			interrupts = <0 59 0x4>;
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
			dmas = <&sdma 59>, <&sdma 60>;
			dma-names = "tx", "rx";
		};

		keypad: keypad@4ae1c000 {
			compatible = "ti,omap4-keypad";
			reg = <0x4ae1c000 0x400>;
			ti,hwmods = "kbd";
		};

		mcpdm: mcpdm@40132000 {
			compatible = "ti,omap4-mcpdm";
			reg = <0x40132000 0x7f>, /* MPU private access */
			      <0x49032000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 112 0x4>;
			ti,hwmods = "mcpdm";
			dmas = <&sdma 65>,
			       <&sdma 66>;
			dma-names = "up_link", "dn_link";
		};

		dmic: dmic@4012e000 {
			compatible = "ti,omap4-dmic";
			reg = <0x4012e000 0x7f>, /* MPU private access */
			      <0x4902e000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 114 0x4>;
			ti,hwmods = "dmic";
			dmas = <&sdma 67>;
			dma-names = "up_link";
		};

		mcbsp1: mcbsp@40122000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40122000 0xff>, /* MPU private access */
			      <0x49022000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 17 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
			dmas = <&sdma 33>,
			       <&sdma 34>;
			dma-names = "tx", "rx";
		};

		mcbsp2: mcbsp@40124000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40124000 0xff>, /* MPU private access */
			      <0x49024000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 22 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
			dmas = <&sdma 17>,
			       <&sdma 18>;
			dma-names = "tx", "rx";
		};

		mcbsp3: mcbsp@40126000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40126000 0xff>, /* MPU private access */
			      <0x49026000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 23 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
			dmas = <&sdma 19>,
			       <&sdma 20>;
			dma-names = "tx", "rx";
		};

		timer1: timer@4ae18000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4ae18000 0x80>;
			interrupts = <0 37 0x4>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48032000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48032000 0x80>;
			interrupts = <0 38 0x4>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48034000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48034000 0x80>;
			interrupts = <0 39 0x4>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48036000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48036000 0x80>;
			interrupts = <0 40 0x4>;
			ti,hwmods = "timer4";
		};

		timer5: timer@40138000 {
			compatible = "ti,omap5430-timer";
			reg = <0x40138000 0x80>,
			      <0x49038000 0x80>;
			interrupts = <0 41 0x4>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer6: timer@4013a000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013a000 0x80>,
			      <0x4903a000 0x80>;
			interrupts = <0 42 0x4>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer7: timer@4013c000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013c000 0x80>,
			      <0x4903c000 0x80>;
			interrupts = <0 43 0x4>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@4013e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013e000 0x80>,
			      <0x4903e000 0x80>;
			interrupts = <0 44 0x4>;
			ti,hwmods = "timer8";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer9: timer@4803e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <0 45 0x4>;
			ti,hwmods = "timer9";
			ti,timer-pwm;
		};

		timer10: timer@48086000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48086000 0x80>;
			interrupts = <0 46 0x4>;
			ti,hwmods = "timer10";
			ti,timer-pwm;
		};

		timer11: timer@48088000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48088000 0x80>;
			interrupts = <0 47 0x4>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};

		wdt2: wdt@4ae14000 {
			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
			reg = <0x4ae14000 0x80>;
			interrupts = <0 80 0x4>;
			ti,hwmods = "wd_timer2";
		};

		emif1: emif@0x4c000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif1";
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4c000000 0x400>;
			interrupts = <0 110 0x4>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		emif2: emif@0x4d000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif2";
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4d000000 0x400>;
			interrupts = <0 111 0x4>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		omap_control_usb: omap-control-usb@4a002300 {
			compatible = "ti,omap-control-usb";
			reg = <0x4a002300 0x4>,
			      <0x4a002370 0x4>;
			reg-names = "control_dev_conf", "phy_power_usb";
			ti,type = <2>;
		};

		omap_dwc3@4a020000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss";
			reg = <0x4a020000 0x1000>;
			interrupts = <0 93 4>;
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <2>;
			ranges;
			dwc3@4a030000 {
				compatible = "synopsys,dwc3";
				reg = <0x4a030000 0x1000>;
				interrupts = <0 92 4>;
				usb-phy = <&usb2_phy>, <&usb3_phy>;
				tx-fifo-resize;
			};
		};

		ocp2scp {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "ocp2scp1";
			usb2_phy: usb2phy@4a084000 {
				compatible = "ti,omap-usb2";
				reg = <0x4a084000 0x7c>;
				ctrl-module = <&omap_control_usb>;
			};

			usb3_phy: usb3phy@4a084400 {
				compatible = "ti,omap-usb3";
				reg = <0x4a084400 0x80>,
				      <0x4a084800 0x64>,
				      <0x4a084c00 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				ctrl-module = <&omap_control_usb>;
			};
		};
	};
};
Commit	Line	Data
6b5de091 S	1	/*
	2	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	* Based on "omap4.dtsi"
	8	*/
	9
6d624eab FV	10	#include <dt-bindings/gpio/gpio.h>
6d624eab FV	11
98ef7957	12	#include "skeleton.dtsi"
6b5de091 S	13
6b5de091 S	14	/ {
ba1829bc SS	15	#address-cells = <1>;
	16	#size-cells = <1>;
	17
6b5de091 S	18	compatible = "ti,omap5";
	19	interrupt-parent = <&gic>;
	20
	21	aliases {
	22	serial0 = &uart1;
	23	serial1 = &uart2;
	24	serial2 = &uart3;
	25	serial3 = &uart4;
	26	serial4 = &uart5;
	27	serial5 = &uart6;
	28	};
	29
	30	cpus {
	31	cpu@0 {
	32	compatible = "arm,cortex-a15";
	33	};
	34	cpu@1 {
	35	compatible = "arm,cortex-a15";
	36	};
	37	};
	38
b45ccc4e SS	39	timer {
b45ccc4e SS	40	compatible = "arm,armv7-timer";
1496c15b RN	41	/* PPI secure/nonsecure IRQ, active low level-sensitive */
1496c15b RN	42	interrupts = <1 13 0x308>,
0129c16c SS	43	<1 14 0x308>,
	44	<1 11 0x308>,
	45	<1 10 0x308>;
b45ccc4e SS	46	clock-frequency = <6144000>;
	47	};
	48
ba1829bc SS	49	gic: interrupt-controller@48211000 {
	50	compatible = "arm,cortex-a15-gic";
	51	interrupt-controller;
	52	#interrupt-cells = <3>;
	53	reg = <0x48211000 0x1000>,
0129c16c SS	54	<0x48212000 0x1000>,
	55	<0x48214000 0x2000>,
	56	<0x48216000 0x2000>;
ba1829bc SS	57	};
ba1829bc SS	58
6b5de091 S	59	/*
	60	* The soc node represents the soc top level view. It is uses for IPs
	61	* that are not memory mapped in the MPU view or for the MPU itself.
	62	*/
	63	soc {
	64	compatible = "ti,omap-infra";
	65	mpu {
	66	compatible = "ti,omap5-mpu";
	67	ti,hwmods = "mpu";
	68	};
	69	};
	70
	71	/*
	72	* XXX: Use a flat representation of the OMAP3 interconnect.
	73	* The real OMAP interconnect network is quite complex.
	74	* Since that will not bring real advantage to represent that in DT for
	75	* the moment, just use a fake OCP bus entry to represent the whole bus
	76	* hierarchy.
	77	*/
	78	ocp {
	79	compatible = "ti,omap4-l3-noc", "simple-bus";
	80	#address-cells = <1>;
	81	#size-cells = <1>;
	82	ranges;
	83	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa SS	84	reg = <0x44000000 0x2000>,
	85	<0x44800000 0x3000>,
	86	<0x45000000 0x4000>;
	87	interrupts = <0 9 0x4>,
	88	<0 10 0x4>;
6b5de091	89
3b3132f7 JH	90	counter32k: counter@4ae04000 {
	91	compatible = "ti,omap-counter32k";
	92	reg = <0x4ae04000 0x40>;
	93	ti,hwmods = "counter_32k";
	94	};
	95
5da6a2d5 PU	96	omap5_pmx_core: pinmux@4a002840 {
	97	compatible = "ti,omap4-padconf", "pinctrl-single";
	98	reg = <0x4a002840 0x01b6>;
	99	#address-cells = <1>;
	100	#size-cells = <0>;
	101	pinctrl-single,register-width = <16>;
	102	pinctrl-single,function-mask = <0x7fff>;
	103	};
	104	omap5_pmx_wkup: pinmux@4ae0c840 {
	105	compatible = "ti,omap4-padconf", "pinctrl-single";
	106	reg = <0x4ae0c840 0x0038>;
	107	#address-cells = <1>;
	108	#size-cells = <0>;
	109	pinctrl-single,register-width = <16>;
	110	pinctrl-single,function-mask = <0x7fff>;
	111	};
	112
2c2dc545 JH	113	sdma: dma-controller@4a056000 {
	114	compatible = "ti,omap4430-sdma";
	115	reg = <0x4a056000 0x1000>;
	116	interrupts = <0 12 0x4>,
	117	<0 13 0x4>,
	118	<0 14 0x4>,
	119	<0 15 0x4>;
	120	#dma-cells = <1>;
	121	#dma-channels = <32>;
	122	#dma-requests = <127>;
	123	};
	124
6b5de091 S	125	gpio1: gpio@4ae10000 {
6b5de091 S	126	compatible = "ti,omap4-gpio";
f4b224f2 SG	127	reg = <0x4ae10000 0x200>;
f4b224f2 SG	128	interrupts = <0 29 0x4>;
6b5de091	129	ti,hwmods = "gpio1";
e4b9b9f3	130	ti,gpio-always-on;
6b5de091 S	131	gpio-controller;
	132	#gpio-cells = <2>;
	133	interrupt-controller;
ff5c9059	134	#interrupt-cells = <2>;
6b5de091 S	135	};
	136
	137	gpio2: gpio@48055000 {
	138	compatible = "ti,omap4-gpio";
f4b224f2 SG	139	reg = <0x48055000 0x200>;
f4b224f2 SG	140	interrupts = <0 30 0x4>;
6b5de091 S	141	ti,hwmods = "gpio2";
	142	gpio-controller;
	143	#gpio-cells = <2>;
	144	interrupt-controller;
ff5c9059	145	#interrupt-cells = <2>;
6b5de091 S	146	};
	147
	148	gpio3: gpio@48057000 {
	149	compatible = "ti,omap4-gpio";
f4b224f2 SG	150	reg = <0x48057000 0x200>;
f4b224f2 SG	151	interrupts = <0 31 0x4>;
6b5de091 S	152	ti,hwmods = "gpio3";
	153	gpio-controller;
	154	#gpio-cells = <2>;
	155	interrupt-controller;
ff5c9059	156	#interrupt-cells = <2>;
6b5de091 S	157	};
	158
	159	gpio4: gpio@48059000 {
	160	compatible = "ti,omap4-gpio";
f4b224f2 SG	161	reg = <0x48059000 0x200>;
f4b224f2 SG	162	interrupts = <0 32 0x4>;
6b5de091 S	163	ti,hwmods = "gpio4";
	164	gpio-controller;
	165	#gpio-cells = <2>;
	166	interrupt-controller;
ff5c9059	167	#interrupt-cells = <2>;
6b5de091 S	168	};
	169
	170	gpio5: gpio@4805b000 {
	171	compatible = "ti,omap4-gpio";
f4b224f2 SG	172	reg = <0x4805b000 0x200>;
f4b224f2 SG	173	interrupts = <0 33 0x4>;
6b5de091 S	174	ti,hwmods = "gpio5";
	175	gpio-controller;
	176	#gpio-cells = <2>;
	177	interrupt-controller;
ff5c9059	178	#interrupt-cells = <2>;
6b5de091 S	179	};
	180
	181	gpio6: gpio@4805d000 {
	182	compatible = "ti,omap4-gpio";
f4b224f2 SG	183	reg = <0x4805d000 0x200>;
f4b224f2 SG	184	interrupts = <0 34 0x4>;
6b5de091 S	185	ti,hwmods = "gpio6";
	186	gpio-controller;
	187	#gpio-cells = <2>;
	188	interrupt-controller;
ff5c9059	189	#interrupt-cells = <2>;
6b5de091 S	190	};
	191
	192	gpio7: gpio@48051000 {
	193	compatible = "ti,omap4-gpio";
f4b224f2 SG	194	reg = <0x48051000 0x200>;
f4b224f2 SG	195	interrupts = <0 35 0x4>;
6b5de091 S	196	ti,hwmods = "gpio7";
	197	gpio-controller;
	198	#gpio-cells = <2>;
	199	interrupt-controller;
ff5c9059	200	#interrupt-cells = <2>;
6b5de091 S	201	};
	202
	203	gpio8: gpio@48053000 {
	204	compatible = "ti,omap4-gpio";
f4b224f2 SG	205	reg = <0x48053000 0x200>;
f4b224f2 SG	206	interrupts = <0 121 0x4>;
6b5de091 S	207	ti,hwmods = "gpio8";
	208	gpio-controller;
	209	#gpio-cells = <2>;
	210	interrupt-controller;
ff5c9059	211	#interrupt-cells = <2>;
6b5de091 S	212	};
6b5de091 S	213
1c7dbb55 JH	214	gpmc: gpmc@50000000 {
	215	compatible = "ti,omap4430-gpmc";
	216	reg = <0x50000000 0x1000>;
	217	#address-cells = <2>;
	218	#size-cells = <1>;
	219	interrupts = <0 20 0x4>;
	220	gpmc,num-cs = <8>;
	221	gpmc,num-waitpins = <4>;
	222	ti,hwmods = "gpmc";
	223	};
	224
6e6a9a50 SP	225	i2c1: i2c@48070000 {
6e6a9a50 SP	226	compatible = "ti,omap4-i2c";
d7118bbd SG	227	reg = <0x48070000 0x100>;
d7118bbd SG	228	interrupts = <0 56 0x4>;
6e6a9a50 SP	229	#address-cells = <1>;
	230	#size-cells = <0>;
	231	ti,hwmods = "i2c1";
	232	};
	233
	234	i2c2: i2c@48072000 {
	235	compatible = "ti,omap4-i2c";
d7118bbd SG	236	reg = <0x48072000 0x100>;
d7118bbd SG	237	interrupts = <0 57 0x4>;
6e6a9a50 SP	238	#address-cells = <1>;
	239	#size-cells = <0>;
	240	ti,hwmods = "i2c2";
	241	};
	242
	243	i2c3: i2c@48060000 {
	244	compatible = "ti,omap4-i2c";
d7118bbd SG	245	reg = <0x48060000 0x100>;
d7118bbd SG	246	interrupts = <0 61 0x4>;
6e6a9a50 SP	247	#address-cells = <1>;
	248	#size-cells = <0>;
	249	ti,hwmods = "i2c3";
	250	};
	251
d7118bbd	252	i2c4: i2c@4807a000 {
6e6a9a50	253	compatible = "ti,omap4-i2c";
d7118bbd SG	254	reg = <0x4807a000 0x100>;
d7118bbd SG	255	interrupts = <0 62 0x4>;
6e6a9a50 SP	256	#address-cells = <1>;
	257	#size-cells = <0>;
	258	ti,hwmods = "i2c4";
	259	};
	260
d7118bbd	261	i2c5: i2c@4807c000 {
6e6a9a50	262	compatible = "ti,omap4-i2c";
d7118bbd SG	263	reg = <0x4807c000 0x100>;
d7118bbd SG	264	interrupts = <0 60 0x4>;
6e6a9a50 SP	265	#address-cells = <1>;
	266	#size-cells = <0>;
	267	ti,hwmods = "i2c5";
	268	};
	269
43286b11 FB	270	mcspi1: spi@48098000 {
	271	compatible = "ti,omap4-mcspi";
	272	reg = <0x48098000 0x200>;
	273	interrupts = <0 65 0x4>;
	274	#address-cells = <1>;
	275	#size-cells = <0>;
	276	ti,hwmods = "mcspi1";
	277	ti,spi-num-cs = <4>;
2c2dc545 JH	278	dmas = <&sdma 35>,
	279	<&sdma 36>,
	280	<&sdma 37>,
	281	<&sdma 38>,
	282	<&sdma 39>,
	283	<&sdma 40>,
	284	<&sdma 41>,
	285	<&sdma 42>;
	286	dma-names = "tx0", "rx0", "tx1", "rx1",
	287	"tx2", "rx2", "tx3", "rx3";
43286b11 FB	288	};
	289
	290	mcspi2: spi@4809a000 {
	291	compatible = "ti,omap4-mcspi";
	292	reg = <0x4809a000 0x200>;
	293	interrupts = <0 66 0x4>;
	294	#address-cells = <1>;
	295	#size-cells = <0>;
	296	ti,hwmods = "mcspi2";
	297	ti,spi-num-cs = <2>;
2c2dc545 JH	298	dmas = <&sdma 43>,
	299	<&sdma 44>,
	300	<&sdma 45>,
	301	<&sdma 46>;
	302	dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11 FB	303	};
	304
	305	mcspi3: spi@480b8000 {
	306	compatible = "ti,omap4-mcspi";
	307	reg = <0x480b8000 0x200>;
	308	interrupts = <0 91 0x4>;
	309	#address-cells = <1>;
	310	#size-cells = <0>;
	311	ti,hwmods = "mcspi3";
	312	ti,spi-num-cs = <2>;
2c2dc545 JH	313	dmas = <&sdma 15>, <&sdma 16>;
2c2dc545 JH	314	dma-names = "tx0", "rx0";
43286b11 FB	315	};
	316
	317	mcspi4: spi@480ba000 {
	318	compatible = "ti,omap4-mcspi";
	319	reg = <0x480ba000 0x200>;
	320	interrupts = <0 48 0x4>;
	321	#address-cells = <1>;
	322	#size-cells = <0>;
	323	ti,hwmods = "mcspi4";
	324	ti,spi-num-cs = <1>;
2c2dc545 JH	325	dmas = <&sdma 70>, <&sdma 71>;
2c2dc545 JH	326	dma-names = "tx0", "rx0";
43286b11 FB	327	};
43286b11 FB	328
6b5de091 S	329	uart1: serial@4806a000 {
6b5de091 S	330	compatible = "ti,omap4-uart";
8e80f660 SG	331	reg = <0x4806a000 0x100>;
8e80f660 SG	332	interrupts = <0 72 0x4>;
6b5de091 S	333	ti,hwmods = "uart1";
	334	clock-frequency = <48000000>;
	335	};
	336
	337	uart2: serial@4806c000 {
	338	compatible = "ti,omap4-uart";
8e80f660 SG	339	reg = <0x4806c000 0x100>;
8e80f660 SG	340	interrupts = <0 73 0x4>;
6b5de091 S	341	ti,hwmods = "uart2";
	342	clock-frequency = <48000000>;
	343	};
	344
	345	uart3: serial@48020000 {
	346	compatible = "ti,omap4-uart";
8e80f660 SG	347	reg = <0x48020000 0x100>;
8e80f660 SG	348	interrupts = <0 74 0x4>;
6b5de091 S	349	ti,hwmods = "uart3";
	350	clock-frequency = <48000000>;
	351	};
	352
	353	uart4: serial@4806e000 {
	354	compatible = "ti,omap4-uart";
8e80f660 SG	355	reg = <0x4806e000 0x100>;
8e80f660 SG	356	interrupts = <0 70 0x4>;
6b5de091 S	357	ti,hwmods = "uart4";
	358	clock-frequency = <48000000>;
	359	};
	360
	361	uart5: serial@48066000 {
8e80f660 SG	362	compatible = "ti,omap4-uart";
	363	reg = <0x48066000 0x100>;
	364	interrupts = <0 105 0x4>;
6b5de091 S	365	ti,hwmods = "uart5";
	366	clock-frequency = <48000000>;
	367	};
	368
	369	uart6: serial@48068000 {
8e80f660 SG	370	compatible = "ti,omap4-uart";
	371	reg = <0x48068000 0x100>;
	372	interrupts = <0 106 0x4>;
6b5de091 S	373	ti,hwmods = "uart6";
	374	clock-frequency = <48000000>;
	375	};
5dd18b01 B	376
	377	mmc1: mmc@4809c000 {
	378	compatible = "ti,omap4-hsmmc";
9a642362 SG	379	reg = <0x4809c000 0x400>;
9a642362 SG	380	interrupts = <0 83 0x4>;
5dd18b01 B	381	ti,hwmods = "mmc1";
	382	ti,dual-volt;
	383	ti,needs-special-reset;
2c2dc545 JH	384	dmas = <&sdma 61>, <&sdma 62>;
2c2dc545 JH	385	dma-names = "tx", "rx";
5dd18b01 B	386	};
	387
	388	mmc2: mmc@480b4000 {
	389	compatible = "ti,omap4-hsmmc";
9a642362 SG	390	reg = <0x480b4000 0x400>;
9a642362 SG	391	interrupts = <0 86 0x4>;
5dd18b01 B	392	ti,hwmods = "mmc2";
5dd18b01 B	393	ti,needs-special-reset;
2c2dc545 JH	394	dmas = <&sdma 47>, <&sdma 48>;
2c2dc545 JH	395	dma-names = "tx", "rx";
5dd18b01 B	396	};
	397
	398	mmc3: mmc@480ad000 {
	399	compatible = "ti,omap4-hsmmc";
9a642362 SG	400	reg = <0x480ad000 0x400>;
9a642362 SG	401	interrupts = <0 94 0x4>;
5dd18b01 B	402	ti,hwmods = "mmc3";
5dd18b01 B	403	ti,needs-special-reset;
2c2dc545 JH	404	dmas = <&sdma 77>, <&sdma 78>;
2c2dc545 JH	405	dma-names = "tx", "rx";
5dd18b01 B	406	};
	407
	408	mmc4: mmc@480d1000 {
	409	compatible = "ti,omap4-hsmmc";
9a642362 SG	410	reg = <0x480d1000 0x400>;
9a642362 SG	411	interrupts = <0 96 0x4>;
5dd18b01 B	412	ti,hwmods = "mmc4";
5dd18b01 B	413	ti,needs-special-reset;
2c2dc545 JH	414	dmas = <&sdma 57>, <&sdma 58>;
2c2dc545 JH	415	dma-names = "tx", "rx";
5dd18b01 B	416	};
	417
	418	mmc5: mmc@480d5000 {
	419	compatible = "ti,omap4-hsmmc";
9a642362 SG	420	reg = <0x480d5000 0x400>;
9a642362 SG	421	interrupts = <0 59 0x4>;
5dd18b01 B	422	ti,hwmods = "mmc5";
5dd18b01 B	423	ti,needs-special-reset;
2c2dc545 JH	424	dmas = <&sdma 59>, <&sdma 60>;
2c2dc545 JH	425	dma-names = "tx", "rx";
5dd18b01	426	};
5449fbc2 SP	427
	428	keypad: keypad@4ae1c000 {
	429	compatible = "ti,omap4-keypad";
8cc8b89f	430	reg = <0x4ae1c000 0x400>;
5449fbc2 SP	431	ti,hwmods = "kbd";
5449fbc2 SP	432	};
ffd5db24	433
cbb57f07 PU	434	mcpdm: mcpdm@40132000 {
	435	compatible = "ti,omap4-mcpdm";
	436	reg = <0x40132000 0x7f>, /* MPU private access */
	437	<0x49032000 0x7f>; /* L3 Interconnect */
	438	reg-names = "mpu", "dma";
	439	interrupts = <0 112 0x4>;
cbb57f07	440	ti,hwmods = "mcpdm";
4e4ead73 SG	441	dmas = <&sdma 65>,
	442	<&sdma 66>;
	443	dma-names = "up_link", "dn_link";
cbb57f07 PU	444	};
	445
	446	dmic: dmic@4012e000 {
	447	compatible = "ti,omap4-dmic";
	448	reg = <0x4012e000 0x7f>, /* MPU private access */
	449	<0x4902e000 0x7f>; /* L3 Interconnect */
	450	reg-names = "mpu", "dma";
	451	interrupts = <0 114 0x4>;
cbb57f07	452	ti,hwmods = "dmic";
4e4ead73 SG	453	dmas = <&sdma 67>;
4e4ead73 SG	454	dma-names = "up_link";
cbb57f07 PU	455	};
cbb57f07 PU	456
ffd5db24 PU	457	mcbsp1: mcbsp@40122000 {
	458	compatible = "ti,omap4-mcbsp";
	459	reg = <0x40122000 0xff>, /* MPU private access */
	460	<0x49022000 0xff>; /* L3 Interconnect */
	461	reg-names = "mpu", "dma";
	462	interrupts = <0 17 0x4>;
	463	interrupt-names = "common";
ffd5db24 PU	464	ti,buffer-size = <128>;
ffd5db24 PU	465	ti,hwmods = "mcbsp1";
4e4ead73 SG	466	dmas = <&sdma 33>,
	467	<&sdma 34>;
	468	dma-names = "tx", "rx";
ffd5db24 PU	469	};
	470
	471	mcbsp2: mcbsp@40124000 {
	472	compatible = "ti,omap4-mcbsp";
	473	reg = <0x40124000 0xff>, /* MPU private access */
	474	<0x49024000 0xff>; /* L3 Interconnect */
	475	reg-names = "mpu", "dma";
	476	interrupts = <0 22 0x4>;
	477	interrupt-names = "common";
ffd5db24 PU	478	ti,buffer-size = <128>;
ffd5db24 PU	479	ti,hwmods = "mcbsp2";
4e4ead73 SG	480	dmas = <&sdma 17>,
	481	<&sdma 18>;
	482	dma-names = "tx", "rx";
ffd5db24 PU	483	};
	484
	485	mcbsp3: mcbsp@40126000 {
	486	compatible = "ti,omap4-mcbsp";
	487	reg = <0x40126000 0xff>, /* MPU private access */
	488	<0x49026000 0xff>; /* L3 Interconnect */
	489	reg-names = "mpu", "dma";
	490	interrupts = <0 23 0x4>;
	491	interrupt-names = "common";
ffd5db24 PU	492	ti,buffer-size = <128>;
ffd5db24 PU	493	ti,hwmods = "mcbsp3";
4e4ead73 SG	494	dmas = <&sdma 19>,
	495	<&sdma 20>;
	496	dma-names = "tx", "rx";
ffd5db24	497	};
df692a92 JH	498
df692a92 JH	499	timer1: timer@4ae18000 {
002e1ec5	500	compatible = "ti,omap5430-timer";
df692a92 JH	501	reg = <0x4ae18000 0x80>;
	502	interrupts = <0 37 0x4>;
	503	ti,hwmods = "timer1";
	504	ti,timer-alwon;
	505	};
	506
	507	timer2: timer@48032000 {
002e1ec5	508	compatible = "ti,omap5430-timer";
df692a92 JH	509	reg = <0x48032000 0x80>;
	510	interrupts = <0 38 0x4>;
	511	ti,hwmods = "timer2";
	512	};
	513
	514	timer3: timer@48034000 {
002e1ec5	515	compatible = "ti,omap5430-timer";
df692a92 JH	516	reg = <0x48034000 0x80>;
	517	interrupts = <0 39 0x4>;
	518	ti,hwmods = "timer3";
	519	};
	520
	521	timer4: timer@48036000 {
002e1ec5	522	compatible = "ti,omap5430-timer";
df692a92 JH	523	reg = <0x48036000 0x80>;
	524	interrupts = <0 40 0x4>;
	525	ti,hwmods = "timer4";
	526	};
	527
	528	timer5: timer@40138000 {
002e1ec5	529	compatible = "ti,omap5430-timer";
df692a92 JH	530	reg = <0x40138000 0x80>,
	531	<0x49038000 0x80>;
	532	interrupts = <0 41 0x4>;
	533	ti,hwmods = "timer5";
	534	ti,timer-dsp;
8341613a	535	ti,timer-pwm;
df692a92 JH	536	};
	537
	538	timer6: timer@4013a000 {
002e1ec5	539	compatible = "ti,omap5430-timer";
df692a92 JH	540	reg = <0x4013a000 0x80>,
	541	<0x4903a000 0x80>;
	542	interrupts = <0 42 0x4>;
	543	ti,hwmods = "timer6";
	544	ti,timer-dsp;
	545	ti,timer-pwm;
	546	};
	547
	548	timer7: timer@4013c000 {
002e1ec5	549	compatible = "ti,omap5430-timer";
df692a92 JH	550	reg = <0x4013c000 0x80>,
	551	<0x4903c000 0x80>;
	552	interrupts = <0 43 0x4>;
	553	ti,hwmods = "timer7";
	554	ti,timer-dsp;
	555	};
	556
	557	timer8: timer@4013e000 {
002e1ec5	558	compatible = "ti,omap5430-timer";
df692a92 JH	559	reg = <0x4013e000 0x80>,
	560	<0x4903e000 0x80>;
	561	interrupts = <0 44 0x4>;
	562	ti,hwmods = "timer8";
	563	ti,timer-dsp;
	564	ti,timer-pwm;
	565	};
	566
	567	timer9: timer@4803e000 {
002e1ec5	568	compatible = "ti,omap5430-timer";
df692a92 JH	569	reg = <0x4803e000 0x80>;
	570	interrupts = <0 45 0x4>;
	571	ti,hwmods = "timer9";
8341613a	572	ti,timer-pwm;
df692a92 JH	573	};
	574
	575	timer10: timer@48086000 {
002e1ec5	576	compatible = "ti,omap5430-timer";
df692a92 JH	577	reg = <0x48086000 0x80>;
	578	interrupts = <0 46 0x4>;
	579	ti,hwmods = "timer10";
8341613a	580	ti,timer-pwm;
df692a92 JH	581	};
	582
	583	timer11: timer@48088000 {
002e1ec5	584	compatible = "ti,omap5430-timer";
df692a92 JH	585	reg = <0x48088000 0x80>;
	586	interrupts = <0 47 0x4>;
	587	ti,hwmods = "timer11";
	588	ti,timer-pwm;
	589	};
e6900ddf	590
55452197 LV	591	wdt2: wdt@4ae14000 {
	592	compatible = "ti,omap5-wdt", "ti,omap3-wdt";
	593	reg = <0x4ae14000 0x80>;
	594	interrupts = <0 80 0x4>;
	595	ti,hwmods = "wd_timer2";
	596	};
	597
e6900ddf LV	598	emif1: emif@0x4c000000 {
	599	compatible = "ti,emif-4d5";
	600	ti,hwmods = "emif1";
	601	phy-type = <2>; /* DDR PHY type: Intelli PHY */
	602	reg = <0x4c000000 0x400>;
	603	interrupts = <0 110 0x4>;
	604	hw-caps-read-idle-ctrl;
	605	hw-caps-ll-interface;
	606	hw-caps-temp-alert;
	607	};
	608
	609	emif2: emif@0x4d000000 {
	610	compatible = "ti,emif-4d5";
	611	ti,hwmods = "emif2";
	612	phy-type = <2>; /* DDR PHY type: Intelli PHY */
	613	reg = <0x4d000000 0x400>;
	614	interrupts = <0 111 0x4>;
	615	hw-caps-read-idle-ctrl;
	616	hw-caps-ll-interface;
	617	hw-caps-temp-alert;
	618	};
fedc428e KVA	619
	620	omap_control_usb: omap-control-usb@4a002300 {
	621	compatible = "ti,omap-control-usb";
	622	reg = <0x4a002300 0x4>,
	623	<0x4a002370 0x4>;
	624	reg-names = "control_dev_conf", "phy_power_usb";
	625	ti,type = <2>;
	626	};
e9831967	627
72f6f957 KVA	628	omap_dwc3@4a020000 {
	629	compatible = "ti,dwc3";
	630	ti,hwmods = "usb_otg_ss";
	631	reg = <0x4a020000 0x1000>;
	632	interrupts = <0 93 4>;
	633	#address-cells = <1>;
	634	#size-cells = <1>;
	635	utmi-mode = <2>;
	636	ranges;
	637	dwc3@4a030000 {
	638	compatible = "synopsys,dwc3";
	639	reg = <0x4a030000 0x1000>;
	640	interrupts = <0 92 4>;
	641	usb-phy = <&usb2_phy>, <&usb3_phy>;
	642	tx-fifo-resize;
	643	};
	644	};
	645
e9831967 KVA	646	ocp2scp {
	647	compatible = "ti,omap-ocp2scp";
	648	#address-cells = <1>;
	649	#size-cells = <1>;
	650	ranges;
	651	ti,hwmods = "ocp2scp1";
ae6a32d2 KVA	652	usb2_phy: usb2phy@4a084000 {
	653	compatible = "ti,omap-usb2";
	654	reg = <0x4a084000 0x7c>;
	655	ctrl-module = <&omap_control_usb>;
	656	};
	657
	658	usb3_phy: usb3phy@4a084400 {
	659	compatible = "ti,omap-usb3";
	660	reg = <0x4a084400 0x80>,
	661	<0x4a084800 0x64>,
	662	<0x4a084c00 0x40>;
	663	reg-names = "phy_rx", "phy_tx", "pll_ctrl";
	664	ctrl-module = <&omap_control_usb>;
	665	};
e9831967	666	};
6b5de091 S	667	};
6b5de091 S	668	};