]>
Commit | Line | Data |
---|---|---|
6b5de091 S |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
10 | /* | |
11 | * Carveout for multimedia usecases | |
12 | * It should be the last 48MB of the first 512MB memory part | |
13 | * In theory, it should not even exist. That zone should be reserved | |
14 | * dynamically during the .reserve callback. | |
15 | */ | |
16 | /memreserve/ 0x9d000000 0x03000000; | |
17 | ||
18 | /include/ "skeleton.dtsi" | |
19 | ||
20 | / { | |
ba1829bc SS |
21 | #address-cells = <1>; |
22 | #size-cells = <1>; | |
23 | ||
6b5de091 S |
24 | compatible = "ti,omap5"; |
25 | interrupt-parent = <&gic>; | |
26 | ||
27 | aliases { | |
28 | serial0 = &uart1; | |
29 | serial1 = &uart2; | |
30 | serial2 = &uart3; | |
31 | serial3 = &uart4; | |
32 | serial4 = &uart5; | |
33 | serial5 = &uart6; | |
34 | }; | |
35 | ||
36 | cpus { | |
37 | cpu@0 { | |
38 | compatible = "arm,cortex-a15"; | |
39 | }; | |
40 | cpu@1 { | |
41 | compatible = "arm,cortex-a15"; | |
42 | }; | |
43 | }; | |
44 | ||
b45ccc4e SS |
45 | timer { |
46 | compatible = "arm,armv7-timer"; | |
1496c15b RN |
47 | /* PPI secure/nonsecure IRQ, active low level-sensitive */ |
48 | interrupts = <1 13 0x308>, | |
0129c16c SS |
49 | <1 14 0x308>, |
50 | <1 11 0x308>, | |
51 | <1 10 0x308>; | |
b45ccc4e SS |
52 | clock-frequency = <6144000>; |
53 | }; | |
54 | ||
ba1829bc SS |
55 | gic: interrupt-controller@48211000 { |
56 | compatible = "arm,cortex-a15-gic"; | |
57 | interrupt-controller; | |
58 | #interrupt-cells = <3>; | |
59 | reg = <0x48211000 0x1000>, | |
0129c16c SS |
60 | <0x48212000 0x1000>, |
61 | <0x48214000 0x2000>, | |
62 | <0x48216000 0x2000>; | |
ba1829bc SS |
63 | }; |
64 | ||
6b5de091 S |
65 | /* |
66 | * The soc node represents the soc top level view. It is uses for IPs | |
67 | * that are not memory mapped in the MPU view or for the MPU itself. | |
68 | */ | |
69 | soc { | |
70 | compatible = "ti,omap-infra"; | |
71 | mpu { | |
72 | compatible = "ti,omap5-mpu"; | |
73 | ti,hwmods = "mpu"; | |
74 | }; | |
75 | }; | |
76 | ||
77 | /* | |
78 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
79 | * The real OMAP interconnect network is quite complex. | |
80 | * Since that will not bring real advantage to represent that in DT for | |
81 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
82 | * hierarchy. | |
83 | */ | |
84 | ocp { | |
85 | compatible = "ti,omap4-l3-noc", "simple-bus"; | |
86 | #address-cells = <1>; | |
87 | #size-cells = <1>; | |
88 | ranges; | |
89 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | |
20a60eaa SS |
90 | reg = <0x44000000 0x2000>, |
91 | <0x44800000 0x3000>, | |
92 | <0x45000000 0x4000>; | |
93 | interrupts = <0 9 0x4>, | |
94 | <0 10 0x4>; | |
6b5de091 | 95 | |
3b3132f7 JH |
96 | counter32k: counter@4ae04000 { |
97 | compatible = "ti,omap-counter32k"; | |
98 | reg = <0x4ae04000 0x40>; | |
99 | ti,hwmods = "counter_32k"; | |
100 | }; | |
101 | ||
5da6a2d5 PU |
102 | omap5_pmx_core: pinmux@4a002840 { |
103 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
104 | reg = <0x4a002840 0x01b6>; | |
105 | #address-cells = <1>; | |
106 | #size-cells = <0>; | |
107 | pinctrl-single,register-width = <16>; | |
108 | pinctrl-single,function-mask = <0x7fff>; | |
109 | }; | |
110 | omap5_pmx_wkup: pinmux@4ae0c840 { | |
111 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
112 | reg = <0x4ae0c840 0x0038>; | |
113 | #address-cells = <1>; | |
114 | #size-cells = <0>; | |
115 | pinctrl-single,register-width = <16>; | |
116 | pinctrl-single,function-mask = <0x7fff>; | |
117 | }; | |
118 | ||
2c2dc545 JH |
119 | sdma: dma-controller@4a056000 { |
120 | compatible = "ti,omap4430-sdma"; | |
121 | reg = <0x4a056000 0x1000>; | |
122 | interrupts = <0 12 0x4>, | |
123 | <0 13 0x4>, | |
124 | <0 14 0x4>, | |
125 | <0 15 0x4>; | |
126 | #dma-cells = <1>; | |
127 | #dma-channels = <32>; | |
128 | #dma-requests = <127>; | |
129 | }; | |
130 | ||
6b5de091 S |
131 | gpio1: gpio@4ae10000 { |
132 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
133 | reg = <0x4ae10000 0x200>; |
134 | interrupts = <0 29 0x4>; | |
6b5de091 | 135 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 136 | ti,gpio-always-on; |
6b5de091 S |
137 | gpio-controller; |
138 | #gpio-cells = <2>; | |
139 | interrupt-controller; | |
ff5c9059 | 140 | #interrupt-cells = <2>; |
6b5de091 S |
141 | }; |
142 | ||
143 | gpio2: gpio@48055000 { | |
144 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
145 | reg = <0x48055000 0x200>; |
146 | interrupts = <0 30 0x4>; | |
6b5de091 S |
147 | ti,hwmods = "gpio2"; |
148 | gpio-controller; | |
149 | #gpio-cells = <2>; | |
150 | interrupt-controller; | |
ff5c9059 | 151 | #interrupt-cells = <2>; |
6b5de091 S |
152 | }; |
153 | ||
154 | gpio3: gpio@48057000 { | |
155 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
156 | reg = <0x48057000 0x200>; |
157 | interrupts = <0 31 0x4>; | |
6b5de091 S |
158 | ti,hwmods = "gpio3"; |
159 | gpio-controller; | |
160 | #gpio-cells = <2>; | |
161 | interrupt-controller; | |
ff5c9059 | 162 | #interrupt-cells = <2>; |
6b5de091 S |
163 | }; |
164 | ||
165 | gpio4: gpio@48059000 { | |
166 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
167 | reg = <0x48059000 0x200>; |
168 | interrupts = <0 32 0x4>; | |
6b5de091 S |
169 | ti,hwmods = "gpio4"; |
170 | gpio-controller; | |
171 | #gpio-cells = <2>; | |
172 | interrupt-controller; | |
ff5c9059 | 173 | #interrupt-cells = <2>; |
6b5de091 S |
174 | }; |
175 | ||
176 | gpio5: gpio@4805b000 { | |
177 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
178 | reg = <0x4805b000 0x200>; |
179 | interrupts = <0 33 0x4>; | |
6b5de091 S |
180 | ti,hwmods = "gpio5"; |
181 | gpio-controller; | |
182 | #gpio-cells = <2>; | |
183 | interrupt-controller; | |
ff5c9059 | 184 | #interrupt-cells = <2>; |
6b5de091 S |
185 | }; |
186 | ||
187 | gpio6: gpio@4805d000 { | |
188 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
189 | reg = <0x4805d000 0x200>; |
190 | interrupts = <0 34 0x4>; | |
6b5de091 S |
191 | ti,hwmods = "gpio6"; |
192 | gpio-controller; | |
193 | #gpio-cells = <2>; | |
194 | interrupt-controller; | |
ff5c9059 | 195 | #interrupt-cells = <2>; |
6b5de091 S |
196 | }; |
197 | ||
198 | gpio7: gpio@48051000 { | |
199 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
200 | reg = <0x48051000 0x200>; |
201 | interrupts = <0 35 0x4>; | |
6b5de091 S |
202 | ti,hwmods = "gpio7"; |
203 | gpio-controller; | |
204 | #gpio-cells = <2>; | |
205 | interrupt-controller; | |
ff5c9059 | 206 | #interrupt-cells = <2>; |
6b5de091 S |
207 | }; |
208 | ||
209 | gpio8: gpio@48053000 { | |
210 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
211 | reg = <0x48053000 0x200>; |
212 | interrupts = <0 121 0x4>; | |
6b5de091 S |
213 | ti,hwmods = "gpio8"; |
214 | gpio-controller; | |
215 | #gpio-cells = <2>; | |
216 | interrupt-controller; | |
ff5c9059 | 217 | #interrupt-cells = <2>; |
6b5de091 S |
218 | }; |
219 | ||
1c7dbb55 JH |
220 | gpmc: gpmc@50000000 { |
221 | compatible = "ti,omap4430-gpmc"; | |
222 | reg = <0x50000000 0x1000>; | |
223 | #address-cells = <2>; | |
224 | #size-cells = <1>; | |
225 | interrupts = <0 20 0x4>; | |
226 | gpmc,num-cs = <8>; | |
227 | gpmc,num-waitpins = <4>; | |
228 | ti,hwmods = "gpmc"; | |
229 | }; | |
230 | ||
6e6a9a50 SP |
231 | i2c1: i2c@48070000 { |
232 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
233 | reg = <0x48070000 0x100>; |
234 | interrupts = <0 56 0x4>; | |
6e6a9a50 SP |
235 | #address-cells = <1>; |
236 | #size-cells = <0>; | |
237 | ti,hwmods = "i2c1"; | |
238 | }; | |
239 | ||
240 | i2c2: i2c@48072000 { | |
241 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
242 | reg = <0x48072000 0x100>; |
243 | interrupts = <0 57 0x4>; | |
6e6a9a50 SP |
244 | #address-cells = <1>; |
245 | #size-cells = <0>; | |
246 | ti,hwmods = "i2c2"; | |
247 | }; | |
248 | ||
249 | i2c3: i2c@48060000 { | |
250 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
251 | reg = <0x48060000 0x100>; |
252 | interrupts = <0 61 0x4>; | |
6e6a9a50 SP |
253 | #address-cells = <1>; |
254 | #size-cells = <0>; | |
255 | ti,hwmods = "i2c3"; | |
256 | }; | |
257 | ||
d7118bbd | 258 | i2c4: i2c@4807a000 { |
6e6a9a50 | 259 | compatible = "ti,omap4-i2c"; |
d7118bbd SG |
260 | reg = <0x4807a000 0x100>; |
261 | interrupts = <0 62 0x4>; | |
6e6a9a50 SP |
262 | #address-cells = <1>; |
263 | #size-cells = <0>; | |
264 | ti,hwmods = "i2c4"; | |
265 | }; | |
266 | ||
d7118bbd | 267 | i2c5: i2c@4807c000 { |
6e6a9a50 | 268 | compatible = "ti,omap4-i2c"; |
d7118bbd SG |
269 | reg = <0x4807c000 0x100>; |
270 | interrupts = <0 60 0x4>; | |
6e6a9a50 SP |
271 | #address-cells = <1>; |
272 | #size-cells = <0>; | |
273 | ti,hwmods = "i2c5"; | |
274 | }; | |
275 | ||
43286b11 FB |
276 | mcspi1: spi@48098000 { |
277 | compatible = "ti,omap4-mcspi"; | |
278 | reg = <0x48098000 0x200>; | |
279 | interrupts = <0 65 0x4>; | |
280 | #address-cells = <1>; | |
281 | #size-cells = <0>; | |
282 | ti,hwmods = "mcspi1"; | |
283 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
284 | dmas = <&sdma 35>, |
285 | <&sdma 36>, | |
286 | <&sdma 37>, | |
287 | <&sdma 38>, | |
288 | <&sdma 39>, | |
289 | <&sdma 40>, | |
290 | <&sdma 41>, | |
291 | <&sdma 42>; | |
292 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
293 | "tx2", "rx2", "tx3", "rx3"; | |
43286b11 FB |
294 | }; |
295 | ||
296 | mcspi2: spi@4809a000 { | |
297 | compatible = "ti,omap4-mcspi"; | |
298 | reg = <0x4809a000 0x200>; | |
299 | interrupts = <0 66 0x4>; | |
300 | #address-cells = <1>; | |
301 | #size-cells = <0>; | |
302 | ti,hwmods = "mcspi2"; | |
303 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
304 | dmas = <&sdma 43>, |
305 | <&sdma 44>, | |
306 | <&sdma 45>, | |
307 | <&sdma 46>; | |
308 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
43286b11 FB |
309 | }; |
310 | ||
311 | mcspi3: spi@480b8000 { | |
312 | compatible = "ti,omap4-mcspi"; | |
313 | reg = <0x480b8000 0x200>; | |
314 | interrupts = <0 91 0x4>; | |
315 | #address-cells = <1>; | |
316 | #size-cells = <0>; | |
317 | ti,hwmods = "mcspi3"; | |
318 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
319 | dmas = <&sdma 15>, <&sdma 16>; |
320 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
321 | }; |
322 | ||
323 | mcspi4: spi@480ba000 { | |
324 | compatible = "ti,omap4-mcspi"; | |
325 | reg = <0x480ba000 0x200>; | |
326 | interrupts = <0 48 0x4>; | |
327 | #address-cells = <1>; | |
328 | #size-cells = <0>; | |
329 | ti,hwmods = "mcspi4"; | |
330 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
331 | dmas = <&sdma 70>, <&sdma 71>; |
332 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
333 | }; |
334 | ||
6b5de091 S |
335 | uart1: serial@4806a000 { |
336 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
337 | reg = <0x4806a000 0x100>; |
338 | interrupts = <0 72 0x4>; | |
6b5de091 S |
339 | ti,hwmods = "uart1"; |
340 | clock-frequency = <48000000>; | |
341 | }; | |
342 | ||
343 | uart2: serial@4806c000 { | |
344 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
345 | reg = <0x4806c000 0x100>; |
346 | interrupts = <0 73 0x4>; | |
6b5de091 S |
347 | ti,hwmods = "uart2"; |
348 | clock-frequency = <48000000>; | |
349 | }; | |
350 | ||
351 | uart3: serial@48020000 { | |
352 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
353 | reg = <0x48020000 0x100>; |
354 | interrupts = <0 74 0x4>; | |
6b5de091 S |
355 | ti,hwmods = "uart3"; |
356 | clock-frequency = <48000000>; | |
357 | }; | |
358 | ||
359 | uart4: serial@4806e000 { | |
360 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
361 | reg = <0x4806e000 0x100>; |
362 | interrupts = <0 70 0x4>; | |
6b5de091 S |
363 | ti,hwmods = "uart4"; |
364 | clock-frequency = <48000000>; | |
365 | }; | |
366 | ||
367 | uart5: serial@48066000 { | |
8e80f660 SG |
368 | compatible = "ti,omap4-uart"; |
369 | reg = <0x48066000 0x100>; | |
370 | interrupts = <0 105 0x4>; | |
6b5de091 S |
371 | ti,hwmods = "uart5"; |
372 | clock-frequency = <48000000>; | |
373 | }; | |
374 | ||
375 | uart6: serial@48068000 { | |
8e80f660 SG |
376 | compatible = "ti,omap4-uart"; |
377 | reg = <0x48068000 0x100>; | |
378 | interrupts = <0 106 0x4>; | |
6b5de091 S |
379 | ti,hwmods = "uart6"; |
380 | clock-frequency = <48000000>; | |
381 | }; | |
5dd18b01 B |
382 | |
383 | mmc1: mmc@4809c000 { | |
384 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
385 | reg = <0x4809c000 0x400>; |
386 | interrupts = <0 83 0x4>; | |
5dd18b01 B |
387 | ti,hwmods = "mmc1"; |
388 | ti,dual-volt; | |
389 | ti,needs-special-reset; | |
2c2dc545 JH |
390 | dmas = <&sdma 61>, <&sdma 62>; |
391 | dma-names = "tx", "rx"; | |
5dd18b01 B |
392 | }; |
393 | ||
394 | mmc2: mmc@480b4000 { | |
395 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
396 | reg = <0x480b4000 0x400>; |
397 | interrupts = <0 86 0x4>; | |
5dd18b01 B |
398 | ti,hwmods = "mmc2"; |
399 | ti,needs-special-reset; | |
2c2dc545 JH |
400 | dmas = <&sdma 47>, <&sdma 48>; |
401 | dma-names = "tx", "rx"; | |
5dd18b01 B |
402 | }; |
403 | ||
404 | mmc3: mmc@480ad000 { | |
405 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
406 | reg = <0x480ad000 0x400>; |
407 | interrupts = <0 94 0x4>; | |
5dd18b01 B |
408 | ti,hwmods = "mmc3"; |
409 | ti,needs-special-reset; | |
2c2dc545 JH |
410 | dmas = <&sdma 77>, <&sdma 78>; |
411 | dma-names = "tx", "rx"; | |
5dd18b01 B |
412 | }; |
413 | ||
414 | mmc4: mmc@480d1000 { | |
415 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
416 | reg = <0x480d1000 0x400>; |
417 | interrupts = <0 96 0x4>; | |
5dd18b01 B |
418 | ti,hwmods = "mmc4"; |
419 | ti,needs-special-reset; | |
2c2dc545 JH |
420 | dmas = <&sdma 57>, <&sdma 58>; |
421 | dma-names = "tx", "rx"; | |
5dd18b01 B |
422 | }; |
423 | ||
424 | mmc5: mmc@480d5000 { | |
425 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
426 | reg = <0x480d5000 0x400>; |
427 | interrupts = <0 59 0x4>; | |
5dd18b01 B |
428 | ti,hwmods = "mmc5"; |
429 | ti,needs-special-reset; | |
2c2dc545 JH |
430 | dmas = <&sdma 59>, <&sdma 60>; |
431 | dma-names = "tx", "rx"; | |
5dd18b01 | 432 | }; |
5449fbc2 SP |
433 | |
434 | keypad: keypad@4ae1c000 { | |
435 | compatible = "ti,omap4-keypad"; | |
8cc8b89f | 436 | reg = <0x4ae1c000 0x400>; |
5449fbc2 SP |
437 | ti,hwmods = "kbd"; |
438 | }; | |
ffd5db24 | 439 | |
cbb57f07 PU |
440 | mcpdm: mcpdm@40132000 { |
441 | compatible = "ti,omap4-mcpdm"; | |
442 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
443 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
444 | reg-names = "mpu", "dma"; | |
445 | interrupts = <0 112 0x4>; | |
cbb57f07 | 446 | ti,hwmods = "mcpdm"; |
4e4ead73 SG |
447 | dmas = <&sdma 65>, |
448 | <&sdma 66>; | |
449 | dma-names = "up_link", "dn_link"; | |
cbb57f07 PU |
450 | }; |
451 | ||
452 | dmic: dmic@4012e000 { | |
453 | compatible = "ti,omap4-dmic"; | |
454 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
455 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
456 | reg-names = "mpu", "dma"; | |
457 | interrupts = <0 114 0x4>; | |
cbb57f07 | 458 | ti,hwmods = "dmic"; |
4e4ead73 SG |
459 | dmas = <&sdma 67>; |
460 | dma-names = "up_link"; | |
cbb57f07 PU |
461 | }; |
462 | ||
ffd5db24 PU |
463 | mcbsp1: mcbsp@40122000 { |
464 | compatible = "ti,omap4-mcbsp"; | |
465 | reg = <0x40122000 0xff>, /* MPU private access */ | |
466 | <0x49022000 0xff>; /* L3 Interconnect */ | |
467 | reg-names = "mpu", "dma"; | |
468 | interrupts = <0 17 0x4>; | |
469 | interrupt-names = "common"; | |
ffd5db24 PU |
470 | ti,buffer-size = <128>; |
471 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
472 | dmas = <&sdma 33>, |
473 | <&sdma 34>; | |
474 | dma-names = "tx", "rx"; | |
ffd5db24 PU |
475 | }; |
476 | ||
477 | mcbsp2: mcbsp@40124000 { | |
478 | compatible = "ti,omap4-mcbsp"; | |
479 | reg = <0x40124000 0xff>, /* MPU private access */ | |
480 | <0x49024000 0xff>; /* L3 Interconnect */ | |
481 | reg-names = "mpu", "dma"; | |
482 | interrupts = <0 22 0x4>; | |
483 | interrupt-names = "common"; | |
ffd5db24 PU |
484 | ti,buffer-size = <128>; |
485 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
486 | dmas = <&sdma 17>, |
487 | <&sdma 18>; | |
488 | dma-names = "tx", "rx"; | |
ffd5db24 PU |
489 | }; |
490 | ||
491 | mcbsp3: mcbsp@40126000 { | |
492 | compatible = "ti,omap4-mcbsp"; | |
493 | reg = <0x40126000 0xff>, /* MPU private access */ | |
494 | <0x49026000 0xff>; /* L3 Interconnect */ | |
495 | reg-names = "mpu", "dma"; | |
496 | interrupts = <0 23 0x4>; | |
497 | interrupt-names = "common"; | |
ffd5db24 PU |
498 | ti,buffer-size = <128>; |
499 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
500 | dmas = <&sdma 19>, |
501 | <&sdma 20>; | |
502 | dma-names = "tx", "rx"; | |
ffd5db24 | 503 | }; |
df692a92 JH |
504 | |
505 | timer1: timer@4ae18000 { | |
002e1ec5 | 506 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
507 | reg = <0x4ae18000 0x80>; |
508 | interrupts = <0 37 0x4>; | |
509 | ti,hwmods = "timer1"; | |
510 | ti,timer-alwon; | |
511 | }; | |
512 | ||
513 | timer2: timer@48032000 { | |
002e1ec5 | 514 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
515 | reg = <0x48032000 0x80>; |
516 | interrupts = <0 38 0x4>; | |
517 | ti,hwmods = "timer2"; | |
518 | }; | |
519 | ||
520 | timer3: timer@48034000 { | |
002e1ec5 | 521 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
522 | reg = <0x48034000 0x80>; |
523 | interrupts = <0 39 0x4>; | |
524 | ti,hwmods = "timer3"; | |
525 | }; | |
526 | ||
527 | timer4: timer@48036000 { | |
002e1ec5 | 528 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
529 | reg = <0x48036000 0x80>; |
530 | interrupts = <0 40 0x4>; | |
531 | ti,hwmods = "timer4"; | |
532 | }; | |
533 | ||
534 | timer5: timer@40138000 { | |
002e1ec5 | 535 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
536 | reg = <0x40138000 0x80>, |
537 | <0x49038000 0x80>; | |
538 | interrupts = <0 41 0x4>; | |
539 | ti,hwmods = "timer5"; | |
540 | ti,timer-dsp; | |
541 | }; | |
542 | ||
543 | timer6: timer@4013a000 { | |
002e1ec5 | 544 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
545 | reg = <0x4013a000 0x80>, |
546 | <0x4903a000 0x80>; | |
547 | interrupts = <0 42 0x4>; | |
548 | ti,hwmods = "timer6"; | |
549 | ti,timer-dsp; | |
550 | ti,timer-pwm; | |
551 | }; | |
552 | ||
553 | timer7: timer@4013c000 { | |
002e1ec5 | 554 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
555 | reg = <0x4013c000 0x80>, |
556 | <0x4903c000 0x80>; | |
557 | interrupts = <0 43 0x4>; | |
558 | ti,hwmods = "timer7"; | |
559 | ti,timer-dsp; | |
560 | }; | |
561 | ||
562 | timer8: timer@4013e000 { | |
002e1ec5 | 563 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
564 | reg = <0x4013e000 0x80>, |
565 | <0x4903e000 0x80>; | |
566 | interrupts = <0 44 0x4>; | |
567 | ti,hwmods = "timer8"; | |
568 | ti,timer-dsp; | |
569 | ti,timer-pwm; | |
570 | }; | |
571 | ||
572 | timer9: timer@4803e000 { | |
002e1ec5 | 573 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
574 | reg = <0x4803e000 0x80>; |
575 | interrupts = <0 45 0x4>; | |
576 | ti,hwmods = "timer9"; | |
577 | }; | |
578 | ||
579 | timer10: timer@48086000 { | |
002e1ec5 | 580 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
581 | reg = <0x48086000 0x80>; |
582 | interrupts = <0 46 0x4>; | |
583 | ti,hwmods = "timer10"; | |
584 | }; | |
585 | ||
586 | timer11: timer@48088000 { | |
002e1ec5 | 587 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
588 | reg = <0x48088000 0x80>; |
589 | interrupts = <0 47 0x4>; | |
590 | ti,hwmods = "timer11"; | |
591 | ti,timer-pwm; | |
592 | }; | |
e6900ddf | 593 | |
55452197 LV |
594 | wdt2: wdt@4ae14000 { |
595 | compatible = "ti,omap5-wdt", "ti,omap3-wdt"; | |
596 | reg = <0x4ae14000 0x80>; | |
597 | interrupts = <0 80 0x4>; | |
598 | ti,hwmods = "wd_timer2"; | |
599 | }; | |
600 | ||
e6900ddf LV |
601 | emif1: emif@0x4c000000 { |
602 | compatible = "ti,emif-4d5"; | |
603 | ti,hwmods = "emif1"; | |
604 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | |
605 | reg = <0x4c000000 0x400>; | |
606 | interrupts = <0 110 0x4>; | |
607 | hw-caps-read-idle-ctrl; | |
608 | hw-caps-ll-interface; | |
609 | hw-caps-temp-alert; | |
610 | }; | |
611 | ||
612 | emif2: emif@0x4d000000 { | |
613 | compatible = "ti,emif-4d5"; | |
614 | ti,hwmods = "emif2"; | |
615 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | |
616 | reg = <0x4d000000 0x400>; | |
617 | interrupts = <0 111 0x4>; | |
618 | hw-caps-read-idle-ctrl; | |
619 | hw-caps-ll-interface; | |
620 | hw-caps-temp-alert; | |
621 | }; | |
fedc428e KVA |
622 | |
623 | omap_control_usb: omap-control-usb@4a002300 { | |
624 | compatible = "ti,omap-control-usb"; | |
625 | reg = <0x4a002300 0x4>, | |
626 | <0x4a002370 0x4>; | |
627 | reg-names = "control_dev_conf", "phy_power_usb"; | |
628 | ti,type = <2>; | |
629 | }; | |
e9831967 | 630 | |
72f6f957 KVA |
631 | omap_dwc3@4a020000 { |
632 | compatible = "ti,dwc3"; | |
633 | ti,hwmods = "usb_otg_ss"; | |
634 | reg = <0x4a020000 0x1000>; | |
635 | interrupts = <0 93 4>; | |
636 | #address-cells = <1>; | |
637 | #size-cells = <1>; | |
638 | utmi-mode = <2>; | |
639 | ranges; | |
640 | dwc3@4a030000 { | |
641 | compatible = "synopsys,dwc3"; | |
642 | reg = <0x4a030000 0x1000>; | |
643 | interrupts = <0 92 4>; | |
644 | usb-phy = <&usb2_phy>, <&usb3_phy>; | |
645 | tx-fifo-resize; | |
646 | }; | |
647 | }; | |
648 | ||
e9831967 KVA |
649 | ocp2scp { |
650 | compatible = "ti,omap-ocp2scp"; | |
651 | #address-cells = <1>; | |
652 | #size-cells = <1>; | |
653 | ranges; | |
654 | ti,hwmods = "ocp2scp1"; | |
ae6a32d2 KVA |
655 | usb2_phy: usb2phy@4a084000 { |
656 | compatible = "ti,omap-usb2"; | |
657 | reg = <0x4a084000 0x7c>; | |
658 | ctrl-module = <&omap_control_usb>; | |
659 | }; | |
660 | ||
661 | usb3_phy: usb3phy@4a084400 { | |
662 | compatible = "ti,omap-usb3"; | |
663 | reg = <0x4a084400 0x80>, | |
664 | <0x4a084800 0x64>, | |
665 | <0x4a084c00 0x40>; | |
666 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
667 | ctrl-module = <&omap_control_usb>; | |
668 | }; | |
e9831967 | 669 | }; |
6b5de091 S |
670 | }; |
671 | }; |