[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / omap5.dtsi

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
#include <dt-bindings/clock/omap5.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	compatible = "ti,omap5";
	interrupt-parent = <&wakeupgen>;
	chosen { };

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		i2c4 = &i2c5;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;

			operating-points = <
				/* kHz    uV */
				1000000 1060000
				1500000 1250000
			>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */

			/* cooling options */
			#cooling-cells = <2>; /* min followed by max */
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x1>;

			operating-points = <
				/* kHz    uV */
				1000000 1060000
				1500000 1250000
			>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */

			/* cooling options */
			#cooling-cells = <2>; /* min followed by max */
		};
	};

	thermal-zones {
		#include "omap4-cpu-thermal.dtsi"
		#include "omap5-gpu-thermal.dtsi"
		#include "omap5-core-thermal.dtsi"
	};

	timer {
		compatible = "arm,armv7-timer";
		/* PPI secure/nonsecure IRQ */
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&gic>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	};

	gic: interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0 0x48211000 0 0x1000>,
		      <0 0x48212000 0 0x2000>,
		      <0 0x48214000 0 0x2000>,
		      <0 0x48216000 0 0x2000>;
		interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0 0x48281000 0 0x1000>;
		interrupt-parent = <&gic>;
	};

	/*
	 * The soc node represents the soc top level view. It is used for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap4-mpu";
			ti,hwmods = "mpu";
			sram = <&ocmcram>;
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since it will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap5-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xc0000000>;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
		reg = <0 0x44000000 0 0x2000>,
		      <0 0x44800000 0 0x3000>,
		      <0 0x45000000 0 0x4000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

		l4_wkup: interconnect@4ae00000 {
		};

		l4_cfg: interconnect@4a000000 {
		};

		l4_per: interconnect@48000000 {
		};

		l4_abe: interconnect@40100000 {
		};

		ocmcram: ocmcram@40300000 {
			compatible = "mmio-sram";
			reg = <0x40300000 0x20000>; /* 128k */
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,omap4430-gpmc";
			reg = <0x50000000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&sdma 4>;
			dma-names = "rxtx";
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			ti,hwmods = "gpmc";
			clocks = <&l3_iclk_div>;
			clock-names = "fck";
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		mmu_dsp: mmu@4a066000 {
			compatible = "ti,omap4-iommu";
			reg = <0x4a066000 0x100>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmu_dsp";
			#iommu-cells = <0>;
		};

		mmu_ipu: mmu@55082000 {
			compatible = "ti,omap4-iommu";
			reg = <0x55082000 0x100>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmu_ipu";
			#iommu-cells = <0>;
			ti,iommu-bus-err-back;
		};

		dmm@4e000000 {
			compatible = "ti,omap5-dmm";
			reg = <0x4e000000 0x800>;
			interrupts = <0 113 0x4>;
			ti,hwmods = "dmm";
		};

		emif1: emif@4c000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif1";
			ti,no-idle-on-init;
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4c000000 0x400>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		emif2: emif@4d000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif2";
			ti,no-idle-on-init;
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4d000000 0x400>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		bandgap: bandgap@4a0021e0 {
			reg = <0x4a0021e0 0xc
			       0x4a00232c 0xc
			       0x4a002380 0x2c
			       0x4a0023C0 0x3c>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			compatible = "ti,omap5430-bandgap";

			#thermal-sensor-cells = <1>;
		};

		/* OCP2SCP3 */
		sata: sata@4a141100 {
			compatible = "snps,dwc-ahci";
			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&sata_phy>;
			phy-names = "sata-phy";
			clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
			ti,hwmods = "sata";
			ports-implemented = <0x1>;
		};

		dss: dss@58000000 {
			compatible = "ti,omap5-dss";
			reg = <0x58000000 0x80>;
			status = "disabled";
			ti,hwmods = "dss_core";
			clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			dispc@58001000 {
				compatible = "ti,omap5-dispc";
				reg = <0x58001000 0x1000>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				ti,hwmods = "dss_dispc";
				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
				clock-names = "fck";
			};

			rfbi: encoder@58002000  {
				compatible = "ti,omap5-rfbi";
				reg = <0x58002000 0x100>;
				status = "disabled";
				ti,hwmods = "dss_rfbi";
				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
				clock-names = "fck", "ick";
			};

			dsi1: encoder@58004000 {
				compatible = "ti,omap5-dsi";
				reg = <0x58004000 0x200>,
				      <0x58004200 0x40>,
				      <0x58004300 0x40>;
				reg-names = "proto", "phy", "pll";
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_dsi1";
				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
					 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
				clock-names = "fck", "sys_clk";
			};

			dsi2: encoder@58005000 {
				compatible = "ti,omap5-dsi";
				reg = <0x58009000 0x200>,
				      <0x58009200 0x40>,
				      <0x58009300 0x40>;
				reg-names = "proto", "phy", "pll";
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_dsi2";
				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
					 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
				clock-names = "fck", "sys_clk";
			};

			hdmi: encoder@58060000 {
				compatible = "ti,omap5-hdmi";
				reg = <0x58040000 0x200>,
				      <0x58040200 0x80>,
				      <0x58040300 0x80>,
				      <0x58060000 0x19000>;
				reg-names = "wp", "pll", "phy", "core";
				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_hdmi";
				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
					 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
				clock-names = "fck", "sys_clk";
				dmas = <&sdma 76>;
				dma-names = "audio_tx";
			};
		};

		abb_mpu: regulator-abb-mpu {
			compatible = "ti,abb-v2";
			regulator-name = "abb_mpu";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
			      <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
			reg-names = "base-address", "int-address",
				    "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x80>;
			/* LDOVBBMPU_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBMPU_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1060000		0	0x0	0 0x02000000 0x01F00000
			1250000		0	0x4	0 0x02000000 0x01F00000
			>;
		};

		abb_mm: regulator-abb-mm {
			compatible = "ti,abb-v2";
			regulator-name = "abb_mm";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
			      <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
			reg-names = "base-address", "int-address",
				    "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x80000000>;
			/* LDOVBBMM_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBMM_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1025000		0	0x0	0 0x02000000 0x01F00000
			1120000		0	0x4	0 0x02000000 0x01F00000
			>;
		};
	};
};

&cpu_thermal {
	polling-delay = <500>; /* milliseconds */
	coefficients = <65 (-1791)>;
};

#include "omap5-l4.dtsi"
#include "omap54xx-clocks.dtsi"

&gpu_thermal {
	coefficients = <117 (-2992)>;
};

&core_thermal {
	coefficients = <0 2000>;
};

#include "omap5-l4-abe.dtsi"
#include "omap54xx-clocks.dtsi"
Commit	Line	Data
6b5de091 S	1	/*
	2	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	* Based on "omap4.dtsi"
	8	*/
	9
4c387984	10	#include <dt-bindings/bus/ti-sysc.h>
6d624eab	11	#include <dt-bindings/gpio/gpio.h>
8fea7d5a	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7	13	#include <dt-bindings/pinctrl/omap.h>
460c4961	14	#include <dt-bindings/clock/omap5.h>
6b5de091	15
6b5de091	16	/ {
98cc4544 TL	17	#address-cells = <2>;
98cc4544 TL	18	#size-cells = <2>;
ba1829bc	19
6b5de091	20	compatible = "ti,omap5";
7136d457	21	interrupt-parent = <&wakeupgen>;
c9faa84c	22	chosen { };
6b5de091 S	23
6b5de091 S	24	aliases {
20b80942 NM	25	i2c0 = &i2c1;
	26	i2c1 = &i2c2;
	27	i2c2 = &i2c3;
	28	i2c3 = &i2c4;
	29	i2c4 = &i2c5;
6b5de091 S	30	serial0 = &uart1;
	31	serial1 = &uart2;
	32	serial2 = &uart3;
	33	serial3 = &uart4;
	34	serial4 = &uart5;
	35	serial5 = &uart6;
	36	};
	37
	38	cpus {
eeb25fd5 LP	39	#address-cells = <1>;
	40	#size-cells = <0>;
	41
b8981d71	42	cpu0: cpu@0 {
eeb25fd5	43	device_type = "cpu";
6b5de091	44	compatible = "arm,cortex-a15";
eeb25fd5	45	reg = <0x0>;
6c24894d K	46
	47	operating-points = <
	48	/* kHz uV */
6c24894d K	49	1000000 1060000
	50	1500000 1250000
	51	>;
8d766fa2 NM	52
	53	clocks = <&dpll_mpu_ck>;
	54	clock-names = "cpu";
	55
	56	clock-latency = <300000>; /* From omap-cpufreq driver */
	57
2cd29f63	58	/* cooling options */
2cd29f63	59	#cooling-cells = <2>; /* min followed by max */
6b5de091 S	60	};
6b5de091 S	61	cpu@1 {
eeb25fd5	62	device_type = "cpu";
6b5de091	63	compatible = "arm,cortex-a15";
eeb25fd5	64	reg = <0x1>;
484d578b VK	65
	66	operating-points = <
	67	/* kHz uV */
	68	1000000 1060000
	69	1500000 1250000
	70	>;
	71
	72	clocks = <&dpll_mpu_ck>;
	73	clock-names = "cpu";
	74
	75	clock-latency = <300000>; /* From omap-cpufreq driver */
	76
	77	/* cooling options */
	78	#cooling-cells = <2>; /* min followed by max */
6b5de091 S	79	};
	80	};
	81
1b761fc5 EV	82	thermal-zones {
	83	#include "omap4-cpu-thermal.dtsi"
	84	#include "omap5-gpu-thermal.dtsi"
	85	#include "omap5-core-thermal.dtsi"
	86	};
	87
b45ccc4e SS	88	timer {
b45ccc4e SS	89	compatible = "arm,armv7-timer";
8fea7d5a FV	90	/* PPI secure/nonsecure IRQ */
	91	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>,
	92	<GIC_PPI 14 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>,
	93	<GIC_PPI 11 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>,
	94	<GIC_PPI 10 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>;
7136d457	95	interrupt-parent = <&gic>;
b45ccc4e SS	96	};
b45ccc4e SS	97
69a126cb NL	98	pmu {
	99	compatible = "arm,cortex-a15-pmu";
	100	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	101	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	102	};
	103
ba1829bc SS	104	gic: interrupt-controller@48211000 {
	105	compatible = "arm,cortex-a15-gic";
	106	interrupt-controller;
	107	#interrupt-cells = <3>;
98cc4544	108	reg = <0 0x48211000 0 0x1000>,
387720c9	109	<0 0x48212000 0 0x2000>,
98cc4544 TL	110	<0 0x48214000 0 0x2000>,
98cc4544 TL	111	<0 0x48216000 0 0x2000>;
7136d457 MZ	112	interrupt-parent = <&gic>;
	113	};
	114
	115	wakeupgen: interrupt-controller@48281000 {
	116	compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
	117	interrupt-controller;
	118	#interrupt-cells = <3>;
98cc4544	119	reg = <0 0x48281000 0 0x1000>;
7136d457	120	interrupt-parent = <&gic>;
ba1829bc SS	121	};
ba1829bc SS	122
6b5de091	123	/*
5c5be9db	124	* The soc node represents the soc top level view. It is used for IPs
6b5de091 S	125	* that are not memory mapped in the MPU view or for the MPU itself.
	126	*/
	127	soc {
	128	compatible = "ti,omap-infra";
	129	mpu {
1306c08a	130	compatible = "ti,omap4-mpu";
6b5de091	131	ti,hwmods = "mpu";
1306c08a	132	sram = <&ocmcram>;
6b5de091 S	133	};
	134	};
	135
	136	/*
	137	* XXX: Use a flat representation of the OMAP3 interconnect.
	138	* The real OMAP interconnect network is quite complex.
b7ab524b	139	* Since it will not bring real advantage to represent that in DT for
6b5de091 S	140	* the moment, just use a fake OCP bus entry to represent the whole bus
	141	* hierarchy.
	142	*/
	143	ocp {
e7309c26	144	compatible = "ti,omap5-l3-noc", "simple-bus";
6b5de091 S	145	#address-cells = <1>;
6b5de091 S	146	#size-cells = <1>;
98cc4544	147	ranges = <0 0 0 0xc0000000>;
6b5de091	148	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
98cc4544 TL	149	reg = <0 0x44000000 0 0x2000>,
	150	<0 0x44800000 0 0x3000>,
	151	<0 0x45000000 0 0x4000>;
8fea7d5a FV	152	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
8fea7d5a FV	153	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091	154
4c387984	155	l4_wkup: interconnect@4ae00000 {
85dc74e9 TK	156	};
85dc74e9 TK	157
4c387984 TL	158	l4_cfg: interconnect@4a000000 {
4c387984 TL	159	};
0b75c042	160
4c387984	161	l4_per: interconnect@48000000 {
cd042fe5 B	162	};
cd042fe5 B	163
b2770b2d TL	164	l4_abe: interconnect@40100000 {
	165	};
	166
8b9a2810 RN	167	ocmcram: ocmcram@40300000 {
	168	compatible = "mmio-sram";
	169	reg = <0x40300000 0x20000>; /* 128k */
	170	};
	171
1c7dbb55 JH	172	gpmc: gpmc@50000000 {
	173	compatible = "ti,omap4430-gpmc";
	174	reg = <0x50000000 0x1000>;
	175	#address-cells = <2>;
	176	#size-cells = <1>;
8fea7d5a	177	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
201c7e33 FCJ	178	dmas = <&sdma 4>;
201c7e33 FCJ	179	dma-names = "rxtx";
1c7dbb55 JH	180	gpmc,num-cs = <8>;
	181	gpmc,num-waitpins = <4>;
	182	ti,hwmods = "gpmc";
7b8b6af1 FV	183	clocks = <&l3_iclk_div>;
7b8b6af1 FV	184	clock-names = "fck";
e99d413f RQ	185	interrupt-controller;
	186	#interrupt-cells = <2>;
	187	gpio-controller;
	188	#gpio-cells = <2>;
1c7dbb55 JH	189	};
1c7dbb55 JH	190
2dcfa56e SA	191	mmu_dsp: mmu@4a066000 {
	192	compatible = "ti,omap4-iommu";
	193	reg = <0x4a066000 0x100>;
	194	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	195	ti,hwmods = "mmu_dsp";
c1b5d0f6	196	#iommu-cells = <0>;
2dcfa56e SA	197	};
	198
	199	mmu_ipu: mmu@55082000 {
	200	compatible = "ti,omap4-iommu";
	201	reg = <0x55082000 0x100>;
	202	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	203	ti,hwmods = "mmu_ipu";
c1b5d0f6	204	#iommu-cells = <0>;
2dcfa56e SA	205	ti,iommu-bus-err-back;
	206	};
	207
1a5fe3ca AT	208	dmm@4e000000 {
	209	compatible = "ti,omap5-dmm";
	210	reg = <0x4e000000 0x800>;
	211	interrupts = <0 113 0x4>;
	212	ti,hwmods = "dmm";
	213	};
	214
8906d654	215	emif1: emif@4c000000 {
e6900ddf LV	216	compatible = "ti,emif-4d5";
e6900ddf LV	217	ti,hwmods = "emif1";
f12ecbe2	218	ti,no-idle-on-init;
e6900ddf LV	219	phy-type = <2>; /* DDR PHY type: Intelli PHY */
e6900ddf LV	220	reg = <0x4c000000 0x400>;
8fea7d5a	221	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf LV	222	hw-caps-read-idle-ctrl;
	223	hw-caps-ll-interface;
	224	hw-caps-temp-alert;
	225	};
	226
8906d654	227	emif2: emif@4d000000 {
e6900ddf LV	228	compatible = "ti,emif-4d5";
e6900ddf LV	229	ti,hwmods = "emif2";
f12ecbe2	230	ti,no-idle-on-init;
e6900ddf LV	231	phy-type = <2>; /* DDR PHY type: Intelli PHY */
e6900ddf LV	232	reg = <0x4d000000 0x400>;
8fea7d5a	233	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf LV	234	hw-caps-read-idle-ctrl;
	235	hw-caps-ll-interface;
	236	hw-caps-temp-alert;
	237	};
fedc428e	238
1b761fc5	239	bandgap: bandgap@4a0021e0 {
cbad26db EV	240	reg = <0x4a0021e0 0xc
	241	0x4a00232c 0xc
	242	0x4a002380 0x2c
	243	0x4a0023C0 0x3c>;
	244	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	245	compatible = "ti,omap5430-bandgap";
1b761fc5 EV	246
1b761fc5 EV	247	#thermal-sensor-cells = <1>;
cbad26db	248	};
4f82952c	249
4f82952c	250	/* OCP2SCP3 */
4f82952c B	251	sata: sata@4a141100 {
	252	compatible = "snps,dwc-ahci";
	253	reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
	254	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	255	phys = <&sata_phy>;
	256	phy-names = "sata-phy";
460c4961	257	clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
4f82952c	258	ti,hwmods = "sata";
87cb1291	259	ports-implemented = <0x1>;
4f82952c B	260	};
4f82952c B	261
e7585c4f TV	262	dss: dss@58000000 {
	263	compatible = "ti,omap5-dss";
	264	reg = <0x58000000 0x80>;
	265	status = "disabled";
	266	ti,hwmods = "dss_core";
460c4961	267	clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
e7585c4f TV	268	clock-names = "fck";
	269	#address-cells = <1>;
	270	#size-cells = <1>;
	271	ranges;
	272
	273	dispc@58001000 {
	274	compatible = "ti,omap5-dispc";
	275	reg = <0x58001000 0x1000>;
	276	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	277	ti,hwmods = "dss_dispc";
460c4961	278	clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
e7585c4f TV	279	clock-names = "fck";
	280	};
	281
84ace674 TV	282	rfbi: encoder@58002000 {
	283	compatible = "ti,omap5-rfbi";
	284	reg = <0x58002000 0x100>;
	285	status = "disabled";
	286	ti,hwmods = "dss_rfbi";
460c4961	287	clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
84ace674 TV	288	clock-names = "fck", "ick";
	289	};
	290
e7585c4f TV	291	dsi1: encoder@58004000 {
	292	compatible = "ti,omap5-dsi";
	293	reg = <0x58004000 0x200>,
	294	<0x58004200 0x40>,
	295	<0x58004300 0x40>;
	296	reg-names = "proto", "phy", "pll";
	297	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	298	status = "disabled";
	299	ti,hwmods = "dss_dsi1";
460c4961 TK	300	clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
460c4961 TK	301	<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
e7585c4f TV	302	clock-names = "fck", "sys_clk";
	303	};
	304
	305	dsi2: encoder@58005000 {
	306	compatible = "ti,omap5-dsi";
	307	reg = <0x58009000 0x200>,
	308	<0x58009200 0x40>,
	309	<0x58009300 0x40>;
	310	reg-names = "proto", "phy", "pll";
	311	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	312	status = "disabled";
	313	ti,hwmods = "dss_dsi2";
460c4961 TK	314	clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
460c4961 TK	315	<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
e7585c4f TV	316	clock-names = "fck", "sys_clk";
	317	};
	318
	319	hdmi: encoder@58060000 {
	320	compatible = "ti,omap5-hdmi";
	321	reg = <0x58040000 0x200>,
	322	<0x58040200 0x80>,
	323	<0x58040300 0x80>,
	324	<0x58060000 0x19000>;
	325	reg-names = "wp", "pll", "phy", "core";
	326	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	327	status = "disabled";
	328	ti,hwmods = "dss_hdmi";
460c4961 TK	329	clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
460c4961 TK	330	<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
e7585c4f	331	clock-names = "fck", "sys_clk";
7d0fde39 JS	332	dmas = <&sdma 76>;
7d0fde39 JS	333	dma-names = "audio_tx";
e7585c4f TV	334	};
e7585c4f TV	335	};
07b9b3d9 AT	336
	337	abb_mpu: regulator-abb-mpu {
	338	compatible = "ti,abb-v2";
	339	regulator-name = "abb_mpu";
	340	#address-cells = <0>;
	341	#size-cells = <0>;
	342	clocks = <&sys_clkin>;
	343	ti,settling-time = <50>;
	344	ti,clock-cycles = <16>;
	345
	346	reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
	347	<0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
	348	reg-names = "base-address", "int-address",
	349	"efuse-address", "ldo-address";
	350	ti,tranxdone-status-mask = <0x80>;
	351	/* LDOVBBMPU_MUX_CTRL */
	352	ti,ldovbb-override-mask = <0x400>;
	353	/* LDOVBBMPU_VSET_OUT */
	354	ti,ldovbb-vset-mask = <0x1F>;
	355
	356	/*
	357	* NOTE: only FBB mode used but actual vset will
	358	* determine final biasing
	359	*/
	360	ti,abb_info = <
	361	/uV ABB efuse rbb_m fbb_m vset_m/
	362	1060000 0 0x0 0 0x02000000 0x01F00000
	363	1250000 0 0x4 0 0x02000000 0x01F00000
	364	>;
	365	};
	366
	367	abb_mm: regulator-abb-mm {
	368	compatible = "ti,abb-v2";
	369	regulator-name = "abb_mm";
	370	#address-cells = <0>;
	371	#size-cells = <0>;
	372	clocks = <&sys_clkin>;
	373	ti,settling-time = <50>;
	374	ti,clock-cycles = <16>;
	375
	376	reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
	377	<0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
	378	reg-names = "base-address", "int-address",
	379	"efuse-address", "ldo-address";
	380	ti,tranxdone-status-mask = <0x80000000>;
	381	/* LDOVBBMM_MUX_CTRL */
	382	ti,ldovbb-override-mask = <0x400>;
	383	/* LDOVBBMM_VSET_OUT */
	384	ti,ldovbb-vset-mask = <0x1F>;
	385
	386	/*
	387	* NOTE: only FBB mode used but actual vset will
	388	* determine final biasing
	389	*/
	390	ti,abb_info = <
	391	/uV ABB efuse rbb_m fbb_m vset_m/
	392	1025000 0 0x0 0 0x02000000 0x01F00000
	393	1120000 0 0x4 0 0x02000000 0x01F00000
	394	>;
	395	};
6b5de091 S	396	};
6b5de091 S	397	};
85dc74e9	398
38f5c8ba TK	399	&cpu_thermal {
38f5c8ba TK	400	polling-delay = <500>; /* milliseconds */
257b1b7c	401	coefficients = <65 (-1791)>;
38f5c8ba TK	402	};
38f5c8ba TK	403
4c387984	404	#include "omap5-l4.dtsi"
460c4961	405	#include "omap54xx-clocks.dtsi"
257b1b7c K	406
	407	&gpu_thermal {
	408	coefficients = <117 (-2992)>;
	409	};
	410
	411	&core_thermal {
	412	coefficients = <0 2000>;
	413	};
b2770b2d TL	414
	415	#include "omap5-l4-abe.dtsi"
	416	#include "omap54xx-clocks.dtsi"