]>
Commit | Line | Data |
---|---|---|
6b5de091 S |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
10 | /* | |
11 | * Carveout for multimedia usecases | |
12 | * It should be the last 48MB of the first 512MB memory part | |
13 | * In theory, it should not even exist. That zone should be reserved | |
14 | * dynamically during the .reserve callback. | |
15 | */ | |
16 | /memreserve/ 0x9d000000 0x03000000; | |
17 | ||
18 | /include/ "skeleton.dtsi" | |
19 | ||
20 | / { | |
21 | compatible = "ti,omap5"; | |
22 | interrupt-parent = <&gic>; | |
23 | ||
24 | aliases { | |
25 | serial0 = &uart1; | |
26 | serial1 = &uart2; | |
27 | serial2 = &uart3; | |
28 | serial3 = &uart4; | |
29 | serial4 = &uart5; | |
30 | serial5 = &uart6; | |
31 | }; | |
32 | ||
33 | cpus { | |
34 | cpu@0 { | |
35 | compatible = "arm,cortex-a15"; | |
3c7c5dab SS |
36 | timer { |
37 | compatible = "arm,armv7-timer"; | |
38 | /* 14th PPI IRQ, active low level-sensitive */ | |
39 | interrupts = <1 14 0x308>; | |
40 | clock-frequency = <6144000>; | |
41 | }; | |
6b5de091 S |
42 | }; |
43 | cpu@1 { | |
44 | compatible = "arm,cortex-a15"; | |
3c7c5dab SS |
45 | timer { |
46 | compatible = "arm,armv7-timer"; | |
47 | /* 14th PPI IRQ, active low level-sensitive */ | |
48 | interrupts = <1 14 0x308>; | |
49 | clock-frequency = <6144000>; | |
50 | }; | |
6b5de091 S |
51 | }; |
52 | }; | |
53 | ||
54 | /* | |
55 | * The soc node represents the soc top level view. It is uses for IPs | |
56 | * that are not memory mapped in the MPU view or for the MPU itself. | |
57 | */ | |
58 | soc { | |
59 | compatible = "ti,omap-infra"; | |
60 | mpu { | |
61 | compatible = "ti,omap5-mpu"; | |
62 | ti,hwmods = "mpu"; | |
63 | }; | |
64 | }; | |
65 | ||
66 | /* | |
67 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
68 | * The real OMAP interconnect network is quite complex. | |
69 | * Since that will not bring real advantage to represent that in DT for | |
70 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
71 | * hierarchy. | |
72 | */ | |
73 | ocp { | |
74 | compatible = "ti,omap4-l3-noc", "simple-bus"; | |
75 | #address-cells = <1>; | |
76 | #size-cells = <1>; | |
77 | ranges; | |
78 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | |
79 | ||
5da6a2d5 PU |
80 | omap5_pmx_core: pinmux@4a002840 { |
81 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
82 | reg = <0x4a002840 0x01b6>; | |
83 | #address-cells = <1>; | |
84 | #size-cells = <0>; | |
85 | pinctrl-single,register-width = <16>; | |
86 | pinctrl-single,function-mask = <0x7fff>; | |
87 | }; | |
88 | omap5_pmx_wkup: pinmux@4ae0c840 { | |
89 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
90 | reg = <0x4ae0c840 0x0038>; | |
91 | #address-cells = <1>; | |
92 | #size-cells = <0>; | |
93 | pinctrl-single,register-width = <16>; | |
94 | pinctrl-single,function-mask = <0x7fff>; | |
95 | }; | |
96 | ||
6b5de091 S |
97 | gic: interrupt-controller@48211000 { |
98 | compatible = "arm,cortex-a15-gic"; | |
99 | interrupt-controller; | |
100 | #interrupt-cells = <3>; | |
101 | reg = <0x48211000 0x1000>, | |
102 | <0x48212000 0x1000>; | |
103 | }; | |
104 | ||
105 | gpio1: gpio@4ae10000 { | |
106 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
107 | reg = <0x4ae10000 0x200>; |
108 | interrupts = <0 29 0x4>; | |
6b5de091 S |
109 | ti,hwmods = "gpio1"; |
110 | gpio-controller; | |
111 | #gpio-cells = <2>; | |
112 | interrupt-controller; | |
113 | #interrupt-cells = <1>; | |
114 | }; | |
115 | ||
116 | gpio2: gpio@48055000 { | |
117 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
118 | reg = <0x48055000 0x200>; |
119 | interrupts = <0 30 0x4>; | |
6b5de091 S |
120 | ti,hwmods = "gpio2"; |
121 | gpio-controller; | |
122 | #gpio-cells = <2>; | |
123 | interrupt-controller; | |
124 | #interrupt-cells = <1>; | |
125 | }; | |
126 | ||
127 | gpio3: gpio@48057000 { | |
128 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
129 | reg = <0x48057000 0x200>; |
130 | interrupts = <0 31 0x4>; | |
6b5de091 S |
131 | ti,hwmods = "gpio3"; |
132 | gpio-controller; | |
133 | #gpio-cells = <2>; | |
134 | interrupt-controller; | |
135 | #interrupt-cells = <1>; | |
136 | }; | |
137 | ||
138 | gpio4: gpio@48059000 { | |
139 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
140 | reg = <0x48059000 0x200>; |
141 | interrupts = <0 32 0x4>; | |
6b5de091 S |
142 | ti,hwmods = "gpio4"; |
143 | gpio-controller; | |
144 | #gpio-cells = <2>; | |
145 | interrupt-controller; | |
146 | #interrupt-cells = <1>; | |
147 | }; | |
148 | ||
149 | gpio5: gpio@4805b000 { | |
150 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
151 | reg = <0x4805b000 0x200>; |
152 | interrupts = <0 33 0x4>; | |
6b5de091 S |
153 | ti,hwmods = "gpio5"; |
154 | gpio-controller; | |
155 | #gpio-cells = <2>; | |
156 | interrupt-controller; | |
157 | #interrupt-cells = <1>; | |
158 | }; | |
159 | ||
160 | gpio6: gpio@4805d000 { | |
161 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
162 | reg = <0x4805d000 0x200>; |
163 | interrupts = <0 34 0x4>; | |
6b5de091 S |
164 | ti,hwmods = "gpio6"; |
165 | gpio-controller; | |
166 | #gpio-cells = <2>; | |
167 | interrupt-controller; | |
168 | #interrupt-cells = <1>; | |
169 | }; | |
170 | ||
171 | gpio7: gpio@48051000 { | |
172 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
173 | reg = <0x48051000 0x200>; |
174 | interrupts = <0 35 0x4>; | |
6b5de091 S |
175 | ti,hwmods = "gpio7"; |
176 | gpio-controller; | |
177 | #gpio-cells = <2>; | |
178 | interrupt-controller; | |
179 | #interrupt-cells = <1>; | |
180 | }; | |
181 | ||
182 | gpio8: gpio@48053000 { | |
183 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
184 | reg = <0x48053000 0x200>; |
185 | interrupts = <0 121 0x4>; | |
6b5de091 S |
186 | ti,hwmods = "gpio8"; |
187 | gpio-controller; | |
188 | #gpio-cells = <2>; | |
189 | interrupt-controller; | |
190 | #interrupt-cells = <1>; | |
191 | }; | |
192 | ||
6e6a9a50 SP |
193 | i2c1: i2c@48070000 { |
194 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
195 | reg = <0x48070000 0x100>; |
196 | interrupts = <0 56 0x4>; | |
6e6a9a50 SP |
197 | #address-cells = <1>; |
198 | #size-cells = <0>; | |
199 | ti,hwmods = "i2c1"; | |
200 | }; | |
201 | ||
202 | i2c2: i2c@48072000 { | |
203 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
204 | reg = <0x48072000 0x100>; |
205 | interrupts = <0 57 0x4>; | |
6e6a9a50 SP |
206 | #address-cells = <1>; |
207 | #size-cells = <0>; | |
208 | ti,hwmods = "i2c2"; | |
209 | }; | |
210 | ||
211 | i2c3: i2c@48060000 { | |
212 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
213 | reg = <0x48060000 0x100>; |
214 | interrupts = <0 61 0x4>; | |
6e6a9a50 SP |
215 | #address-cells = <1>; |
216 | #size-cells = <0>; | |
217 | ti,hwmods = "i2c3"; | |
218 | }; | |
219 | ||
d7118bbd | 220 | i2c4: i2c@4807a000 { |
6e6a9a50 | 221 | compatible = "ti,omap4-i2c"; |
d7118bbd SG |
222 | reg = <0x4807a000 0x100>; |
223 | interrupts = <0 62 0x4>; | |
6e6a9a50 SP |
224 | #address-cells = <1>; |
225 | #size-cells = <0>; | |
226 | ti,hwmods = "i2c4"; | |
227 | }; | |
228 | ||
d7118bbd | 229 | i2c5: i2c@4807c000 { |
6e6a9a50 | 230 | compatible = "ti,omap4-i2c"; |
d7118bbd SG |
231 | reg = <0x4807c000 0x100>; |
232 | interrupts = <0 60 0x4>; | |
6e6a9a50 SP |
233 | #address-cells = <1>; |
234 | #size-cells = <0>; | |
235 | ti,hwmods = "i2c5"; | |
236 | }; | |
237 | ||
6b5de091 S |
238 | uart1: serial@4806a000 { |
239 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
240 | reg = <0x4806a000 0x100>; |
241 | interrupts = <0 72 0x4>; | |
6b5de091 S |
242 | ti,hwmods = "uart1"; |
243 | clock-frequency = <48000000>; | |
244 | }; | |
245 | ||
246 | uart2: serial@4806c000 { | |
247 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
248 | reg = <0x4806c000 0x100>; |
249 | interrupts = <0 73 0x4>; | |
6b5de091 S |
250 | ti,hwmods = "uart2"; |
251 | clock-frequency = <48000000>; | |
252 | }; | |
253 | ||
254 | uart3: serial@48020000 { | |
255 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
256 | reg = <0x48020000 0x100>; |
257 | interrupts = <0 74 0x4>; | |
6b5de091 S |
258 | ti,hwmods = "uart3"; |
259 | clock-frequency = <48000000>; | |
260 | }; | |
261 | ||
262 | uart4: serial@4806e000 { | |
263 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
264 | reg = <0x4806e000 0x100>; |
265 | interrupts = <0 70 0x4>; | |
6b5de091 S |
266 | ti,hwmods = "uart4"; |
267 | clock-frequency = <48000000>; | |
268 | }; | |
269 | ||
270 | uart5: serial@48066000 { | |
8e80f660 SG |
271 | compatible = "ti,omap4-uart"; |
272 | reg = <0x48066000 0x100>; | |
273 | interrupts = <0 105 0x4>; | |
6b5de091 S |
274 | ti,hwmods = "uart5"; |
275 | clock-frequency = <48000000>; | |
276 | }; | |
277 | ||
278 | uart6: serial@48068000 { | |
8e80f660 SG |
279 | compatible = "ti,omap4-uart"; |
280 | reg = <0x48068000 0x100>; | |
281 | interrupts = <0 106 0x4>; | |
6b5de091 S |
282 | ti,hwmods = "uart6"; |
283 | clock-frequency = <48000000>; | |
284 | }; | |
5dd18b01 B |
285 | |
286 | mmc1: mmc@4809c000 { | |
287 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
288 | reg = <0x4809c000 0x400>; |
289 | interrupts = <0 83 0x4>; | |
5dd18b01 B |
290 | ti,hwmods = "mmc1"; |
291 | ti,dual-volt; | |
292 | ti,needs-special-reset; | |
293 | }; | |
294 | ||
295 | mmc2: mmc@480b4000 { | |
296 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
297 | reg = <0x480b4000 0x400>; |
298 | interrupts = <0 86 0x4>; | |
5dd18b01 B |
299 | ti,hwmods = "mmc2"; |
300 | ti,needs-special-reset; | |
301 | }; | |
302 | ||
303 | mmc3: mmc@480ad000 { | |
304 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
305 | reg = <0x480ad000 0x400>; |
306 | interrupts = <0 94 0x4>; | |
5dd18b01 B |
307 | ti,hwmods = "mmc3"; |
308 | ti,needs-special-reset; | |
309 | }; | |
310 | ||
311 | mmc4: mmc@480d1000 { | |
312 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
313 | reg = <0x480d1000 0x400>; |
314 | interrupts = <0 96 0x4>; | |
5dd18b01 B |
315 | ti,hwmods = "mmc4"; |
316 | ti,needs-special-reset; | |
317 | }; | |
318 | ||
319 | mmc5: mmc@480d5000 { | |
320 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
321 | reg = <0x480d5000 0x400>; |
322 | interrupts = <0 59 0x4>; | |
5dd18b01 B |
323 | ti,hwmods = "mmc5"; |
324 | ti,needs-special-reset; | |
325 | }; | |
5449fbc2 SP |
326 | |
327 | keypad: keypad@4ae1c000 { | |
328 | compatible = "ti,omap4-keypad"; | |
329 | ti,hwmods = "kbd"; | |
330 | }; | |
ffd5db24 | 331 | |
cbb57f07 PU |
332 | mcpdm: mcpdm@40132000 { |
333 | compatible = "ti,omap4-mcpdm"; | |
334 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
335 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
336 | reg-names = "mpu", "dma"; | |
337 | interrupts = <0 112 0x4>; | |
cbb57f07 PU |
338 | ti,hwmods = "mcpdm"; |
339 | }; | |
340 | ||
341 | dmic: dmic@4012e000 { | |
342 | compatible = "ti,omap4-dmic"; | |
343 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
344 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
345 | reg-names = "mpu", "dma"; | |
346 | interrupts = <0 114 0x4>; | |
cbb57f07 PU |
347 | ti,hwmods = "dmic"; |
348 | }; | |
349 | ||
ffd5db24 PU |
350 | mcbsp1: mcbsp@40122000 { |
351 | compatible = "ti,omap4-mcbsp"; | |
352 | reg = <0x40122000 0xff>, /* MPU private access */ | |
353 | <0x49022000 0xff>; /* L3 Interconnect */ | |
354 | reg-names = "mpu", "dma"; | |
355 | interrupts = <0 17 0x4>; | |
356 | interrupt-names = "common"; | |
ffd5db24 PU |
357 | ti,buffer-size = <128>; |
358 | ti,hwmods = "mcbsp1"; | |
359 | }; | |
360 | ||
361 | mcbsp2: mcbsp@40124000 { | |
362 | compatible = "ti,omap4-mcbsp"; | |
363 | reg = <0x40124000 0xff>, /* MPU private access */ | |
364 | <0x49024000 0xff>; /* L3 Interconnect */ | |
365 | reg-names = "mpu", "dma"; | |
366 | interrupts = <0 22 0x4>; | |
367 | interrupt-names = "common"; | |
ffd5db24 PU |
368 | ti,buffer-size = <128>; |
369 | ti,hwmods = "mcbsp2"; | |
370 | }; | |
371 | ||
372 | mcbsp3: mcbsp@40126000 { | |
373 | compatible = "ti,omap4-mcbsp"; | |
374 | reg = <0x40126000 0xff>, /* MPU private access */ | |
375 | <0x49026000 0xff>; /* L3 Interconnect */ | |
376 | reg-names = "mpu", "dma"; | |
377 | interrupts = <0 23 0x4>; | |
378 | interrupt-names = "common"; | |
ffd5db24 PU |
379 | ti,buffer-size = <128>; |
380 | ti,hwmods = "mcbsp3"; | |
381 | }; | |
6b5de091 S |
382 | }; |
383 | }; |