]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - arch/arm/boot/dts/omap5.dtsi
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: AM437x: switch to compatible pinctrl
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / omap5.dtsi
CommitLineData
6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
98ef7957 14#include "skeleton.dtsi"
6b5de091
S		 15
16/ {
ba1829bc
SS		 17 #address-cells = <1>;
18 #size-cells = <1>;
19
6b5de091
S		 20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
20b80942
NM		 24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
6b5de091
S		 29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
eeb25fd5
LP		 38 #address-cells = <1>;
39 #size-cells = <0>;
40
b8981d71 41 cpu0: cpu@0 {
eeb25fd5 42 device_type = "cpu";
6b5de091 43 compatible = "arm,cortex-a15";
eeb25fd5 44 reg = <0x0>;
6c24894d
K		 45
46 operating-points = <
47 /* kHz uV */
6c24894d
K		 48 1000000 1060000
49 1500000 1250000
50 >;
8d766fa2
NM		 51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
55 clock-latency = <300000>; /* From omap-cpufreq driver */
56
2cd29f63
EV		 57 /* cooling options */
58 cooling-min-level = <0>;
59 cooling-max-level = <2>;
60 #cooling-cells = <2>; /* min followed by max */
6b5de091
S		 61 };
62 cpu@1 {
eeb25fd5 63 device_type = "cpu";
6b5de091 64 compatible = "arm,cortex-a15";
eeb25fd5 65 reg = <0x1>;
6b5de091
S		 66 };
67 };
68
1b761fc5
EV		 69 thermal-zones {
70 #include "omap4-cpu-thermal.dtsi"
71 #include "omap5-gpu-thermal.dtsi"
72 #include "omap5-core-thermal.dtsi"
73 };
74
b45ccc4e
SS		 75 timer {
76 compatible = "arm,armv7-timer";
8fea7d5a
FV		 77 /* PPI secure/nonsecure IRQ */
78 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
b45ccc4e
SS		 82 };
83
69a126cb
NL		 84 pmu {
85 compatible = "arm,cortex-a15-pmu";
86 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
88 };
89
ba1829bc
SS		 90 gic: interrupt-controller@48211000 {
91 compatible = "arm,cortex-a15-gic";
92 interrupt-controller;
93 #interrupt-cells = <3>;
94 reg = <0x48211000 0x1000>,
0129c16c
SS		 95 <0x48212000 0x1000>,
96 <0x48214000 0x2000>,
97 <0x48216000 0x2000>;
ba1829bc
SS		 98 };
99
6b5de091 100 /*
5c5be9db 101 * The soc node represents the soc top level view. It is used for IPs
6b5de091
S		 102 * that are not memory mapped in the MPU view or for the MPU itself.
103 */
104 soc {
105 compatible = "ti,omap-infra";
106 mpu {
107 compatible = "ti,omap5-mpu";
108 ti,hwmods = "mpu";
109 };
110 };
111
112 /*
113 * XXX: Use a flat representation of the OMAP3 interconnect.
114 * The real OMAP interconnect network is quite complex.
b7ab524b 115 * Since it will not bring real advantage to represent that in DT for
6b5de091
S		 116 * the moment, just use a fake OCP bus entry to represent the whole bus
117 * hierarchy.
118 */
119 ocp {
120 compatible = "ti,omap4-l3-noc", "simple-bus";
121 #address-cells = <1>;
122 #size-cells = <1>;
123 ranges;
124 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 125 reg = <0x44000000 0x2000>,
126 <0x44800000 0x3000>,
127 <0x45000000 0x4000>;
8fea7d5a
FV		 128 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 130
85dc74e9
TK		 131 prm: prm@4ae06000 {
132 compatible = "ti,omap5-prm";
133 reg = <0x4ae06000 0x3000>;
134
135 prm_clocks: clocks {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139
140 prm_clockdomains: clockdomains {
141 };
142 };
143
144 cm_core_aon: cm_core_aon@4a004000 {
145 compatible = "ti,omap5-cm-core-aon";
146 reg = <0x4a004000 0x2000>;
147
148 cm_core_aon_clocks: clocks {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 };
152
153 cm_core_aon_clockdomains: clockdomains {
154 };
155 };
156
157 scrm: scrm@4ae0a000 {
158 compatible = "ti,omap5-scrm";
159 reg = <0x4ae0a000 0x2000>;
160
161 scrm_clocks: clocks {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 };
165
166 scrm_clockdomains: clockdomains {
167 };
168 };
169
170 cm_core: cm_core@4a008000 {
171 compatible = "ti,omap5-cm-core";
172 reg = <0x4a008000 0x3000>;
173
174 cm_core_clocks: clocks {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 };
178
179 cm_core_clockdomains: clockdomains {
180 };
181 };
182
3b3132f7
JH		 183 counter32k: counter@4ae04000 {
184 compatible = "ti,omap-counter32k";
185 reg = <0x4ae04000 0x40>;
186 ti,hwmods = "counter_32k";
187 };
188
5da6a2d5 189 omap5_pmx_core: pinmux@4a002840 {
924c31cc 190 compatible = "ti,omap5-padconf", "pinctrl-single";
5da6a2d5
PU		 191 reg = <0x4a002840 0x01b6>;
192 #address-cells = <1>;
193 #size-cells = <0>;
924c31cc
NM		 194 #interrupt-cells = <1>;
195 interrupt-controller;
5da6a2d5
PU		 196 pinctrl-single,register-width = <16>;
197 pinctrl-single,function-mask = <0x7fff>;
198 };
199 omap5_pmx_wkup: pinmux@4ae0c840 {
924c31cc 200 compatible = "ti,omap5-padconf", "pinctrl-single";
5da6a2d5
PU		 201 reg = <0x4ae0c840 0x0038>;
202 #address-cells = <1>;
203 #size-cells = <0>;
924c31cc
NM		 204 #interrupt-cells = <1>;
205 interrupt-controller;
5da6a2d5
PU		 206 pinctrl-single,register-width = <16>;
207 pinctrl-single,function-mask = <0x7fff>;
208 };
209
cd042fe5
B		 210 omap5_padconf_global: tisyscon@4a002da0 {
211 compatible = "syscon";
212 reg = <0x4A002da0 0xec>;
213 };
214
215 pbias_regulator: pbias_regulator {
216 compatible = "ti,pbias-omap";
217 reg = <0x60 0x4>;
218 syscon = <&omap5_padconf_global>;
219 pbias_mmc_reg: pbias_mmc_omap5 {
220 regulator-name = "pbias_mmc_omap5";
221 regulator-min-microvolt = <1800000>;
222 regulator-max-microvolt = <3000000>;
223 };
224 };
225
2c2dc545
JH		 226 sdma: dma-controller@4a056000 {
227 compatible = "ti,omap4430-sdma";
228 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 229 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 233 #dma-cells = <1>;
234 #dma-channels = <32>;
235 #dma-requests = <127>;
236 };
237
6b5de091
S		 238 gpio1: gpio@4ae10000 {
239 compatible = "ti,omap4-gpio";
f4b224f2 240 reg = <0x4ae10000 0x200>;
8fea7d5a 241 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 242 ti,hwmods = "gpio1";
e4b9b9f3 243 ti,gpio-always-on;
6b5de091
S		 244 gpio-controller;
245 #gpio-cells = <2>;
246 interrupt-controller;
ff5c9059 247 #interrupt-cells = <2>;
6b5de091
S		 248 };
249
250 gpio2: gpio@48055000 {
251 compatible = "ti,omap4-gpio";
f4b224f2 252 reg = <0x48055000 0x200>;
8fea7d5a 253 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 254 ti,hwmods = "gpio2";
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
ff5c9059 258 #interrupt-cells = <2>;
6b5de091
S		 259 };
260
261 gpio3: gpio@48057000 {
262 compatible = "ti,omap4-gpio";
f4b224f2 263 reg = <0x48057000 0x200>;
8fea7d5a 264 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 265 ti,hwmods = "gpio3";
266 gpio-controller;
267 #gpio-cells = <2>;
268 interrupt-controller;
ff5c9059 269 #interrupt-cells = <2>;
6b5de091
S		 270 };
271
272 gpio4: gpio@48059000 {
273 compatible = "ti,omap4-gpio";
f4b224f2 274 reg = <0x48059000 0x200>;
8fea7d5a 275 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 276 ti,hwmods = "gpio4";
277 gpio-controller;
278 #gpio-cells = <2>;
279 interrupt-controller;
ff5c9059 280 #interrupt-cells = <2>;
6b5de091
S		 281 };
282
283 gpio5: gpio@4805b000 {
284 compatible = "ti,omap4-gpio";
f4b224f2 285 reg = <0x4805b000 0x200>;
8fea7d5a 286 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 287 ti,hwmods = "gpio5";
288 gpio-controller;
289 #gpio-cells = <2>;
290 interrupt-controller;
ff5c9059 291 #interrupt-cells = <2>;
6b5de091
S		 292 };
293
294 gpio6: gpio@4805d000 {
295 compatible = "ti,omap4-gpio";
f4b224f2 296 reg = <0x4805d000 0x200>;
8fea7d5a 297 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 298 ti,hwmods = "gpio6";
299 gpio-controller;
300 #gpio-cells = <2>;
301 interrupt-controller;
ff5c9059 302 #interrupt-cells = <2>;
6b5de091
S		 303 };
304
305 gpio7: gpio@48051000 {
306 compatible = "ti,omap4-gpio";
f4b224f2 307 reg = <0x48051000 0x200>;
8fea7d5a 308 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 309 ti,hwmods = "gpio7";
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
ff5c9059 313 #interrupt-cells = <2>;
6b5de091
S		 314 };
315
316 gpio8: gpio@48053000 {
317 compatible = "ti,omap4-gpio";
f4b224f2 318 reg = <0x48053000 0x200>;
8fea7d5a 319 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 320 ti,hwmods = "gpio8";
321 gpio-controller;
322 #gpio-cells = <2>;
323 interrupt-controller;
ff5c9059 324 #interrupt-cells = <2>;
6b5de091
S		 325 };
326
1c7dbb55
JH		 327 gpmc: gpmc@50000000 {
328 compatible = "ti,omap4430-gpmc";
329 reg = <0x50000000 0x1000>;
330 #address-cells = <2>;
331 #size-cells = <1>;
8fea7d5a 332 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 333 gpmc,num-cs = <8>;
334 gpmc,num-waitpins = <4>;
335 ti,hwmods = "gpmc";
7b8b6af1
FV		 336 clocks = <&l3_iclk_div>;
337 clock-names = "fck";
1c7dbb55
JH		 338 };
339
6e6a9a50
SP		 340 i2c1: i2c@48070000 {
341 compatible = "ti,omap4-i2c";
d7118bbd 342 reg = <0x48070000 0x100>;
8fea7d5a 343 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 344 #address-cells = <1>;
345 #size-cells = <0>;
346 ti,hwmods = "i2c1";
347 };
348
349 i2c2: i2c@48072000 {
350 compatible = "ti,omap4-i2c";
d7118bbd 351 reg = <0x48072000 0x100>;
8fea7d5a 352 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 353 #address-cells = <1>;
354 #size-cells = <0>;
355 ti,hwmods = "i2c2";
356 };
357
358 i2c3: i2c@48060000 {
359 compatible = "ti,omap4-i2c";
d7118bbd 360 reg = <0x48060000 0x100>;
8fea7d5a 361 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 362 #address-cells = <1>;
363 #size-cells = <0>;
364 ti,hwmods = "i2c3";
365 };
366
d7118bbd 367 i2c4: i2c@4807a000 {
6e6a9a50 368 compatible = "ti,omap4-i2c";
d7118bbd 369 reg = <0x4807a000 0x100>;
8fea7d5a 370 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 371 #address-cells = <1>;
372 #size-cells = <0>;
373 ti,hwmods = "i2c4";
374 };
375
d7118bbd 376 i2c5: i2c@4807c000 {
6e6a9a50 377 compatible = "ti,omap4-i2c";
d7118bbd 378 reg = <0x4807c000 0x100>;
8fea7d5a 379 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 380 #address-cells = <1>;
381 #size-cells = <0>;
382 ti,hwmods = "i2c5";
383 };
384
fe0e09e4
SA		 385 hwspinlock: spinlock@4a0f6000 {
386 compatible = "ti,omap4-hwspinlock";
387 reg = <0x4a0f6000 0x1000>;
388 ti,hwmods = "spinlock";
34054213 389 #hwlock-cells = <1>;
fe0e09e4
SA		 390 };
391
43286b11
FB		 392 mcspi1: spi@48098000 {
393 compatible = "ti,omap4-mcspi";
394 reg = <0x48098000 0x200>;
8fea7d5a 395 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 396 #address-cells = <1>;
397 #size-cells = <0>;
398 ti,hwmods = "mcspi1";
399 ti,spi-num-cs = <4>;
2c2dc545
JH		 400 dmas = <&sdma 35>,
401 <&sdma 36>,
402 <&sdma 37>,
403 <&sdma 38>,
404 <&sdma 39>,
405 <&sdma 40>,
406 <&sdma 41>,
407 <&sdma 42>;
408 dma-names = "tx0", "rx0", "tx1", "rx1",
409 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 410 };
411
412 mcspi2: spi@4809a000 {
413 compatible = "ti,omap4-mcspi";
414 reg = <0x4809a000 0x200>;
8fea7d5a 415 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 416 #address-cells = <1>;
417 #size-cells = <0>;
418 ti,hwmods = "mcspi2";
419 ti,spi-num-cs = <2>;
2c2dc545
JH		 420 dmas = <&sdma 43>,
421 <&sdma 44>,
422 <&sdma 45>,
423 <&sdma 46>;
424 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 425 };
426
427 mcspi3: spi@480b8000 {
428 compatible = "ti,omap4-mcspi";
429 reg = <0x480b8000 0x200>;
8fea7d5a 430 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 431 #address-cells = <1>;
432 #size-cells = <0>;
433 ti,hwmods = "mcspi3";
434 ti,spi-num-cs = <2>;
2c2dc545
JH		 435 dmas = <&sdma 15>, <&sdma 16>;
436 dma-names = "tx0", "rx0";
43286b11
FB		 437 };
438
439 mcspi4: spi@480ba000 {
440 compatible = "ti,omap4-mcspi";
441 reg = <0x480ba000 0x200>;
8fea7d5a 442 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 443 #address-cells = <1>;
444 #size-cells = <0>;
445 ti,hwmods = "mcspi4";
446 ti,spi-num-cs = <1>;
2c2dc545
JH		 447 dmas = <&sdma 70>, <&sdma 71>;
448 dma-names = "tx0", "rx0";
43286b11
FB		 449 };
450
6b5de091
S		 451 uart1: serial@4806a000 {
452 compatible = "ti,omap4-uart";
8e80f660 453 reg = <0x4806a000 0x100>;
8fea7d5a 454 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 455 ti,hwmods = "uart1";
456 clock-frequency = <48000000>;
457 };
458
459 uart2: serial@4806c000 {
460 compatible = "ti,omap4-uart";
8e80f660 461 reg = <0x4806c000 0x100>;
8fea7d5a 462 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 463 ti,hwmods = "uart2";
464 clock-frequency = <48000000>;
465 };
466
467 uart3: serial@48020000 {
468 compatible = "ti,omap4-uart";
8e80f660 469 reg = <0x48020000 0x100>;
8fea7d5a 470 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 471 ti,hwmods = "uart3";
472 clock-frequency = <48000000>;
473 };
474
475 uart4: serial@4806e000 {
476 compatible = "ti,omap4-uart";
8e80f660 477 reg = <0x4806e000 0x100>;
8fea7d5a 478 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 479 ti,hwmods = "uart4";
480 clock-frequency = <48000000>;
481 };
482
483 uart5: serial@48066000 {
8e80f660
SG		 484 compatible = "ti,omap4-uart";
485 reg = <0x48066000 0x100>;
8fea7d5a 486 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 487 ti,hwmods = "uart5";
488 clock-frequency = <48000000>;
489 };
490
491 uart6: serial@48068000 {
8e80f660
SG		 492 compatible = "ti,omap4-uart";
493 reg = <0x48068000 0x100>;
8fea7d5a 494 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 495 ti,hwmods = "uart6";
496 clock-frequency = <48000000>;
497 };
5dd18b01
B		 498
499 mmc1: mmc@4809c000 {
500 compatible = "ti,omap4-hsmmc";
9a642362 501 reg = <0x4809c000 0x400>;
8fea7d5a 502 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 503 ti,hwmods = "mmc1";
504 ti,dual-volt;
505 ti,needs-special-reset;
2c2dc545
JH		 506 dmas = <&sdma 61>, <&sdma 62>;
507 dma-names = "tx", "rx";
cd042fe5 508 pbias-supply = <&pbias_mmc_reg>;
5dd18b01
B		 509 };
510
511 mmc2: mmc@480b4000 {
512 compatible = "ti,omap4-hsmmc";
9a642362 513 reg = <0x480b4000 0x400>;
8fea7d5a 514 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 515 ti,hwmods = "mmc2";
516 ti,needs-special-reset;
2c2dc545
JH		 517 dmas = <&sdma 47>, <&sdma 48>;
518 dma-names = "tx", "rx";
5dd18b01
B		 519 };
520
521 mmc3: mmc@480ad000 {
522 compatible = "ti,omap4-hsmmc";
9a642362 523 reg = <0x480ad000 0x400>;
8fea7d5a 524 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 525 ti,hwmods = "mmc3";
526 ti,needs-special-reset;
2c2dc545
JH		 527 dmas = <&sdma 77>, <&sdma 78>;
528 dma-names = "tx", "rx";
5dd18b01
B		 529 };
530
531 mmc4: mmc@480d1000 {
532 compatible = "ti,omap4-hsmmc";
9a642362 533 reg = <0x480d1000 0x400>;
8fea7d5a 534 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 535 ti,hwmods = "mmc4";
536 ti,needs-special-reset;
2c2dc545
JH		 537 dmas = <&sdma 57>, <&sdma 58>;
538 dma-names = "tx", "rx";
5dd18b01
B		 539 };
540
541 mmc5: mmc@480d5000 {
542 compatible = "ti,omap4-hsmmc";
9a642362 543 reg = <0x480d5000 0x400>;
8fea7d5a 544 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 545 ti,hwmods = "mmc5";
546 ti,needs-special-reset;
2c2dc545
JH		 547 dmas = <&sdma 59>, <&sdma 60>;
548 dma-names = "tx", "rx";
5dd18b01 549 };
5449fbc2 550
2dcfa56e
SA		 551 mmu_dsp: mmu@4a066000 {
552 compatible = "ti,omap4-iommu";
553 reg = <0x4a066000 0x100>;
554 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
555 ti,hwmods = "mmu_dsp";
556 };
557
558 mmu_ipu: mmu@55082000 {
559 compatible = "ti,omap4-iommu";
560 reg = <0x55082000 0x100>;
561 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
562 ti,hwmods = "mmu_ipu";
563 ti,iommu-bus-err-back;
564 };
565
5449fbc2
SP		 566 keypad: keypad@4ae1c000 {
567 compatible = "ti,omap4-keypad";
8cc8b89f 568 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 569 ti,hwmods = "kbd";
570 };
ffd5db24 571
cbb57f07
PU		 572 mcpdm: mcpdm@40132000 {
573 compatible = "ti,omap4-mcpdm";
574 reg = <0x40132000 0x7f>, /* MPU private access */
575 <0x49032000 0x7f>; /* L3 Interconnect */
576 reg-names = "mpu", "dma";
8fea7d5a 577 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 578 ti,hwmods = "mcpdm";
4e4ead73
SG		 579 dmas = <&sdma 65>,
580 <&sdma 66>;
581 dma-names = "up_link", "dn_link";
f15534ea 582 status = "disabled";
cbb57f07
PU		 583 };
584
585 dmic: dmic@4012e000 {
586 compatible = "ti,omap4-dmic";
587 reg = <0x4012e000 0x7f>, /* MPU private access */
588 <0x4902e000 0x7f>; /* L3 Interconnect */
589 reg-names = "mpu", "dma";
8fea7d5a 590 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 591 ti,hwmods = "dmic";
4e4ead73
SG		 592 dmas = <&sdma 67>;
593 dma-names = "up_link";
f15534ea 594 status = "disabled";
cbb57f07
PU		 595 };
596
ffd5db24
PU		 597 mcbsp1: mcbsp@40122000 {
598 compatible = "ti,omap4-mcbsp";
599 reg = <0x40122000 0xff>, /* MPU private access */
600 <0x49022000 0xff>; /* L3 Interconnect */
601 reg-names = "mpu", "dma";
8fea7d5a 602 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 603 interrupt-names = "common";
ffd5db24
PU		 604 ti,buffer-size = <128>;
605 ti,hwmods = "mcbsp1";
4e4ead73
SG		 606 dmas = <&sdma 33>,
607 <&sdma 34>;
608 dma-names = "tx", "rx";
f15534ea 609 status = "disabled";
ffd5db24
PU		 610 };
611
612 mcbsp2: mcbsp@40124000 {
613 compatible = "ti,omap4-mcbsp";
614 reg = <0x40124000 0xff>, /* MPU private access */
615 <0x49024000 0xff>; /* L3 Interconnect */
616 reg-names = "mpu", "dma";
8fea7d5a 617 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 618 interrupt-names = "common";
ffd5db24
PU		 619 ti,buffer-size = <128>;
620 ti,hwmods = "mcbsp2";
4e4ead73
SG		 621 dmas = <&sdma 17>,
622 <&sdma 18>;
623 dma-names = "tx", "rx";
f15534ea 624 status = "disabled";
ffd5db24
PU		 625 };
626
627 mcbsp3: mcbsp@40126000 {
628 compatible = "ti,omap4-mcbsp";
629 reg = <0x40126000 0xff>, /* MPU private access */
630 <0x49026000 0xff>; /* L3 Interconnect */
631 reg-names = "mpu", "dma";
8fea7d5a 632 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 633 interrupt-names = "common";
ffd5db24
PU		 634 ti,buffer-size = <128>;
635 ti,hwmods = "mcbsp3";
4e4ead73
SG		 636 dmas = <&sdma 19>,
637 <&sdma 20>;
638 dma-names = "tx", "rx";
f15534ea 639 status = "disabled";
ffd5db24 640 };
df692a92 641
84d89c31
SA		 642 mailbox: mailbox@4a0f4000 {
643 compatible = "ti,omap4-mailbox";
644 reg = <0x4a0f4000 0x200>;
645 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
646 ti,hwmods = "mailbox";
41ffada1
SA		 647 ti,mbox-num-users = <3>;
648 ti,mbox-num-fifos = <8>;
84d89c31
SA		 649 };
650
df692a92 651 timer1: timer@4ae18000 {
002e1ec5 652 compatible = "ti,omap5430-timer";
df692a92 653 reg = <0x4ae18000 0x80>;
8fea7d5a 654 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 655 ti,hwmods = "timer1";
656 ti,timer-alwon;
657 };
658
659 timer2: timer@48032000 {
002e1ec5 660 compatible = "ti,omap5430-timer";
df692a92 661 reg = <0x48032000 0x80>;
8fea7d5a 662 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 663 ti,hwmods = "timer2";
664 };
665
666 timer3: timer@48034000 {
002e1ec5 667 compatible = "ti,omap5430-timer";
df692a92 668 reg = <0x48034000 0x80>;
8fea7d5a 669 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 670 ti,hwmods = "timer3";
671 };
672
673 timer4: timer@48036000 {
002e1ec5 674 compatible = "ti,omap5430-timer";
df692a92 675 reg = <0x48036000 0x80>;
8fea7d5a 676 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 677 ti,hwmods = "timer4";
678 };
679
680 timer5: timer@40138000 {
002e1ec5 681 compatible = "ti,omap5430-timer";
df692a92
JH		 682 reg = <0x40138000 0x80>,
683 <0x49038000 0x80>;
8fea7d5a 684 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 685 ti,hwmods = "timer5";
686 ti,timer-dsp;
8341613a 687 ti,timer-pwm;
df692a92
JH		 688 };
689
690 timer6: timer@4013a000 {
002e1ec5 691 compatible = "ti,omap5430-timer";
df692a92
JH		 692 reg = <0x4013a000 0x80>,
693 <0x4903a000 0x80>;
8fea7d5a 694 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 695 ti,hwmods = "timer6";
696 ti,timer-dsp;
697 ti,timer-pwm;
698 };
699
700 timer7: timer@4013c000 {
002e1ec5 701 compatible = "ti,omap5430-timer";
df692a92
JH		 702 reg = <0x4013c000 0x80>,
703 <0x4903c000 0x80>;
8fea7d5a 704 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 705 ti,hwmods = "timer7";
706 ti,timer-dsp;
707 };
708
709 timer8: timer@4013e000 {
002e1ec5 710 compatible = "ti,omap5430-timer";
df692a92
JH		 711 reg = <0x4013e000 0x80>,
712 <0x4903e000 0x80>;
8fea7d5a 713 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 714 ti,hwmods = "timer8";
715 ti,timer-dsp;
716 ti,timer-pwm;
717 };
718
719 timer9: timer@4803e000 {
002e1ec5 720 compatible = "ti,omap5430-timer";
df692a92 721 reg = <0x4803e000 0x80>;
8fea7d5a 722 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 723 ti,hwmods = "timer9";
8341613a 724 ti,timer-pwm;
df692a92
JH		 725 };
726
727 timer10: timer@48086000 {
002e1ec5 728 compatible = "ti,omap5430-timer";
df692a92 729 reg = <0x48086000 0x80>;
8fea7d5a 730 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 731 ti,hwmods = "timer10";
8341613a 732 ti,timer-pwm;
df692a92
JH		 733 };
734
735 timer11: timer@48088000 {
002e1ec5 736 compatible = "ti,omap5430-timer";
df692a92 737 reg = <0x48088000 0x80>;
8fea7d5a 738 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 739 ti,hwmods = "timer11";
740 ti,timer-pwm;
741 };
e6900ddf 742
55452197
LV		 743 wdt2: wdt@4ae14000 {
744 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
745 reg = <0x4ae14000 0x80>;
8fea7d5a 746 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 747 ti,hwmods = "wd_timer2";
748 };
749
1a5fe3ca
AT		 750 dmm@4e000000 {
751 compatible = "ti,omap5-dmm";
752 reg = <0x4e000000 0x800>;
753 interrupts = <0 113 0x4>;
754 ti,hwmods = "dmm";
755 };
756
8906d654 757 emif1: emif@4c000000 {
e6900ddf
LV		 758 compatible = "ti,emif-4d5";
759 ti,hwmods = "emif1";
f12ecbe2 760 ti,no-idle-on-init;
e6900ddf
LV		 761 phy-type = <2>; /* DDR PHY type: Intelli PHY */
762 reg = <0x4c000000 0x400>;
8fea7d5a 763 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 764 hw-caps-read-idle-ctrl;
765 hw-caps-ll-interface;
766 hw-caps-temp-alert;
767 };
768
8906d654 769 emif2: emif@4d000000 {
e6900ddf
LV		 770 compatible = "ti,emif-4d5";
771 ti,hwmods = "emif2";
f12ecbe2 772 ti,no-idle-on-init;
e6900ddf
LV		 773 phy-type = <2>; /* DDR PHY type: Intelli PHY */
774 reg = <0x4d000000 0x400>;
8fea7d5a 775 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 776 hw-caps-read-idle-ctrl;
777 hw-caps-ll-interface;
778 hw-caps-temp-alert;
779 };
fedc428e 780
b297c292
RQ		 781 omap_control_usb2phy: control-phy@4a002300 {
782 compatible = "ti,control-phy-usb2";
783 reg = <0x4a002300 0x4>;
784 reg-names = "power";
785 };
786
787 omap_control_usb3phy: control-phy@4a002370 {
788 compatible = "ti,control-phy-pipe3";
789 reg = <0x4a002370 0x4>;
790 reg-names = "power";
fedc428e 791 };
e9831967 792
e3a412c9 793 usb3: omap_dwc3@4a020000 {
72f6f957
KVA		 794 compatible = "ti,dwc3";
795 ti,hwmods = "usb_otg_ss";
6f61ee23 796 reg = <0x4a020000 0x10000>;
8fea7d5a 797 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 798 #address-cells = <1>;
799 #size-cells = <1>;
800 utmi-mode = <2>;
801 ranges;
802 dwc3@4a030000 {
22a5aa17 803 compatible = "snps,dwc3";
6f61ee23 804 reg = <0x4a030000 0x10000>;
8fea7d5a 805 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
073addc8
KVA		 806 phys = <&usb2_phy>, <&usb3_phy>;
807 phy-names = "usb2-phy", "usb3-phy";
c47ee6ee 808 dr_mode = "peripheral";
72f6f957
KVA		 809 tx-fifo-resize;
810 };
811 };
812
b6731f78 813 ocp2scp@4a080000 {
e9831967
KVA		 814 compatible = "ti,omap-ocp2scp";
815 #address-cells = <1>;
816 #size-cells = <1>;
b6731f78 817 reg = <0x4a080000 0x20>;
e9831967
KVA		 818 ranges;
819 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 820 usb2_phy: usb2phy@4a084000 {
821 compatible = "ti,omap-usb2";
822 reg = <0x4a084000 0x7c>;
b297c292 823 ctrl-module = <&omap_control_usb2phy>;
c65d0ad5
RQ		 824 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
825 clock-names = "wkupclk", "refclk";
073addc8 826 #phy-cells = <0>;
ae6a32d2
KVA		 827 };
828
829 usb3_phy: usb3phy@4a084400 {
830 compatible = "ti,omap-usb3";
831 reg = <0x4a084400 0x80>,
832 <0x4a084800 0x64>,
833 <0x4a084c00 0x40>;
834 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
b297c292 835 ctrl-module = <&omap_control_usb3phy>;
ada76576
RQ		 836 clocks = <&usb_phy_cm_clk32k>,
837 <&sys_clkin>,
838 <&usb_otg_ss_refclk960m>;
839 clock-names = "wkupclk",
840 "sysclk",
841 "refclk";
073addc8 842 #phy-cells = <0>;
ae6a32d2 843 };
e9831967 844 };
ed7f8e8a
RQ		 845
846 usbhstll: usbhstll@4a062000 {
847 compatible = "ti,usbhs-tll";
848 reg = <0x4a062000 0x1000>;
849 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
850 ti,hwmods = "usb_tll_hs";
851 };
852
853 usbhshost: usbhshost@4a064000 {
854 compatible = "ti,usbhs-host";
855 reg = <0x4a064000 0x800>;
856 ti,hwmods = "usb_host_hs";
857 #address-cells = <1>;
858 #size-cells = <1>;
859 ranges;
051fc06d
RQ		 860 clocks = <&l3init_60m_fclk>,
861 <&xclk60mhsp1_ck>,
862 <&xclk60mhsp2_ck>;
863 clock-names = "refclk_60m_int",
864 "refclk_60m_ext_p1",
865 "refclk_60m_ext_p2";
ed7f8e8a
RQ		 866
867 usbhsohci: ohci@4a064800 {
a2525e54 868 compatible = "ti,ohci-omap3";
ed7f8e8a
RQ		 869 reg = <0x4a064800 0x400>;
870 interrupt-parent = <&gic>;
871 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
872 };
873
874 usbhsehci: ehci@4a064c00 {
a2525e54 875 compatible = "ti,ehci-omap";
ed7f8e8a
RQ		 876 reg = <0x4a064c00 0x400>;
877 interrupt-parent = <&gic>;
878 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
879 };
880 };
cbad26db 881
1b761fc5 882 bandgap: bandgap@4a0021e0 {
cbad26db
EV		 883 reg = <0x4a0021e0 0xc
884 0x4a00232c 0xc
885 0x4a002380 0x2c
886 0x4a0023C0 0x3c>;
887 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
888 compatible = "ti,omap5430-bandgap";
1b761fc5
EV		 889
890 #thermal-sensor-cells = <1>;
cbad26db 891 };
4f82952c
B		 892
893 omap_control_sata: control-phy@4a002374 {
894 compatible = "ti,control-phy-pipe3";
895 reg = <0x4a002374 0x4>;
896 reg-names = "power";
897 clocks = <&sys_clkin>;
898 clock-names = "sysclk";
899 };
900
901 /* OCP2SCP3 */
902 ocp2scp@4a090000 {
903 compatible = "ti,omap-ocp2scp";
904 #address-cells = <1>;
905 #size-cells = <1>;
906 reg = <0x4a090000 0x20>;
907 ranges;
908 ti,hwmods = "ocp2scp3";
909 sata_phy: phy@4a096000 {
910 compatible = "ti,phy-pipe3-sata";
911 reg = <0x4A096000 0x80>, /* phy_rx */
912 <0x4A096400 0x64>, /* phy_tx */
913 <0x4A096800 0x40>; /* pll_ctrl */
914 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
915 ctrl-module = <&omap_control_sata>;
916 clocks = <&sys_clkin>;
917 clock-names = "sysclk";
918 #phy-cells = <0>;
919 };
920 };
921
922 sata: sata@4a141100 {
923 compatible = "snps,dwc-ahci";
924 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
925 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
926 phys = <&sata_phy>;
927 phy-names = "sata-phy";
928 clocks = <&sata_ref_clk>;
929 ti,hwmods = "sata";
930 };
931
e7585c4f
TV		 932 dss: dss@58000000 {
933 compatible = "ti,omap5-dss";
934 reg = <0x58000000 0x80>;
935 status = "disabled";
936 ti,hwmods = "dss_core";
937 clocks = <&dss_dss_clk>;
938 clock-names = "fck";
939 #address-cells = <1>;
940 #size-cells = <1>;
941 ranges;
942
943 dispc@58001000 {
944 compatible = "ti,omap5-dispc";
945 reg = <0x58001000 0x1000>;
946 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
947 ti,hwmods = "dss_dispc";
948 clocks = <&dss_dss_clk>;
949 clock-names = "fck";
950 };
951
952 dsi1: encoder@58004000 {
953 compatible = "ti,omap5-dsi";
954 reg = <0x58004000 0x200>,
955 <0x58004200 0x40>,
956 <0x58004300 0x40>;
957 reg-names = "proto", "phy", "pll";
958 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
959 status = "disabled";
960 ti,hwmods = "dss_dsi1";
961 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
962 clock-names = "fck", "sys_clk";
963 };
964
965 dsi2: encoder@58005000 {
966 compatible = "ti,omap5-dsi";
967 reg = <0x58009000 0x200>,
968 <0x58009200 0x40>,
969 <0x58009300 0x40>;
970 reg-names = "proto", "phy", "pll";
971 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
972 status = "disabled";
973 ti,hwmods = "dss_dsi2";
974 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
975 clock-names = "fck", "sys_clk";
976 };
977
978 hdmi: encoder@58060000 {
979 compatible = "ti,omap5-hdmi";
980 reg = <0x58040000 0x200>,
981 <0x58040200 0x80>,
982 <0x58040300 0x80>,
983 <0x58060000 0x19000>;
984 reg-names = "wp", "pll", "phy", "core";
985 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
986 status = "disabled";
987 ti,hwmods = "dss_hdmi";
988 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
989 clock-names = "fck", "sys_clk";
7d0fde39
JS		 990 dmas = <&sdma 76>;
991 dma-names = "audio_tx";
e7585c4f
TV		 992 };
993 };
07b9b3d9
AT		 994
995 abb_mpu: regulator-abb-mpu {
996 compatible = "ti,abb-v2";
997 regulator-name = "abb_mpu";
998 #address-cells = <0>;
999 #size-cells = <0>;
1000 clocks = <&sys_clkin>;
1001 ti,settling-time = <50>;
1002 ti,clock-cycles = <16>;
1003
1004 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1005 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1006 reg-names = "base-address", "int-address",
1007 "efuse-address", "ldo-address";
1008 ti,tranxdone-status-mask = <0x80>;
1009 /* LDOVBBMPU_MUX_CTRL */
1010 ti,ldovbb-override-mask = <0x400>;
1011 /* LDOVBBMPU_VSET_OUT */
1012 ti,ldovbb-vset-mask = <0x1F>;
1013
1014 /*
1015 * NOTE: only FBB mode used but actual vset will
1016 * determine final biasing
1017 */
1018 ti,abb_info = <
1019 /*uV ABB efuse rbb_m fbb_m vset_m*/
1020 1060000 0 0x0 0 0x02000000 0x01F00000
1021 1250000 0 0x4 0 0x02000000 0x01F00000
1022 >;
1023 };
1024
1025 abb_mm: regulator-abb-mm {
1026 compatible = "ti,abb-v2";
1027 regulator-name = "abb_mm";
1028 #address-cells = <0>;
1029 #size-cells = <0>;
1030 clocks = <&sys_clkin>;
1031 ti,settling-time = <50>;
1032 ti,clock-cycles = <16>;
1033
1034 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1035 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1036 reg-names = "base-address", "int-address",
1037 "efuse-address", "ldo-address";
1038 ti,tranxdone-status-mask = <0x80000000>;
1039 /* LDOVBBMM_MUX_CTRL */
1040 ti,ldovbb-override-mask = <0x400>;
1041 /* LDOVBBMM_VSET_OUT */
1042 ti,ldovbb-vset-mask = <0x1F>;
1043
1044 /*
1045 * NOTE: only FBB mode used but actual vset will
1046 * determine final biasing
1047 */
1048 ti,abb_info = <
1049 /*uV ABB efuse rbb_m fbb_m vset_m*/
1050 1025000 0 0x0 0 0x02000000 0x01F00000
1051 1120000 0 0x4 0 0x02000000 0x01F00000
1052 >;
1053 };
6b5de091
S		 1054 };
1055};
85dc74e9
TK		 1056
1057/include/ "omap54xx-clocks.dtsi"
Ubuntu Hirsute Linux kernel mirror