]>
Commit | Line | Data |
---|---|---|
6b5de091 S |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
6d624eab | 10 | #include <dt-bindings/gpio/gpio.h> |
8fea7d5a | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
bcd3cca7 | 12 | #include <dt-bindings/pinctrl/omap.h> |
6b5de091 | 13 | |
98ef7957 | 14 | #include "skeleton.dtsi" |
6b5de091 S |
15 | |
16 | / { | |
ba1829bc SS |
17 | #address-cells = <1>; |
18 | #size-cells = <1>; | |
19 | ||
6b5de091 S |
20 | compatible = "ti,omap5"; |
21 | interrupt-parent = <&gic>; | |
22 | ||
23 | aliases { | |
20b80942 NM |
24 | i2c0 = &i2c1; |
25 | i2c1 = &i2c2; | |
26 | i2c2 = &i2c3; | |
27 | i2c3 = &i2c4; | |
28 | i2c4 = &i2c5; | |
6b5de091 S |
29 | serial0 = &uart1; |
30 | serial1 = &uart2; | |
31 | serial2 = &uart3; | |
32 | serial3 = &uart4; | |
33 | serial4 = &uart5; | |
34 | serial5 = &uart6; | |
35 | }; | |
36 | ||
37 | cpus { | |
eeb25fd5 LP |
38 | #address-cells = <1>; |
39 | #size-cells = <0>; | |
40 | ||
b8981d71 | 41 | cpu0: cpu@0 { |
eeb25fd5 | 42 | device_type = "cpu"; |
6b5de091 | 43 | compatible = "arm,cortex-a15"; |
eeb25fd5 | 44 | reg = <0x0>; |
6c24894d K |
45 | |
46 | operating-points = < | |
47 | /* kHz uV */ | |
48 | 500000 880000 | |
49 | 1000000 1060000 | |
50 | 1500000 1250000 | |
51 | >; | |
6b5de091 S |
52 | }; |
53 | cpu@1 { | |
eeb25fd5 | 54 | device_type = "cpu"; |
6b5de091 | 55 | compatible = "arm,cortex-a15"; |
eeb25fd5 | 56 | reg = <0x1>; |
6b5de091 S |
57 | }; |
58 | }; | |
59 | ||
b45ccc4e SS |
60 | timer { |
61 | compatible = "arm,armv7-timer"; | |
8fea7d5a FV |
62 | /* PPI secure/nonsecure IRQ */ |
63 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
64 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
65 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
66 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; | |
b45ccc4e SS |
67 | }; |
68 | ||
ba1829bc SS |
69 | gic: interrupt-controller@48211000 { |
70 | compatible = "arm,cortex-a15-gic"; | |
71 | interrupt-controller; | |
72 | #interrupt-cells = <3>; | |
73 | reg = <0x48211000 0x1000>, | |
0129c16c SS |
74 | <0x48212000 0x1000>, |
75 | <0x48214000 0x2000>, | |
76 | <0x48216000 0x2000>; | |
ba1829bc SS |
77 | }; |
78 | ||
6b5de091 S |
79 | /* |
80 | * The soc node represents the soc top level view. It is uses for IPs | |
81 | * that are not memory mapped in the MPU view or for the MPU itself. | |
82 | */ | |
83 | soc { | |
84 | compatible = "ti,omap-infra"; | |
85 | mpu { | |
86 | compatible = "ti,omap5-mpu"; | |
87 | ti,hwmods = "mpu"; | |
88 | }; | |
89 | }; | |
90 | ||
91 | /* | |
92 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
93 | * The real OMAP interconnect network is quite complex. | |
94 | * Since that will not bring real advantage to represent that in DT for | |
95 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
96 | * hierarchy. | |
97 | */ | |
98 | ocp { | |
99 | compatible = "ti,omap4-l3-noc", "simple-bus"; | |
100 | #address-cells = <1>; | |
101 | #size-cells = <1>; | |
102 | ranges; | |
103 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | |
20a60eaa SS |
104 | reg = <0x44000000 0x2000>, |
105 | <0x44800000 0x3000>, | |
106 | <0x45000000 0x4000>; | |
8fea7d5a FV |
107 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
108 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
6b5de091 | 109 | |
3b3132f7 JH |
110 | counter32k: counter@4ae04000 { |
111 | compatible = "ti,omap-counter32k"; | |
112 | reg = <0x4ae04000 0x40>; | |
113 | ti,hwmods = "counter_32k"; | |
114 | }; | |
115 | ||
5da6a2d5 PU |
116 | omap5_pmx_core: pinmux@4a002840 { |
117 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
118 | reg = <0x4a002840 0x01b6>; | |
119 | #address-cells = <1>; | |
120 | #size-cells = <0>; | |
121 | pinctrl-single,register-width = <16>; | |
122 | pinctrl-single,function-mask = <0x7fff>; | |
123 | }; | |
124 | omap5_pmx_wkup: pinmux@4ae0c840 { | |
125 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
126 | reg = <0x4ae0c840 0x0038>; | |
127 | #address-cells = <1>; | |
128 | #size-cells = <0>; | |
129 | pinctrl-single,register-width = <16>; | |
130 | pinctrl-single,function-mask = <0x7fff>; | |
131 | }; | |
132 | ||
2c2dc545 JH |
133 | sdma: dma-controller@4a056000 { |
134 | compatible = "ti,omap4430-sdma"; | |
135 | reg = <0x4a056000 0x1000>; | |
8fea7d5a FV |
136 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
137 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
138 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
139 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
2c2dc545 JH |
140 | #dma-cells = <1>; |
141 | #dma-channels = <32>; | |
142 | #dma-requests = <127>; | |
143 | }; | |
144 | ||
6b5de091 S |
145 | gpio1: gpio@4ae10000 { |
146 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 147 | reg = <0x4ae10000 0x200>; |
8fea7d5a | 148 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 | 149 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 150 | ti,gpio-always-on; |
6b5de091 S |
151 | gpio-controller; |
152 | #gpio-cells = <2>; | |
153 | interrupt-controller; | |
ff5c9059 | 154 | #interrupt-cells = <2>; |
6b5de091 S |
155 | }; |
156 | ||
157 | gpio2: gpio@48055000 { | |
158 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 159 | reg = <0x48055000 0x200>; |
8fea7d5a | 160 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
161 | ti,hwmods = "gpio2"; |
162 | gpio-controller; | |
163 | #gpio-cells = <2>; | |
164 | interrupt-controller; | |
ff5c9059 | 165 | #interrupt-cells = <2>; |
6b5de091 S |
166 | }; |
167 | ||
168 | gpio3: gpio@48057000 { | |
169 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 170 | reg = <0x48057000 0x200>; |
8fea7d5a | 171 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
172 | ti,hwmods = "gpio3"; |
173 | gpio-controller; | |
174 | #gpio-cells = <2>; | |
175 | interrupt-controller; | |
ff5c9059 | 176 | #interrupt-cells = <2>; |
6b5de091 S |
177 | }; |
178 | ||
179 | gpio4: gpio@48059000 { | |
180 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 181 | reg = <0x48059000 0x200>; |
8fea7d5a | 182 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
183 | ti,hwmods = "gpio4"; |
184 | gpio-controller; | |
185 | #gpio-cells = <2>; | |
186 | interrupt-controller; | |
ff5c9059 | 187 | #interrupt-cells = <2>; |
6b5de091 S |
188 | }; |
189 | ||
190 | gpio5: gpio@4805b000 { | |
191 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 192 | reg = <0x4805b000 0x200>; |
8fea7d5a | 193 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
194 | ti,hwmods = "gpio5"; |
195 | gpio-controller; | |
196 | #gpio-cells = <2>; | |
197 | interrupt-controller; | |
ff5c9059 | 198 | #interrupt-cells = <2>; |
6b5de091 S |
199 | }; |
200 | ||
201 | gpio6: gpio@4805d000 { | |
202 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 203 | reg = <0x4805d000 0x200>; |
8fea7d5a | 204 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
205 | ti,hwmods = "gpio6"; |
206 | gpio-controller; | |
207 | #gpio-cells = <2>; | |
208 | interrupt-controller; | |
ff5c9059 | 209 | #interrupt-cells = <2>; |
6b5de091 S |
210 | }; |
211 | ||
212 | gpio7: gpio@48051000 { | |
213 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 214 | reg = <0x48051000 0x200>; |
8fea7d5a | 215 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
216 | ti,hwmods = "gpio7"; |
217 | gpio-controller; | |
218 | #gpio-cells = <2>; | |
219 | interrupt-controller; | |
ff5c9059 | 220 | #interrupt-cells = <2>; |
6b5de091 S |
221 | }; |
222 | ||
223 | gpio8: gpio@48053000 { | |
224 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 225 | reg = <0x48053000 0x200>; |
8fea7d5a | 226 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
227 | ti,hwmods = "gpio8"; |
228 | gpio-controller; | |
229 | #gpio-cells = <2>; | |
230 | interrupt-controller; | |
ff5c9059 | 231 | #interrupt-cells = <2>; |
6b5de091 S |
232 | }; |
233 | ||
1c7dbb55 JH |
234 | gpmc: gpmc@50000000 { |
235 | compatible = "ti,omap4430-gpmc"; | |
236 | reg = <0x50000000 0x1000>; | |
237 | #address-cells = <2>; | |
238 | #size-cells = <1>; | |
8fea7d5a | 239 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
1c7dbb55 JH |
240 | gpmc,num-cs = <8>; |
241 | gpmc,num-waitpins = <4>; | |
242 | ti,hwmods = "gpmc"; | |
243 | }; | |
244 | ||
6e6a9a50 SP |
245 | i2c1: i2c@48070000 { |
246 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 247 | reg = <0x48070000 0x100>; |
8fea7d5a | 248 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
249 | #address-cells = <1>; |
250 | #size-cells = <0>; | |
251 | ti,hwmods = "i2c1"; | |
252 | }; | |
253 | ||
254 | i2c2: i2c@48072000 { | |
255 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 256 | reg = <0x48072000 0x100>; |
8fea7d5a | 257 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
258 | #address-cells = <1>; |
259 | #size-cells = <0>; | |
260 | ti,hwmods = "i2c2"; | |
261 | }; | |
262 | ||
263 | i2c3: i2c@48060000 { | |
264 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 265 | reg = <0x48060000 0x100>; |
8fea7d5a | 266 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
267 | #address-cells = <1>; |
268 | #size-cells = <0>; | |
269 | ti,hwmods = "i2c3"; | |
270 | }; | |
271 | ||
d7118bbd | 272 | i2c4: i2c@4807a000 { |
6e6a9a50 | 273 | compatible = "ti,omap4-i2c"; |
d7118bbd | 274 | reg = <0x4807a000 0x100>; |
8fea7d5a | 275 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
276 | #address-cells = <1>; |
277 | #size-cells = <0>; | |
278 | ti,hwmods = "i2c4"; | |
279 | }; | |
280 | ||
d7118bbd | 281 | i2c5: i2c@4807c000 { |
6e6a9a50 | 282 | compatible = "ti,omap4-i2c"; |
d7118bbd | 283 | reg = <0x4807c000 0x100>; |
8fea7d5a | 284 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
285 | #address-cells = <1>; |
286 | #size-cells = <0>; | |
287 | ti,hwmods = "i2c5"; | |
288 | }; | |
289 | ||
fe0e09e4 SA |
290 | hwspinlock: spinlock@4a0f6000 { |
291 | compatible = "ti,omap4-hwspinlock"; | |
292 | reg = <0x4a0f6000 0x1000>; | |
293 | ti,hwmods = "spinlock"; | |
294 | }; | |
295 | ||
43286b11 FB |
296 | mcspi1: spi@48098000 { |
297 | compatible = "ti,omap4-mcspi"; | |
298 | reg = <0x48098000 0x200>; | |
8fea7d5a | 299 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
300 | #address-cells = <1>; |
301 | #size-cells = <0>; | |
302 | ti,hwmods = "mcspi1"; | |
303 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
304 | dmas = <&sdma 35>, |
305 | <&sdma 36>, | |
306 | <&sdma 37>, | |
307 | <&sdma 38>, | |
308 | <&sdma 39>, | |
309 | <&sdma 40>, | |
310 | <&sdma 41>, | |
311 | <&sdma 42>; | |
312 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
313 | "tx2", "rx2", "tx3", "rx3"; | |
43286b11 FB |
314 | }; |
315 | ||
316 | mcspi2: spi@4809a000 { | |
317 | compatible = "ti,omap4-mcspi"; | |
318 | reg = <0x4809a000 0x200>; | |
8fea7d5a | 319 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
320 | #address-cells = <1>; |
321 | #size-cells = <0>; | |
322 | ti,hwmods = "mcspi2"; | |
323 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
324 | dmas = <&sdma 43>, |
325 | <&sdma 44>, | |
326 | <&sdma 45>, | |
327 | <&sdma 46>; | |
328 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
43286b11 FB |
329 | }; |
330 | ||
331 | mcspi3: spi@480b8000 { | |
332 | compatible = "ti,omap4-mcspi"; | |
333 | reg = <0x480b8000 0x200>; | |
8fea7d5a | 334 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
335 | #address-cells = <1>; |
336 | #size-cells = <0>; | |
337 | ti,hwmods = "mcspi3"; | |
338 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
339 | dmas = <&sdma 15>, <&sdma 16>; |
340 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
341 | }; |
342 | ||
343 | mcspi4: spi@480ba000 { | |
344 | compatible = "ti,omap4-mcspi"; | |
345 | reg = <0x480ba000 0x200>; | |
8fea7d5a | 346 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
347 | #address-cells = <1>; |
348 | #size-cells = <0>; | |
349 | ti,hwmods = "mcspi4"; | |
350 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
351 | dmas = <&sdma 70>, <&sdma 71>; |
352 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
353 | }; |
354 | ||
6b5de091 S |
355 | uart1: serial@4806a000 { |
356 | compatible = "ti,omap4-uart"; | |
8e80f660 | 357 | reg = <0x4806a000 0x100>; |
8fea7d5a | 358 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
359 | ti,hwmods = "uart1"; |
360 | clock-frequency = <48000000>; | |
361 | }; | |
362 | ||
363 | uart2: serial@4806c000 { | |
364 | compatible = "ti,omap4-uart"; | |
8e80f660 | 365 | reg = <0x4806c000 0x100>; |
8fea7d5a | 366 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
367 | ti,hwmods = "uart2"; |
368 | clock-frequency = <48000000>; | |
369 | }; | |
370 | ||
371 | uart3: serial@48020000 { | |
372 | compatible = "ti,omap4-uart"; | |
8e80f660 | 373 | reg = <0x48020000 0x100>; |
8fea7d5a | 374 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
375 | ti,hwmods = "uart3"; |
376 | clock-frequency = <48000000>; | |
377 | }; | |
378 | ||
379 | uart4: serial@4806e000 { | |
380 | compatible = "ti,omap4-uart"; | |
8e80f660 | 381 | reg = <0x4806e000 0x100>; |
8fea7d5a | 382 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
383 | ti,hwmods = "uart4"; |
384 | clock-frequency = <48000000>; | |
385 | }; | |
386 | ||
387 | uart5: serial@48066000 { | |
8e80f660 SG |
388 | compatible = "ti,omap4-uart"; |
389 | reg = <0x48066000 0x100>; | |
8fea7d5a | 390 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
391 | ti,hwmods = "uart5"; |
392 | clock-frequency = <48000000>; | |
393 | }; | |
394 | ||
395 | uart6: serial@48068000 { | |
8e80f660 SG |
396 | compatible = "ti,omap4-uart"; |
397 | reg = <0x48068000 0x100>; | |
8fea7d5a | 398 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
399 | ti,hwmods = "uart6"; |
400 | clock-frequency = <48000000>; | |
401 | }; | |
5dd18b01 B |
402 | |
403 | mmc1: mmc@4809c000 { | |
404 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 405 | reg = <0x4809c000 0x400>; |
8fea7d5a | 406 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
407 | ti,hwmods = "mmc1"; |
408 | ti,dual-volt; | |
409 | ti,needs-special-reset; | |
2c2dc545 JH |
410 | dmas = <&sdma 61>, <&sdma 62>; |
411 | dma-names = "tx", "rx"; | |
5dd18b01 B |
412 | }; |
413 | ||
414 | mmc2: mmc@480b4000 { | |
415 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 416 | reg = <0x480b4000 0x400>; |
8fea7d5a | 417 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
418 | ti,hwmods = "mmc2"; |
419 | ti,needs-special-reset; | |
2c2dc545 JH |
420 | dmas = <&sdma 47>, <&sdma 48>; |
421 | dma-names = "tx", "rx"; | |
5dd18b01 B |
422 | }; |
423 | ||
424 | mmc3: mmc@480ad000 { | |
425 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 426 | reg = <0x480ad000 0x400>; |
8fea7d5a | 427 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
428 | ti,hwmods = "mmc3"; |
429 | ti,needs-special-reset; | |
2c2dc545 JH |
430 | dmas = <&sdma 77>, <&sdma 78>; |
431 | dma-names = "tx", "rx"; | |
5dd18b01 B |
432 | }; |
433 | ||
434 | mmc4: mmc@480d1000 { | |
435 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 436 | reg = <0x480d1000 0x400>; |
8fea7d5a | 437 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
438 | ti,hwmods = "mmc4"; |
439 | ti,needs-special-reset; | |
2c2dc545 JH |
440 | dmas = <&sdma 57>, <&sdma 58>; |
441 | dma-names = "tx", "rx"; | |
5dd18b01 B |
442 | }; |
443 | ||
444 | mmc5: mmc@480d5000 { | |
445 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 446 | reg = <0x480d5000 0x400>; |
8fea7d5a | 447 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
448 | ti,hwmods = "mmc5"; |
449 | ti,needs-special-reset; | |
2c2dc545 JH |
450 | dmas = <&sdma 59>, <&sdma 60>; |
451 | dma-names = "tx", "rx"; | |
5dd18b01 | 452 | }; |
5449fbc2 SP |
453 | |
454 | keypad: keypad@4ae1c000 { | |
455 | compatible = "ti,omap4-keypad"; | |
8cc8b89f | 456 | reg = <0x4ae1c000 0x400>; |
5449fbc2 SP |
457 | ti,hwmods = "kbd"; |
458 | }; | |
ffd5db24 | 459 | |
cbb57f07 PU |
460 | mcpdm: mcpdm@40132000 { |
461 | compatible = "ti,omap4-mcpdm"; | |
462 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
463 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
464 | reg-names = "mpu", "dma"; | |
8fea7d5a | 465 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
cbb57f07 | 466 | ti,hwmods = "mcpdm"; |
4e4ead73 SG |
467 | dmas = <&sdma 65>, |
468 | <&sdma 66>; | |
469 | dma-names = "up_link", "dn_link"; | |
cbb57f07 PU |
470 | }; |
471 | ||
472 | dmic: dmic@4012e000 { | |
473 | compatible = "ti,omap4-dmic"; | |
474 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
475 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
476 | reg-names = "mpu", "dma"; | |
8fea7d5a | 477 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
cbb57f07 | 478 | ti,hwmods = "dmic"; |
4e4ead73 SG |
479 | dmas = <&sdma 67>; |
480 | dma-names = "up_link"; | |
cbb57f07 PU |
481 | }; |
482 | ||
ffd5db24 PU |
483 | mcbsp1: mcbsp@40122000 { |
484 | compatible = "ti,omap4-mcbsp"; | |
485 | reg = <0x40122000 0xff>, /* MPU private access */ | |
486 | <0x49022000 0xff>; /* L3 Interconnect */ | |
487 | reg-names = "mpu", "dma"; | |
8fea7d5a | 488 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 489 | interrupt-names = "common"; |
ffd5db24 PU |
490 | ti,buffer-size = <128>; |
491 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
492 | dmas = <&sdma 33>, |
493 | <&sdma 34>; | |
494 | dma-names = "tx", "rx"; | |
ffd5db24 PU |
495 | }; |
496 | ||
497 | mcbsp2: mcbsp@40124000 { | |
498 | compatible = "ti,omap4-mcbsp"; | |
499 | reg = <0x40124000 0xff>, /* MPU private access */ | |
500 | <0x49024000 0xff>; /* L3 Interconnect */ | |
501 | reg-names = "mpu", "dma"; | |
8fea7d5a | 502 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 503 | interrupt-names = "common"; |
ffd5db24 PU |
504 | ti,buffer-size = <128>; |
505 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
506 | dmas = <&sdma 17>, |
507 | <&sdma 18>; | |
508 | dma-names = "tx", "rx"; | |
ffd5db24 PU |
509 | }; |
510 | ||
511 | mcbsp3: mcbsp@40126000 { | |
512 | compatible = "ti,omap4-mcbsp"; | |
513 | reg = <0x40126000 0xff>, /* MPU private access */ | |
514 | <0x49026000 0xff>; /* L3 Interconnect */ | |
515 | reg-names = "mpu", "dma"; | |
8fea7d5a | 516 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 517 | interrupt-names = "common"; |
ffd5db24 PU |
518 | ti,buffer-size = <128>; |
519 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
520 | dmas = <&sdma 19>, |
521 | <&sdma 20>; | |
522 | dma-names = "tx", "rx"; | |
ffd5db24 | 523 | }; |
df692a92 JH |
524 | |
525 | timer1: timer@4ae18000 { | |
002e1ec5 | 526 | compatible = "ti,omap5430-timer"; |
df692a92 | 527 | reg = <0x4ae18000 0x80>; |
8fea7d5a | 528 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
529 | ti,hwmods = "timer1"; |
530 | ti,timer-alwon; | |
531 | }; | |
532 | ||
533 | timer2: timer@48032000 { | |
002e1ec5 | 534 | compatible = "ti,omap5430-timer"; |
df692a92 | 535 | reg = <0x48032000 0x80>; |
8fea7d5a | 536 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
537 | ti,hwmods = "timer2"; |
538 | }; | |
539 | ||
540 | timer3: timer@48034000 { | |
002e1ec5 | 541 | compatible = "ti,omap5430-timer"; |
df692a92 | 542 | reg = <0x48034000 0x80>; |
8fea7d5a | 543 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
544 | ti,hwmods = "timer3"; |
545 | }; | |
546 | ||
547 | timer4: timer@48036000 { | |
002e1ec5 | 548 | compatible = "ti,omap5430-timer"; |
df692a92 | 549 | reg = <0x48036000 0x80>; |
8fea7d5a | 550 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
551 | ti,hwmods = "timer4"; |
552 | }; | |
553 | ||
554 | timer5: timer@40138000 { | |
002e1ec5 | 555 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
556 | reg = <0x40138000 0x80>, |
557 | <0x49038000 0x80>; | |
8fea7d5a | 558 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
559 | ti,hwmods = "timer5"; |
560 | ti,timer-dsp; | |
8341613a | 561 | ti,timer-pwm; |
df692a92 JH |
562 | }; |
563 | ||
564 | timer6: timer@4013a000 { | |
002e1ec5 | 565 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
566 | reg = <0x4013a000 0x80>, |
567 | <0x4903a000 0x80>; | |
8fea7d5a | 568 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
569 | ti,hwmods = "timer6"; |
570 | ti,timer-dsp; | |
571 | ti,timer-pwm; | |
572 | }; | |
573 | ||
574 | timer7: timer@4013c000 { | |
002e1ec5 | 575 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
576 | reg = <0x4013c000 0x80>, |
577 | <0x4903c000 0x80>; | |
8fea7d5a | 578 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
579 | ti,hwmods = "timer7"; |
580 | ti,timer-dsp; | |
581 | }; | |
582 | ||
583 | timer8: timer@4013e000 { | |
002e1ec5 | 584 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
585 | reg = <0x4013e000 0x80>, |
586 | <0x4903e000 0x80>; | |
8fea7d5a | 587 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
588 | ti,hwmods = "timer8"; |
589 | ti,timer-dsp; | |
590 | ti,timer-pwm; | |
591 | }; | |
592 | ||
593 | timer9: timer@4803e000 { | |
002e1ec5 | 594 | compatible = "ti,omap5430-timer"; |
df692a92 | 595 | reg = <0x4803e000 0x80>; |
8fea7d5a | 596 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 | 597 | ti,hwmods = "timer9"; |
8341613a | 598 | ti,timer-pwm; |
df692a92 JH |
599 | }; |
600 | ||
601 | timer10: timer@48086000 { | |
002e1ec5 | 602 | compatible = "ti,omap5430-timer"; |
df692a92 | 603 | reg = <0x48086000 0x80>; |
8fea7d5a | 604 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 | 605 | ti,hwmods = "timer10"; |
8341613a | 606 | ti,timer-pwm; |
df692a92 JH |
607 | }; |
608 | ||
609 | timer11: timer@48088000 { | |
002e1ec5 | 610 | compatible = "ti,omap5430-timer"; |
df692a92 | 611 | reg = <0x48088000 0x80>; |
8fea7d5a | 612 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
613 | ti,hwmods = "timer11"; |
614 | ti,timer-pwm; | |
615 | }; | |
e6900ddf | 616 | |
55452197 LV |
617 | wdt2: wdt@4ae14000 { |
618 | compatible = "ti,omap5-wdt", "ti,omap3-wdt"; | |
619 | reg = <0x4ae14000 0x80>; | |
8fea7d5a | 620 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
55452197 LV |
621 | ti,hwmods = "wd_timer2"; |
622 | }; | |
623 | ||
8906d654 | 624 | emif1: emif@4c000000 { |
e6900ddf LV |
625 | compatible = "ti,emif-4d5"; |
626 | ti,hwmods = "emif1"; | |
f12ecbe2 | 627 | ti,no-idle-on-init; |
e6900ddf LV |
628 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
629 | reg = <0x4c000000 0x400>; | |
8fea7d5a | 630 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
e6900ddf LV |
631 | hw-caps-read-idle-ctrl; |
632 | hw-caps-ll-interface; | |
633 | hw-caps-temp-alert; | |
634 | }; | |
635 | ||
8906d654 | 636 | emif2: emif@4d000000 { |
e6900ddf LV |
637 | compatible = "ti,emif-4d5"; |
638 | ti,hwmods = "emif2"; | |
f12ecbe2 | 639 | ti,no-idle-on-init; |
e6900ddf LV |
640 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
641 | reg = <0x4d000000 0x400>; | |
8fea7d5a | 642 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
e6900ddf LV |
643 | hw-caps-read-idle-ctrl; |
644 | hw-caps-ll-interface; | |
645 | hw-caps-temp-alert; | |
646 | }; | |
fedc428e | 647 | |
b297c292 RQ |
648 | omap_control_usb2phy: control-phy@4a002300 { |
649 | compatible = "ti,control-phy-usb2"; | |
650 | reg = <0x4a002300 0x4>; | |
651 | reg-names = "power"; | |
652 | }; | |
653 | ||
654 | omap_control_usb3phy: control-phy@4a002370 { | |
655 | compatible = "ti,control-phy-pipe3"; | |
656 | reg = <0x4a002370 0x4>; | |
657 | reg-names = "power"; | |
fedc428e | 658 | }; |
e9831967 | 659 | |
e3a412c9 | 660 | usb3: omap_dwc3@4a020000 { |
72f6f957 KVA |
661 | compatible = "ti,dwc3"; |
662 | ti,hwmods = "usb_otg_ss"; | |
6f61ee23 | 663 | reg = <0x4a020000 0x10000>; |
8fea7d5a | 664 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
72f6f957 KVA |
665 | #address-cells = <1>; |
666 | #size-cells = <1>; | |
667 | utmi-mode = <2>; | |
668 | ranges; | |
669 | dwc3@4a030000 { | |
22a5aa17 | 670 | compatible = "snps,dwc3"; |
6f61ee23 | 671 | reg = <0x4a030000 0x10000>; |
8fea7d5a | 672 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
72f6f957 | 673 | usb-phy = <&usb2_phy>, <&usb3_phy>; |
c47ee6ee | 674 | dr_mode = "peripheral"; |
72f6f957 KVA |
675 | tx-fifo-resize; |
676 | }; | |
677 | }; | |
678 | ||
b6731f78 | 679 | ocp2scp@4a080000 { |
e9831967 KVA |
680 | compatible = "ti,omap-ocp2scp"; |
681 | #address-cells = <1>; | |
682 | #size-cells = <1>; | |
b6731f78 | 683 | reg = <0x4a080000 0x20>; |
e9831967 KVA |
684 | ranges; |
685 | ti,hwmods = "ocp2scp1"; | |
ae6a32d2 KVA |
686 | usb2_phy: usb2phy@4a084000 { |
687 | compatible = "ti,omap-usb2"; | |
688 | reg = <0x4a084000 0x7c>; | |
b297c292 | 689 | ctrl-module = <&omap_control_usb2phy>; |
ae6a32d2 KVA |
690 | }; |
691 | ||
692 | usb3_phy: usb3phy@4a084400 { | |
693 | compatible = "ti,omap-usb3"; | |
694 | reg = <0x4a084400 0x80>, | |
695 | <0x4a084800 0x64>, | |
696 | <0x4a084c00 0x40>; | |
697 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
b297c292 | 698 | ctrl-module = <&omap_control_usb3phy>; |
ae6a32d2 | 699 | }; |
e9831967 | 700 | }; |
ed7f8e8a RQ |
701 | |
702 | usbhstll: usbhstll@4a062000 { | |
703 | compatible = "ti,usbhs-tll"; | |
704 | reg = <0x4a062000 0x1000>; | |
705 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
706 | ti,hwmods = "usb_tll_hs"; | |
707 | }; | |
708 | ||
709 | usbhshost: usbhshost@4a064000 { | |
710 | compatible = "ti,usbhs-host"; | |
711 | reg = <0x4a064000 0x800>; | |
712 | ti,hwmods = "usb_host_hs"; | |
713 | #address-cells = <1>; | |
714 | #size-cells = <1>; | |
715 | ranges; | |
716 | ||
717 | usbhsohci: ohci@4a064800 { | |
718 | compatible = "ti,ohci-omap3", "usb-ohci"; | |
719 | reg = <0x4a064800 0x400>; | |
720 | interrupt-parent = <&gic>; | |
721 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
722 | }; | |
723 | ||
724 | usbhsehci: ehci@4a064c00 { | |
725 | compatible = "ti,ehci-omap", "usb-ehci"; | |
726 | reg = <0x4a064c00 0x400>; | |
727 | interrupt-parent = <&gic>; | |
728 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
729 | }; | |
730 | }; | |
cbad26db EV |
731 | |
732 | bandgap@4a0021e0 { | |
733 | reg = <0x4a0021e0 0xc | |
734 | 0x4a00232c 0xc | |
735 | 0x4a002380 0x2c | |
736 | 0x4a0023C0 0x3c>; | |
737 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; | |
738 | compatible = "ti,omap5430-bandgap"; | |
739 | }; | |
6b5de091 S |
740 | }; |
741 | }; |