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1 | /* |
2 | * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC | |
3 | * | |
4 | * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> | |
5 | * | |
6 | * Licensed under GPLv2 or later | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
11 | ||
12 | / { | |
13 | compatible = "oxsemi,ox820"; | |
14 | ||
15 | cpus { | |
16 | #address-cells = <1>; | |
17 | #size-cells = <0>; | |
18 | enable-method = "oxsemi,ox820-smp"; | |
19 | ||
20 | cpu@0 { | |
21 | device_type = "cpu"; | |
22 | compatible = "arm,arm11mpcore"; | |
23 | clocks = <&armclk>; | |
24 | reg = <0>; | |
25 | }; | |
26 | ||
27 | cpu@1 { | |
28 | device_type = "cpu"; | |
29 | compatible = "arm,arm11mpcore"; | |
30 | clocks = <&armclk>; | |
31 | reg = <1>; | |
32 | }; | |
33 | }; | |
34 | ||
35 | memory { | |
36 | /* Max 512MB @ 0x60000000 */ | |
37 | reg = <0x60000000 0x20000000>; | |
38 | }; | |
39 | ||
40 | clocks { | |
41 | osc: oscillator { | |
42 | compatible = "fixed-clock"; | |
43 | #clock-cells = <0>; | |
44 | clock-frequency = <25000000>; | |
45 | }; | |
46 | ||
47 | gmacclk: gmacclk { | |
48 | compatible = "fixed-clock"; | |
49 | #clock-cells = <0>; | |
50 | clock-frequency = <125000000>; | |
51 | }; | |
52 | ||
53 | sysclk: sysclk { | |
54 | compatible = "fixed-factor-clock"; | |
55 | #clock-cells = <0>; | |
56 | clock-div = <4>; | |
57 | clock-mult = <1>; | |
58 | clocks = <&osc>; | |
59 | }; | |
60 | ||
61 | plla: plla { | |
62 | compatible = "fixed-clock"; | |
63 | #clock-cells = <0>; | |
64 | clock-frequency = <850000000>; | |
65 | }; | |
66 | ||
67 | armclk: armclk { | |
68 | compatible = "fixed-factor-clock"; | |
69 | #clock-cells = <0>; | |
70 | clock-div = <2>; | |
71 | clock-mult = <1>; | |
72 | clocks = <&plla>; | |
73 | }; | |
74 | }; | |
75 | ||
76 | soc { | |
77 | #address-cells = <1>; | |
78 | #size-cells = <1>; | |
79 | compatible = "simple-bus"; | |
80 | ranges; | |
81 | interrupt-parent = <&gic>; | |
82 | ||
83 | nandc: nand-controller@41000000 { | |
84 | compatible = "oxsemi,ox820-nand"; | |
85 | reg = <0x41000000 0x100000>; | |
86 | clocks = <&stdclk 11>; | |
87 | resets = <&reset 15>; | |
88 | #address-cells = <1>; | |
89 | #size-cells = <0>; | |
90 | status = "disabled"; | |
91 | }; | |
92 | ||
93 | etha: ethernet@40400000 { | |
94 | compatible = "oxsemi,ox820-dwmac", "snps,dwmac"; | |
95 | reg = <0x40400000 0x2000>; | |
96 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
97 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
98 | interrupt-names = "macirq", "eth_wake_irq"; | |
99 | mac-address = [000000000000]; /* Filled in by U-Boot */ | |
100 | phy-mode = "rgmii"; | |
101 | ||
102 | clocks = <&stdclk 9>, <&gmacclk>; | |
103 | clock-names = "gmac", "stmmaceth"; | |
104 | resets = <&reset 6>; | |
105 | ||
106 | /* Regmap for sys registers */ | |
107 | oxsemi,sys-ctrl = <&sys>; | |
108 | ||
109 | status = "disabled"; | |
110 | }; | |
111 | ||
112 | apb-bridge@44000000 { | |
113 | #address-cells = <1>; | |
114 | #size-cells = <1>; | |
115 | compatible = "simple-bus"; | |
116 | ranges = <0 0x44000000 0x1000000>; | |
117 | ||
118 | pinctrl: pinctrl { | |
119 | compatible = "oxsemi,ox820-pinctrl"; | |
120 | ||
121 | /* Regmap for sys registers */ | |
122 | oxsemi,sys-ctrl = <&sys>; | |
123 | ||
124 | pinctrl_uart0: uart0 { | |
125 | uart0 { | |
126 | pins = "gpio30", "gpio31"; | |
127 | function = "fct5"; | |
128 | }; | |
129 | }; | |
130 | ||
131 | pinctrl_uart0_modem: uart0_modem { | |
132 | uart0_modem_a { | |
133 | pins = "gpio24", "gpio24", "gpio26", "gpio27"; | |
134 | function = "fct4"; | |
135 | }; | |
136 | uart0_modem_b { | |
137 | pins = "gpio28", "gpio29"; | |
138 | function = "fct5"; | |
139 | }; | |
140 | }; | |
141 | ||
142 | pinctrl_uart1: uart1 { | |
143 | uart1 { | |
144 | pins = "gpio7", "gpio8"; | |
145 | function = "fct4"; | |
146 | }; | |
147 | }; | |
148 | ||
149 | pinctrl_uart1_modem: uart1_modem { | |
150 | uart1_modem { | |
151 | pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43"; | |
152 | function = "fct4"; | |
153 | }; | |
154 | }; | |
155 | ||
156 | pinctrl_etha_mdio: etha_mdio { | |
157 | etha_mdio { | |
158 | pins = "gpio3", "gpio4"; | |
159 | function = "fct1"; | |
160 | }; | |
161 | }; | |
162 | ||
163 | pinctrl_nand: nand { | |
164 | nand { | |
165 | pins = "gpio12", "gpio13", "gpio14", "gpio15", | |
166 | "gpio16", "gpio17", "gpio18", "gpio19", | |
167 | "gpio20", "gpio21", "gpio22", "gpio23", | |
168 | "gpio24"; | |
169 | function = "fct1"; | |
170 | }; | |
171 | }; | |
172 | }; | |
173 | ||
174 | gpio0: gpio@000000 { | |
175 | compatible = "oxsemi,ox820-gpio"; | |
176 | reg = <0x000000 0x100000>; | |
177 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
178 | #gpio-cells = <2>; | |
179 | gpio-controller; | |
180 | interrupt-controller; | |
181 | #interrupt-cells = <2>; | |
182 | ngpios = <32>; | |
183 | oxsemi,gpio-bank = <0>; | |
184 | gpio-ranges = <&pinctrl 0 0 32>; | |
185 | }; | |
186 | ||
187 | gpio1: gpio@100000 { | |
188 | compatible = "oxsemi,ox820-gpio"; | |
189 | reg = <0x100000 0x100000>; | |
190 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
191 | #gpio-cells = <2>; | |
192 | gpio-controller; | |
193 | interrupt-controller; | |
194 | #interrupt-cells = <2>; | |
195 | ngpios = <18>; | |
196 | oxsemi,gpio-bank = <1>; | |
197 | gpio-ranges = <&pinctrl 0 32 18>; | |
198 | }; | |
199 | ||
200 | uart0: serial@200000 { | |
201 | compatible = "ns16550a"; | |
202 | reg = <0x200000 0x100000>; | |
203 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
204 | reg-shift = <0>; | |
205 | fifo-size = <16>; | |
206 | reg-io-width = <1>; | |
207 | current-speed = <115200>; | |
208 | no-loopback-test; | |
209 | status = "disabled"; | |
210 | clocks = <&sysclk>; | |
211 | resets = <&reset 17>; | |
212 | }; | |
213 | ||
214 | uart1: serial@300000 { | |
215 | compatible = "ns16550a"; | |
216 | reg = <0x200000 0x100000>; | |
217 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
218 | reg-shift = <0>; | |
219 | fifo-size = <16>; | |
220 | reg-io-width = <1>; | |
221 | current-speed = <115200>; | |
222 | no-loopback-test; | |
223 | status = "disabled"; | |
224 | clocks = <&sysclk>; | |
225 | resets = <&reset 18>; | |
226 | }; | |
227 | ||
228 | rps@400000 { | |
229 | #address-cells = <1>; | |
230 | #size-cells = <1>; | |
231 | compatible = "simple-bus"; | |
232 | ranges = <0 0x400000 0x100000>; | |
233 | ||
234 | intc: interrupt-controller@0 { | |
235 | compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq"; | |
236 | interrupt-controller; | |
237 | reg = <0 0x200>; | |
238 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
239 | #interrupt-cells = <1>; | |
240 | valid-mask = <0xFFFFFFFF>; | |
241 | clear-mask = <0>; | |
242 | }; | |
243 | ||
244 | timer0: timer@200 { | |
245 | compatible = "oxsemi,ox820-rps-timer"; | |
246 | reg = <0x200 0x40>; | |
247 | clocks = <&sysclk>; | |
248 | interrupt-parent = <&intc>; | |
249 | interrupts = <4>; | |
250 | }; | |
251 | }; | |
252 | ||
253 | sys: sys-ctrl@e00000 { | |
254 | compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"; | |
255 | reg = <0xe00000 0x200000>; | |
256 | ||
257 | reset: reset-controller { | |
258 | compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset"; | |
259 | #reset-cells = <1>; | |
260 | }; | |
261 | ||
262 | stdclk: stdclk { | |
263 | compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk"; | |
264 | #clock-cells = <1>; | |
265 | }; | |
266 | }; | |
267 | }; | |
268 | ||
269 | apb-bridge@47000000 { | |
270 | #address-cells = <1>; | |
271 | #size-cells = <1>; | |
272 | compatible = "simple-bus"; | |
273 | ranges = <0 0x47000000 0x1000000>; | |
274 | ||
275 | scu: scu@0 { | |
276 | compatible = "arm,arm11mp-scu"; | |
277 | reg = <0x0 0x100>; | |
278 | }; | |
279 | ||
280 | local-timer@600 { | |
281 | compatible = "arm,arm11mp-twd-timer"; | |
282 | reg = <0x600 0x20>; | |
283 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>; | |
284 | clocks = <&armclk>; | |
285 | }; | |
286 | ||
287 | gic: gic@1000 { | |
288 | compatible = "arm,arm11mp-gic"; | |
289 | interrupt-controller; | |
290 | #interrupt-cells = <3>; | |
291 | reg = <0x1000 0x1000>, | |
292 | <0x100 0x500>; | |
293 | }; | |
294 | }; | |
295 | }; | |
296 | }; |