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1 | /* |
2 | * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC | |
3 | * | |
4 | * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> | |
5 | * | |
6 | * Licensed under GPLv2 or later | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
0c5987d3 NA |
11 | #include <dt-bindings/clock/oxsemi,ox820.h> |
12 | #include <dt-bindings/reset/oxsemi,ox820.h> | |
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13 | |
14 | / { | |
15 | compatible = "oxsemi,ox820"; | |
16 | ||
17 | cpus { | |
18 | #address-cells = <1>; | |
19 | #size-cells = <0>; | |
20 | enable-method = "oxsemi,ox820-smp"; | |
21 | ||
22 | cpu@0 { | |
23 | device_type = "cpu"; | |
24 | compatible = "arm,arm11mpcore"; | |
25 | clocks = <&armclk>; | |
26 | reg = <0>; | |
27 | }; | |
28 | ||
29 | cpu@1 { | |
30 | device_type = "cpu"; | |
31 | compatible = "arm,arm11mpcore"; | |
32 | clocks = <&armclk>; | |
33 | reg = <1>; | |
34 | }; | |
35 | }; | |
36 | ||
37 | memory { | |
38 | /* Max 512MB @ 0x60000000 */ | |
39 | reg = <0x60000000 0x20000000>; | |
40 | }; | |
41 | ||
42 | clocks { | |
43 | osc: oscillator { | |
44 | compatible = "fixed-clock"; | |
45 | #clock-cells = <0>; | |
46 | clock-frequency = <25000000>; | |
47 | }; | |
48 | ||
49 | gmacclk: gmacclk { | |
50 | compatible = "fixed-clock"; | |
51 | #clock-cells = <0>; | |
52 | clock-frequency = <125000000>; | |
53 | }; | |
54 | ||
55 | sysclk: sysclk { | |
56 | compatible = "fixed-factor-clock"; | |
57 | #clock-cells = <0>; | |
58 | clock-div = <4>; | |
59 | clock-mult = <1>; | |
60 | clocks = <&osc>; | |
61 | }; | |
62 | ||
63 | plla: plla { | |
64 | compatible = "fixed-clock"; | |
65 | #clock-cells = <0>; | |
66 | clock-frequency = <850000000>; | |
67 | }; | |
68 | ||
69 | armclk: armclk { | |
70 | compatible = "fixed-factor-clock"; | |
71 | #clock-cells = <0>; | |
72 | clock-div = <2>; | |
73 | clock-mult = <1>; | |
74 | clocks = <&plla>; | |
75 | }; | |
76 | }; | |
77 | ||
78 | soc { | |
79 | #address-cells = <1>; | |
80 | #size-cells = <1>; | |
81 | compatible = "simple-bus"; | |
82 | ranges; | |
83 | interrupt-parent = <&gic>; | |
84 | ||
85 | nandc: nand-controller@41000000 { | |
86 | compatible = "oxsemi,ox820-nand"; | |
87 | reg = <0x41000000 0x100000>; | |
0c5987d3 NA |
88 | clocks = <&stdclk CLK_820_NAND>; |
89 | resets = <&reset RESET_NAND>; | |
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90 | #address-cells = <1>; |
91 | #size-cells = <0>; | |
92 | status = "disabled"; | |
93 | }; | |
94 | ||
95 | etha: ethernet@40400000 { | |
96 | compatible = "oxsemi,ox820-dwmac", "snps,dwmac"; | |
97 | reg = <0x40400000 0x2000>; | |
98 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
99 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
100 | interrupt-names = "macirq", "eth_wake_irq"; | |
101 | mac-address = [000000000000]; /* Filled in by U-Boot */ | |
102 | phy-mode = "rgmii"; | |
103 | ||
0c5987d3 | 104 | clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>; |
38d4a537 | 105 | clock-names = "gmac", "stmmaceth"; |
0c5987d3 | 106 | resets = <&reset RESET_MAC>; |
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107 | |
108 | /* Regmap for sys registers */ | |
109 | oxsemi,sys-ctrl = <&sys>; | |
110 | ||
111 | status = "disabled"; | |
112 | }; | |
113 | ||
114 | apb-bridge@44000000 { | |
115 | #address-cells = <1>; | |
116 | #size-cells = <1>; | |
117 | compatible = "simple-bus"; | |
118 | ranges = <0 0x44000000 0x1000000>; | |
119 | ||
120 | pinctrl: pinctrl { | |
121 | compatible = "oxsemi,ox820-pinctrl"; | |
122 | ||
123 | /* Regmap for sys registers */ | |
124 | oxsemi,sys-ctrl = <&sys>; | |
125 | ||
126 | pinctrl_uart0: uart0 { | |
127 | uart0 { | |
128 | pins = "gpio30", "gpio31"; | |
129 | function = "fct5"; | |
130 | }; | |
131 | }; | |
132 | ||
133 | pinctrl_uart0_modem: uart0_modem { | |
134 | uart0_modem_a { | |
135 | pins = "gpio24", "gpio24", "gpio26", "gpio27"; | |
136 | function = "fct4"; | |
137 | }; | |
138 | uart0_modem_b { | |
139 | pins = "gpio28", "gpio29"; | |
140 | function = "fct5"; | |
141 | }; | |
142 | }; | |
143 | ||
144 | pinctrl_uart1: uart1 { | |
145 | uart1 { | |
146 | pins = "gpio7", "gpio8"; | |
147 | function = "fct4"; | |
148 | }; | |
149 | }; | |
150 | ||
151 | pinctrl_uart1_modem: uart1_modem { | |
152 | uart1_modem { | |
153 | pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43"; | |
154 | function = "fct4"; | |
155 | }; | |
156 | }; | |
157 | ||
158 | pinctrl_etha_mdio: etha_mdio { | |
159 | etha_mdio { | |
160 | pins = "gpio3", "gpio4"; | |
161 | function = "fct1"; | |
162 | }; | |
163 | }; | |
164 | ||
165 | pinctrl_nand: nand { | |
166 | nand { | |
167 | pins = "gpio12", "gpio13", "gpio14", "gpio15", | |
168 | "gpio16", "gpio17", "gpio18", "gpio19", | |
169 | "gpio20", "gpio21", "gpio22", "gpio23", | |
170 | "gpio24"; | |
171 | function = "fct1"; | |
172 | }; | |
173 | }; | |
174 | }; | |
175 | ||
176 | gpio0: gpio@000000 { | |
177 | compatible = "oxsemi,ox820-gpio"; | |
178 | reg = <0x000000 0x100000>; | |
179 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
180 | #gpio-cells = <2>; | |
181 | gpio-controller; | |
182 | interrupt-controller; | |
183 | #interrupt-cells = <2>; | |
184 | ngpios = <32>; | |
185 | oxsemi,gpio-bank = <0>; | |
186 | gpio-ranges = <&pinctrl 0 0 32>; | |
187 | }; | |
188 | ||
189 | gpio1: gpio@100000 { | |
190 | compatible = "oxsemi,ox820-gpio"; | |
191 | reg = <0x100000 0x100000>; | |
192 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
193 | #gpio-cells = <2>; | |
194 | gpio-controller; | |
195 | interrupt-controller; | |
196 | #interrupt-cells = <2>; | |
197 | ngpios = <18>; | |
198 | oxsemi,gpio-bank = <1>; | |
199 | gpio-ranges = <&pinctrl 0 32 18>; | |
200 | }; | |
201 | ||
202 | uart0: serial@200000 { | |
203 | compatible = "ns16550a"; | |
204 | reg = <0x200000 0x100000>; | |
205 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
206 | reg-shift = <0>; | |
207 | fifo-size = <16>; | |
208 | reg-io-width = <1>; | |
209 | current-speed = <115200>; | |
210 | no-loopback-test; | |
211 | status = "disabled"; | |
212 | clocks = <&sysclk>; | |
0c5987d3 | 213 | resets = <&reset RESET_UART1>; |
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214 | }; |
215 | ||
216 | uart1: serial@300000 { | |
217 | compatible = "ns16550a"; | |
218 | reg = <0x200000 0x100000>; | |
219 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
220 | reg-shift = <0>; | |
221 | fifo-size = <16>; | |
222 | reg-io-width = <1>; | |
223 | current-speed = <115200>; | |
224 | no-loopback-test; | |
225 | status = "disabled"; | |
226 | clocks = <&sysclk>; | |
0c5987d3 | 227 | resets = <&reset RESET_UART2>; |
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228 | }; |
229 | ||
230 | rps@400000 { | |
231 | #address-cells = <1>; | |
232 | #size-cells = <1>; | |
233 | compatible = "simple-bus"; | |
234 | ranges = <0 0x400000 0x100000>; | |
235 | ||
236 | intc: interrupt-controller@0 { | |
237 | compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq"; | |
238 | interrupt-controller; | |
239 | reg = <0 0x200>; | |
240 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
241 | #interrupt-cells = <1>; | |
242 | valid-mask = <0xFFFFFFFF>; | |
243 | clear-mask = <0>; | |
244 | }; | |
245 | ||
246 | timer0: timer@200 { | |
247 | compatible = "oxsemi,ox820-rps-timer"; | |
248 | reg = <0x200 0x40>; | |
249 | clocks = <&sysclk>; | |
250 | interrupt-parent = <&intc>; | |
251 | interrupts = <4>; | |
252 | }; | |
253 | }; | |
254 | ||
255 | sys: sys-ctrl@e00000 { | |
256 | compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"; | |
257 | reg = <0xe00000 0x200000>; | |
258 | ||
259 | reset: reset-controller { | |
260 | compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset"; | |
261 | #reset-cells = <1>; | |
262 | }; | |
263 | ||
264 | stdclk: stdclk { | |
265 | compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk"; | |
266 | #clock-cells = <1>; | |
267 | }; | |
268 | }; | |
269 | }; | |
270 | ||
271 | apb-bridge@47000000 { | |
272 | #address-cells = <1>; | |
273 | #size-cells = <1>; | |
274 | compatible = "simple-bus"; | |
275 | ranges = <0 0x47000000 0x1000000>; | |
276 | ||
277 | scu: scu@0 { | |
278 | compatible = "arm,arm11mp-scu"; | |
279 | reg = <0x0 0x100>; | |
280 | }; | |
281 | ||
282 | local-timer@600 { | |
283 | compatible = "arm,arm11mp-twd-timer"; | |
284 | reg = <0x600 0x20>; | |
285 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>; | |
286 | clocks = <&armclk>; | |
287 | }; | |
288 | ||
289 | gic: gic@1000 { | |
290 | compatible = "arm,arm11mp-gic"; | |
291 | interrupt-controller; | |
292 | #interrupt-cells = <3>; | |
293 | reg = <0x1000 0x1000>, | |
294 | <0x100 0x500>; | |
295 | }; | |
296 | }; | |
297 | }; | |
298 | }; |