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fee75656 JI |
1 | /* |
2 | * Copyright (C) 2011 Picochip, Jamie Iles | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
fee75656 JI |
13 | / { |
14 | model = "Picochip picoXcell PC3X3"; | |
15 | compatible = "picochip,pc3x3"; | |
16 | #address-cells = <1>; | |
17 | #size-cells = <1>; | |
18 | ||
19 | cpus { | |
7021f0b8 | 20 | #address-cells = <0>; |
fee75656 JI |
21 | #size-cells = <0>; |
22 | ||
7021f0b8 LP |
23 | cpu { |
24 | compatible = "arm,arm1176jz-s"; | |
25 | device_type = "cpu"; | |
fee75656 | 26 | cpu-clock = <&arm_clk>, "cpu"; |
fee75656 JI |
27 | d-cache-line-size = <32>; |
28 | d-cache-size = <32768>; | |
29 | i-cache-line-size = <32>; | |
30 | i-cache-size = <32768>; | |
31 | }; | |
32 | }; | |
33 | ||
34 | clocks { | |
35 | #address-cells = <1>; | |
36 | #size-cells = <1>; | |
37 | ranges; | |
38 | ||
39 | clkgate: clkgate@800a0048 { | |
40 | #address-cells = <1>; | |
41 | #size-cells = <0>; | |
42 | reg = <0x800a0048 4>; | |
43 | compatible = "picochip,pc3x3-clk-gate"; | |
44 | ||
45 | tzprot_clk: clock@0 { | |
46 | compatible = "picochip,pc3x3-gated-clk"; | |
47 | clock-outputs = "bus"; | |
48 | picochip,clk-disable-bit = <0>; | |
49 | clock-frequency = <200000000>; | |
50 | ref-clock = <&ref_clk>, "ref"; | |
51 | }; | |
52 | ||
53 | spi_clk: clock@1 { | |
54 | compatible = "picochip,pc3x3-gated-clk"; | |
55 | clock-outputs = "bus"; | |
56 | picochip,clk-disable-bit = <1>; | |
57 | clock-frequency = <200000000>; | |
58 | ref-clock = <&ref_clk>, "ref"; | |
59 | }; | |
60 | ||
61 | dmac0_clk: clock@2 { | |
62 | compatible = "picochip,pc3x3-gated-clk"; | |
63 | clock-outputs = "bus"; | |
64 | picochip,clk-disable-bit = <2>; | |
65 | clock-frequency = <200000000>; | |
66 | ref-clock = <&ref_clk>, "ref"; | |
67 | }; | |
68 | ||
69 | dmac1_clk: clock@3 { | |
70 | compatible = "picochip,pc3x3-gated-clk"; | |
71 | clock-outputs = "bus"; | |
72 | picochip,clk-disable-bit = <3>; | |
73 | clock-frequency = <200000000>; | |
74 | ref-clock = <&ref_clk>, "ref"; | |
75 | }; | |
76 | ||
77 | ebi_clk: clock@4 { | |
78 | compatible = "picochip,pc3x3-gated-clk"; | |
79 | clock-outputs = "bus"; | |
80 | picochip,clk-disable-bit = <4>; | |
81 | clock-frequency = <200000000>; | |
82 | ref-clock = <&ref_clk>, "ref"; | |
83 | }; | |
84 | ||
85 | ipsec_clk: clock@5 { | |
86 | compatible = "picochip,pc3x3-gated-clk"; | |
87 | clock-outputs = "bus"; | |
88 | picochip,clk-disable-bit = <5>; | |
89 | clock-frequency = <200000000>; | |
90 | ref-clock = <&ref_clk>, "ref"; | |
91 | }; | |
92 | ||
93 | l2_clk: clock@6 { | |
94 | compatible = "picochip,pc3x3-gated-clk"; | |
95 | clock-outputs = "bus"; | |
96 | picochip,clk-disable-bit = <6>; | |
97 | clock-frequency = <200000000>; | |
98 | ref-clock = <&ref_clk>, "ref"; | |
99 | }; | |
100 | ||
101 | trng_clk: clock@7 { | |
102 | compatible = "picochip,pc3x3-gated-clk"; | |
103 | clock-outputs = "bus"; | |
104 | picochip,clk-disable-bit = <7>; | |
105 | clock-frequency = <200000000>; | |
106 | ref-clock = <&ref_clk>, "ref"; | |
107 | }; | |
108 | ||
109 | fuse_clk: clock@8 { | |
110 | compatible = "picochip,pc3x3-gated-clk"; | |
111 | clock-outputs = "bus"; | |
112 | picochip,clk-disable-bit = <8>; | |
113 | clock-frequency = <200000000>; | |
114 | ref-clock = <&ref_clk>, "ref"; | |
115 | }; | |
116 | ||
117 | otp_clk: clock@9 { | |
118 | compatible = "picochip,pc3x3-gated-clk"; | |
119 | clock-outputs = "bus"; | |
120 | picochip,clk-disable-bit = <9>; | |
121 | clock-frequency = <200000000>; | |
122 | ref-clock = <&ref_clk>, "ref"; | |
123 | }; | |
124 | }; | |
125 | ||
126 | arm_clk: clock@11 { | |
127 | compatible = "picochip,pc3x3-pll"; | |
128 | reg = <0x800a0050 0x8>; | |
129 | picochip,min-freq = <140000000>; | |
130 | picochip,max-freq = <700000000>; | |
131 | ref-clock = <&ref_clk>, "ref"; | |
132 | clock-outputs = "cpu"; | |
133 | }; | |
134 | ||
135 | pclk: clock@12 { | |
136 | compatible = "fixed-clock"; | |
137 | clock-outputs = "bus", "pclk"; | |
138 | clock-frequency = <200000000>; | |
139 | ref-clock = <&ref_clk>, "ref"; | |
140 | }; | |
141 | }; | |
142 | ||
143 | paxi { | |
144 | compatible = "simple-bus"; | |
145 | #address-cells = <1>; | |
146 | #size-cells = <1>; | |
147 | ranges = <0 0x80000000 0x400000>; | |
148 | ||
149 | emac: gem@30000 { | |
150 | compatible = "cadence,gem"; | |
151 | reg = <0x30000 0x10000>; | |
152 | interrupt-parent = <&vic0>; | |
153 | interrupts = <31>; | |
154 | }; | |
155 | ||
156 | dmac1: dmac@40000 { | |
157 | compatible = "snps,dw-dmac"; | |
158 | reg = <0x40000 0x10000>; | |
159 | interrupt-parent = <&vic0>; | |
160 | interrupts = <25>; | |
161 | }; | |
162 | ||
163 | dmac2: dmac@50000 { | |
164 | compatible = "snps,dw-dmac"; | |
165 | reg = <0x50000 0x10000>; | |
166 | interrupt-parent = <&vic0>; | |
167 | interrupts = <26>; | |
168 | }; | |
169 | ||
170 | vic0: interrupt-controller@60000 { | |
171 | compatible = "arm,pl192-vic"; | |
172 | interrupt-controller; | |
173 | reg = <0x60000 0x1000>; | |
174 | #interrupt-cells = <1>; | |
175 | }; | |
176 | ||
177 | vic1: interrupt-controller@64000 { | |
178 | compatible = "arm,pl192-vic"; | |
179 | interrupt-controller; | |
180 | reg = <0x64000 0x1000>; | |
181 | #interrupt-cells = <1>; | |
182 | }; | |
183 | ||
184 | fuse: picoxcell-fuse@80000 { | |
185 | compatible = "picoxcell,fuse-pc3x3"; | |
186 | reg = <0x80000 0x10000>; | |
187 | }; | |
188 | ||
189 | ssi: picoxcell-spi@90000 { | |
190 | compatible = "picoxcell,spi"; | |
191 | reg = <0x90000 0x10000>; | |
192 | interrupt-parent = <&vic0>; | |
193 | interrupts = <10>; | |
194 | }; | |
195 | ||
196 | ipsec: spacc@100000 { | |
197 | compatible = "picochip,spacc-ipsec"; | |
198 | reg = <0x100000 0x10000>; | |
199 | interrupt-parent = <&vic0>; | |
200 | interrupts = <24>; | |
201 | ref-clock = <&ipsec_clk>, "ref"; | |
202 | }; | |
203 | ||
204 | srtp: spacc@140000 { | |
205 | compatible = "picochip,spacc-srtp"; | |
206 | reg = <0x140000 0x10000>; | |
207 | interrupt-parent = <&vic0>; | |
208 | interrupts = <23>; | |
209 | }; | |
210 | ||
211 | l2_engine: spacc@180000 { | |
212 | compatible = "picochip,spacc-l2"; | |
213 | reg = <0x180000 0x10000>; | |
214 | interrupt-parent = <&vic0>; | |
215 | interrupts = <22>; | |
216 | ref-clock = <&l2_clk>, "ref"; | |
217 | }; | |
218 | ||
219 | apb { | |
220 | compatible = "simple-bus"; | |
221 | #address-cells = <1>; | |
222 | #size-cells = <1>; | |
223 | ranges = <0 0x200000 0x80000>; | |
224 | ||
8dccafaa | 225 | rtc0: rtc@0 { |
fee75656 JI |
226 | compatible = "picochip,pc3x2-rtc"; |
227 | clock-freq = <200000000>; | |
228 | reg = <0x00000 0xf>; | |
229 | interrupt-parent = <&vic0>; | |
230 | interrupts = <8>; | |
231 | }; | |
232 | ||
233 | timer0: timer@10000 { | |
234 | compatible = "picochip,pc3x2-timer"; | |
235 | interrupt-parent = <&vic0>; | |
236 | interrupts = <4>; | |
237 | clock-freq = <200000000>; | |
238 | reg = <0x10000 0x14>; | |
239 | }; | |
240 | ||
241 | timer1: timer@10014 { | |
242 | compatible = "picochip,pc3x2-timer"; | |
243 | interrupt-parent = <&vic0>; | |
244 | interrupts = <5>; | |
245 | clock-freq = <200000000>; | |
246 | reg = <0x10014 0x14>; | |
247 | }; | |
248 | ||
249 | gpio: gpio@20000 { | |
250 | compatible = "snps,dw-apb-gpio"; | |
251 | reg = <0x20000 0x1000>; | |
252 | #address-cells = <1>; | |
253 | #size-cells = <0>; | |
254 | reg-io-width = <4>; | |
255 | ||
256 | banka: gpio-controller@0 { | |
257 | compatible = "snps,dw-apb-gpio-bank"; | |
258 | gpio-controller; | |
259 | #gpio-cells = <2>; | |
260 | gpio-generic,nr-gpio = <8>; | |
261 | ||
262 | regoffset-dat = <0x50>; | |
263 | regoffset-set = <0x00>; | |
264 | regoffset-dirout = <0x04>; | |
265 | }; | |
266 | ||
267 | bankb: gpio-controller@1 { | |
268 | compatible = "snps,dw-apb-gpio-bank"; | |
269 | gpio-controller; | |
270 | #gpio-cells = <2>; | |
271 | gpio-generic,nr-gpio = <16>; | |
272 | ||
273 | regoffset-dat = <0x54>; | |
274 | regoffset-set = <0x0c>; | |
275 | regoffset-dirout = <0x10>; | |
276 | }; | |
277 | ||
278 | bankd: gpio-controller@2 { | |
279 | compatible = "snps,dw-apb-gpio-bank"; | |
280 | gpio-controller; | |
281 | #gpio-cells = <2>; | |
282 | gpio-generic,nr-gpio = <30>; | |
283 | ||
284 | regoffset-dat = <0x5c>; | |
285 | regoffset-set = <0x24>; | |
286 | regoffset-dirout = <0x28>; | |
287 | }; | |
288 | }; | |
289 | ||
290 | uart0: uart@30000 { | |
291 | compatible = "snps,dw-apb-uart"; | |
292 | reg = <0x30000 0x1000>; | |
293 | interrupt-parent = <&vic1>; | |
294 | interrupts = <10>; | |
295 | clock-frequency = <3686400>; | |
296 | reg-shift = <2>; | |
297 | reg-io-width = <4>; | |
298 | }; | |
299 | ||
300 | uart1: uart@40000 { | |
301 | compatible = "snps,dw-apb-uart"; | |
302 | reg = <0x40000 0x1000>; | |
303 | interrupt-parent = <&vic1>; | |
304 | interrupts = <9>; | |
305 | clock-frequency = <3686400>; | |
306 | reg-shift = <2>; | |
307 | reg-io-width = <4>; | |
308 | }; | |
309 | ||
310 | wdog: watchdog@50000 { | |
311 | compatible = "snps,dw-apb-wdg"; | |
312 | reg = <0x50000 0x10000>; | |
313 | interrupt-parent = <&vic0>; | |
314 | interrupts = <11>; | |
315 | bus-clock = <&pclk>, "bus"; | |
316 | }; | |
317 | ||
318 | timer2: timer@60000 { | |
319 | compatible = "picochip,pc3x2-timer"; | |
320 | interrupt-parent = <&vic0>; | |
321 | interrupts = <6>; | |
322 | clock-freq = <200000000>; | |
323 | reg = <0x60000 0x14>; | |
324 | }; | |
325 | ||
326 | timer3: timer@60014 { | |
327 | compatible = "picochip,pc3x2-timer"; | |
328 | interrupt-parent = <&vic0>; | |
329 | interrupts = <7>; | |
330 | clock-freq = <200000000>; | |
331 | reg = <0x60014 0x14>; | |
332 | }; | |
333 | }; | |
334 | }; | |
335 | ||
336 | rwid-axi { | |
337 | #address-cells = <1>; | |
338 | #size-cells = <1>; | |
339 | compatible = "simple-bus"; | |
340 | ranges; | |
341 | ||
342 | ebi@50000000 { | |
343 | compatible = "simple-bus"; | |
344 | #address-cells = <2>; | |
345 | #size-cells = <1>; | |
346 | ranges = <0 0 0x40000000 0x08000000 | |
347 | 1 0 0x48000000 0x08000000 | |
348 | 2 0 0x50000000 0x08000000 | |
349 | 3 0 0x58000000 0x08000000>; | |
350 | }; | |
351 | ||
352 | axi2pico@c0000000 { | |
353 | compatible = "picochip,axi2pico-pc3x3"; | |
354 | reg = <0xc0000000 0x10000>; | |
355 | interrupt-parent = <&vic0>; | |
356 | interrupts = <13 14 15 16 17 18 19 20 21>; | |
357 | }; | |
358 | ||
359 | otp@ffff8000 { | |
360 | compatible = "picochip,otp-pc3x3"; | |
361 | reg = <0xffff8000 0x8000>; | |
362 | }; | |
363 | }; | |
364 | }; |