]>
Commit | Line | Data |
---|---|---|
434e1c57 BS |
1 | /* |
2 | * DTS file for CSR SiRFprimaII SoC | |
3 | * | |
4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
02c981c0 | 10 | / { |
434e1c57 | 11 | compatible = "sirf,prima2"; |
02c981c0 BD |
12 | #address-cells = <1>; |
13 | #size-cells = <1>; | |
14 | interrupt-parent = <&intc>; | |
15 | ||
02c981c0 BD |
16 | cpus { |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
20 | cpu@0 { | |
cc73f875 LP |
21 | compatible = "arm,cortex-a9"; |
22 | device_type = "cpu"; | |
02c981c0 BD |
23 | reg = <0x0>; |
24 | d-cache-line-size = <32>; | |
25 | i-cache-line-size = <32>; | |
26 | d-cache-size = <32768>; | |
27 | i-cache-size = <32768>; | |
28 | /* from bootloader */ | |
29 | timebase-frequency = <0>; | |
30 | bus-frequency = <0>; | |
31 | clock-frequency = <0>; | |
32 | }; | |
33 | }; | |
34 | ||
35 | axi { | |
36 | compatible = "simple-bus"; | |
37 | #address-cells = <1>; | |
38 | #size-cells = <1>; | |
39 | ranges = <0x40000000 0x40000000 0x80000000>; | |
40 | ||
41 | l2-cache-controller@80040000 { | |
917d8535 | 42 | compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; |
02c981c0 BD |
43 | reg = <0x80040000 0x1000>; |
44 | interrupts = <59>; | |
917d8535 BS |
45 | arm,tag-latency = <1 1 1>; |
46 | arm,data-latency = <1 1 1>; | |
47 | arm,filter-ranges = <0 0x40000000>; | |
02c981c0 BD |
48 | }; |
49 | ||
50 | intc: interrupt-controller@80020000 { | |
51 | #interrupt-cells = <1>; | |
52 | interrupt-controller; | |
53 | compatible = "sirf,prima2-intc"; | |
54 | reg = <0x80020000 0x1000>; | |
55 | }; | |
56 | ||
57 | sys-iobg { | |
58 | compatible = "simple-bus"; | |
59 | #address-cells = <1>; | |
60 | #size-cells = <1>; | |
61 | ranges = <0x88000000 0x88000000 0x40000>; | |
62 | ||
eb8b8f2e | 63 | clks: clock-controller@88000000 { |
02c981c0 BD |
64 | compatible = "sirf,prima2-clkc"; |
65 | reg = <0x88000000 0x1000>; | |
66 | interrupts = <3>; | |
eb8b8f2e | 67 | #clock-cells = <1>; |
02c981c0 BD |
68 | }; |
69 | ||
70 | reset-controller@88010000 { | |
71 | compatible = "sirf,prima2-rstc"; | |
72 | reg = <0x88010000 0x1000>; | |
73 | }; | |
073adf4f BS |
74 | |
75 | rsc-controller@88020000 { | |
76 | compatible = "sirf,prima2-rsc"; | |
77 | reg = <0x88020000 0x1000>; | |
78 | }; | |
02c981c0 BD |
79 | }; |
80 | ||
81 | mem-iobg { | |
82 | compatible = "simple-bus"; | |
83 | #address-cells = <1>; | |
84 | #size-cells = <1>; | |
85 | ranges = <0x90000000 0x90000000 0x10000>; | |
86 | ||
87 | memory-controller@90000000 { | |
88 | compatible = "sirf,prima2-memc"; | |
5fadea22 | 89 | reg = <0x90000000 0x2000>; |
02c981c0 | 90 | interrupts = <27>; |
eb8b8f2e | 91 | clocks = <&clks 5>; |
02c981c0 | 92 | }; |
5fadea22 YH |
93 | |
94 | memc-monitor { | |
95 | compatible = "sirf,prima2-memcmon"; | |
96 | reg = <0x90002000 0x200>; | |
97 | interrupts = <4>; | |
98 | clocks = <&clks 32>; | |
99 | }; | |
02c981c0 BD |
100 | }; |
101 | ||
102 | disp-iobg { | |
103 | compatible = "simple-bus"; | |
104 | #address-cells = <1>; | |
105 | #size-cells = <1>; | |
106 | ranges = <0x90010000 0x90010000 0x30000>; | |
107 | ||
108 | display@90010000 { | |
109 | compatible = "sirf,prima2-lcd"; | |
110 | reg = <0x90010000 0x20000>; | |
111 | interrupts = <30>; | |
112 | }; | |
113 | ||
114 | vpp@90020000 { | |
115 | compatible = "sirf,prima2-vpp"; | |
116 | reg = <0x90020000 0x10000>; | |
117 | interrupts = <31>; | |
eb8b8f2e | 118 | clocks = <&clks 35>; |
02c981c0 BD |
119 | }; |
120 | }; | |
121 | ||
122 | graphics-iobg { | |
123 | compatible = "simple-bus"; | |
124 | #address-cells = <1>; | |
125 | #size-cells = <1>; | |
126 | ranges = <0x98000000 0x98000000 0x8000000>; | |
127 | ||
128 | graphics@98000000 { | |
129 | compatible = "powervr,sgx531"; | |
130 | reg = <0x98000000 0x8000000>; | |
131 | interrupts = <6>; | |
eb8b8f2e | 132 | clocks = <&clks 32>; |
02c981c0 BD |
133 | }; |
134 | }; | |
135 | ||
136 | multimedia-iobg { | |
137 | compatible = "simple-bus"; | |
138 | #address-cells = <1>; | |
139 | #size-cells = <1>; | |
140 | ranges = <0xa0000000 0xa0000000 0x8000000>; | |
141 | ||
142 | multimedia@a0000000 { | |
143 | compatible = "sirf,prima2-video-codec"; | |
144 | reg = <0xa0000000 0x8000000>; | |
145 | interrupts = <5>; | |
eb8b8f2e | 146 | clocks = <&clks 33>; |
02c981c0 BD |
147 | }; |
148 | }; | |
149 | ||
150 | dsp-iobg { | |
151 | compatible = "simple-bus"; | |
152 | #address-cells = <1>; | |
153 | #size-cells = <1>; | |
154 | ranges = <0xa8000000 0xa8000000 0x2000000>; | |
155 | ||
156 | dspif@a8000000 { | |
157 | compatible = "sirf,prima2-dspif"; | |
158 | reg = <0xa8000000 0x10000>; | |
159 | interrupts = <9>; | |
160 | }; | |
161 | ||
162 | gps@a8010000 { | |
163 | compatible = "sirf,prima2-gps"; | |
164 | reg = <0xa8010000 0x10000>; | |
165 | interrupts = <7>; | |
eb8b8f2e | 166 | clocks = <&clks 9>; |
02c981c0 BD |
167 | }; |
168 | ||
169 | dsp@a9000000 { | |
170 | compatible = "sirf,prima2-dsp"; | |
171 | reg = <0xa9000000 0x1000000>; | |
172 | interrupts = <8>; | |
eb8b8f2e | 173 | clocks = <&clks 8>; |
02c981c0 BD |
174 | }; |
175 | }; | |
176 | ||
177 | peri-iobg { | |
178 | compatible = "simple-bus"; | |
179 | #address-cells = <1>; | |
180 | #size-cells = <1>; | |
9e85b9d1 BS |
181 | ranges = <0xb0000000 0xb0000000 0x180000>, |
182 | <0x56000000 0x56000000 0x1b00000>; | |
02c981c0 BD |
183 | |
184 | timer@b0020000 { | |
185 | compatible = "sirf,prima2-tick"; | |
186 | reg = <0xb0020000 0x1000>; | |
187 | interrupts = <0>; | |
188 | }; | |
189 | ||
190 | nand@b0030000 { | |
191 | compatible = "sirf,prima2-nand"; | |
192 | reg = <0xb0030000 0x10000>; | |
193 | interrupts = <41>; | |
eb8b8f2e | 194 | clocks = <&clks 26>; |
02c981c0 BD |
195 | }; |
196 | ||
197 | audio@b0040000 { | |
198 | compatible = "sirf,prima2-audio"; | |
199 | reg = <0xb0040000 0x10000>; | |
200 | interrupts = <35>; | |
eb8b8f2e | 201 | clocks = <&clks 27>; |
02c981c0 BD |
202 | }; |
203 | ||
204 | uart0: uart@b0050000 { | |
205 | cell-index = <0>; | |
206 | compatible = "sirf,prima2-uart"; | |
a1369978 | 207 | reg = <0xb0050000 0x1000>; |
02c981c0 | 208 | interrupts = <17>; |
a1369978 | 209 | fifosize = <128>; |
eb8b8f2e | 210 | clocks = <&clks 13>; |
a1369978 QL |
211 | sirf,uart-dma-rx-channel = <21>; |
212 | sirf,uart-dma-tx-channel = <2>; | |
02c981c0 BD |
213 | }; |
214 | ||
215 | uart1: uart@b0060000 { | |
216 | cell-index = <1>; | |
217 | compatible = "sirf,prima2-uart"; | |
a1369978 | 218 | reg = <0xb0060000 0x1000>; |
02c981c0 | 219 | interrupts = <18>; |
a1369978 | 220 | fifosize = <32>; |
eb8b8f2e | 221 | clocks = <&clks 14>; |
02c981c0 BD |
222 | }; |
223 | ||
224 | uart2: uart@b0070000 { | |
225 | cell-index = <2>; | |
226 | compatible = "sirf,prima2-uart"; | |
a1369978 | 227 | reg = <0xb0070000 0x1000>; |
02c981c0 | 228 | interrupts = <19>; |
a1369978 | 229 | fifosize = <128>; |
eb8b8f2e | 230 | clocks = <&clks 15>; |
a1369978 QL |
231 | sirf,uart-dma-rx-channel = <6>; |
232 | sirf,uart-dma-tx-channel = <7>; | |
02c981c0 BD |
233 | }; |
234 | ||
235 | usp0: usp@b0080000 { | |
236 | cell-index = <0>; | |
237 | compatible = "sirf,prima2-usp"; | |
238 | reg = <0xb0080000 0x10000>; | |
239 | interrupts = <20>; | |
a1369978 | 240 | fifosize = <128>; |
eb8b8f2e | 241 | clocks = <&clks 28>; |
a1369978 QL |
242 | sirf,usp-dma-rx-channel = <17>; |
243 | sirf,usp-dma-tx-channel = <18>; | |
02c981c0 BD |
244 | }; |
245 | ||
246 | usp1: usp@b0090000 { | |
247 | cell-index = <1>; | |
248 | compatible = "sirf,prima2-usp"; | |
249 | reg = <0xb0090000 0x10000>; | |
250 | interrupts = <21>; | |
a1369978 | 251 | fifosize = <128>; |
eb8b8f2e | 252 | clocks = <&clks 29>; |
a1369978 QL |
253 | sirf,usp-dma-rx-channel = <14>; |
254 | sirf,usp-dma-tx-channel = <15>; | |
02c981c0 BD |
255 | }; |
256 | ||
257 | usp2: usp@b00a0000 { | |
258 | cell-index = <2>; | |
259 | compatible = "sirf,prima2-usp"; | |
260 | reg = <0xb00a0000 0x10000>; | |
261 | interrupts = <22>; | |
a1369978 | 262 | fifosize = <128>; |
eb8b8f2e | 263 | clocks = <&clks 30>; |
a1369978 QL |
264 | sirf,usp-dma-rx-channel = <10>; |
265 | sirf,usp-dma-tx-channel = <11>; | |
02c981c0 BD |
266 | }; |
267 | ||
268 | dmac0: dma-controller@b00b0000 { | |
269 | cell-index = <0>; | |
270 | compatible = "sirf,prima2-dmac"; | |
271 | reg = <0xb00b0000 0x10000>; | |
272 | interrupts = <12>; | |
eb8b8f2e | 273 | clocks = <&clks 24>; |
02c981c0 BD |
274 | }; |
275 | ||
276 | dmac1: dma-controller@b0160000 { | |
277 | cell-index = <1>; | |
278 | compatible = "sirf,prima2-dmac"; | |
279 | reg = <0xb0160000 0x10000>; | |
280 | interrupts = <13>; | |
eb8b8f2e | 281 | clocks = <&clks 25>; |
02c981c0 BD |
282 | }; |
283 | ||
284 | vip@b00C0000 { | |
285 | compatible = "sirf,prima2-vip"; | |
286 | reg = <0xb00C0000 0x10000>; | |
eb8b8f2e | 287 | clocks = <&clks 31>; |
262bcc1d RW |
288 | interrupts = <14>; |
289 | sirf,vip-dma-rx-channel = <16>; | |
02c981c0 BD |
290 | }; |
291 | ||
292 | spi0: spi@b00d0000 { | |
293 | cell-index = <0>; | |
294 | compatible = "sirf,prima2-spi"; | |
295 | reg = <0xb00d0000 0x10000>; | |
296 | interrupts = <15>; | |
eb8b8f2e | 297 | clocks = <&clks 19>; |
02c981c0 BD |
298 | }; |
299 | ||
300 | spi1: spi@b0170000 { | |
301 | cell-index = <1>; | |
302 | compatible = "sirf,prima2-spi"; | |
303 | reg = <0xb0170000 0x10000>; | |
304 | interrupts = <16>; | |
eb8b8f2e | 305 | clocks = <&clks 20>; |
02c981c0 BD |
306 | }; |
307 | ||
308 | i2c0: i2c@b00e0000 { | |
309 | cell-index = <0>; | |
310 | compatible = "sirf,prima2-i2c"; | |
311 | reg = <0xb00e0000 0x10000>; | |
312 | interrupts = <24>; | |
eb8b8f2e | 313 | clocks = <&clks 17>; |
02c981c0 BD |
314 | }; |
315 | ||
316 | i2c1: i2c@b00f0000 { | |
317 | cell-index = <1>; | |
318 | compatible = "sirf,prima2-i2c"; | |
319 | reg = <0xb00f0000 0x10000>; | |
320 | interrupts = <25>; | |
eb8b8f2e | 321 | clocks = <&clks 18>; |
02c981c0 BD |
322 | }; |
323 | ||
324 | tsc@b0110000 { | |
325 | compatible = "sirf,prima2-tsc"; | |
326 | reg = <0xb0110000 0x10000>; | |
327 | interrupts = <33>; | |
eb8b8f2e | 328 | clocks = <&clks 16>; |
02c981c0 BD |
329 | }; |
330 | ||
056876f6 | 331 | gpio: pinctrl@b0120000 { |
02c981c0 BD |
332 | #gpio-cells = <2>; |
333 | #interrupt-cells = <2>; | |
056876f6 | 334 | compatible = "sirf,prima2-pinctrl"; |
02c981c0 | 335 | reg = <0xb0120000 0x10000>; |
500b6ae3 | 336 | interrupts = <43 44 45 46 47>; |
02c981c0 BD |
337 | gpio-controller; |
338 | interrupt-controller; | |
056876f6 BS |
339 | |
340 | lcd_16pins_a: lcd0@0 { | |
341 | lcd { | |
342 | sirf,pins = "lcd_16bitsgrp"; | |
343 | sirf,function = "lcd_16bits"; | |
344 | }; | |
345 | }; | |
346 | lcd_18pins_a: lcd0@1 { | |
347 | lcd { | |
348 | sirf,pins = "lcd_18bitsgrp"; | |
349 | sirf,function = "lcd_18bits"; | |
350 | }; | |
351 | }; | |
352 | lcd_24pins_a: lcd0@2 { | |
353 | lcd { | |
354 | sirf,pins = "lcd_24bitsgrp"; | |
355 | sirf,function = "lcd_24bits"; | |
356 | }; | |
357 | }; | |
358 | lcdrom_pins_a: lcdrom0@0 { | |
359 | lcd { | |
360 | sirf,pins = "lcdromgrp"; | |
361 | sirf,function = "lcdrom"; | |
362 | }; | |
363 | }; | |
364 | uart0_pins_a: uart0@0 { | |
365 | uart { | |
366 | sirf,pins = "uart0grp"; | |
367 | sirf,function = "uart0"; | |
368 | }; | |
369 | }; | |
370 | uart1_pins_a: uart1@0 { | |
371 | uart { | |
372 | sirf,pins = "uart1grp"; | |
373 | sirf,function = "uart1"; | |
374 | }; | |
375 | }; | |
376 | uart2_pins_a: uart2@0 { | |
377 | uart { | |
378 | sirf,pins = "uart2grp"; | |
379 | sirf,function = "uart2"; | |
380 | }; | |
381 | }; | |
382 | uart2_noflow_pins_a: uart2@1 { | |
383 | uart { | |
384 | sirf,pins = "uart2_nostreamctrlgrp"; | |
385 | sirf,function = "uart2_nostreamctrl"; | |
386 | }; | |
387 | }; | |
388 | spi0_pins_a: spi0@0 { | |
389 | spi { | |
390 | sirf,pins = "spi0grp"; | |
391 | sirf,function = "spi0"; | |
392 | }; | |
393 | }; | |
394 | spi1_pins_a: spi1@0 { | |
395 | spi { | |
396 | sirf,pins = "spi1grp"; | |
397 | sirf,function = "spi1"; | |
398 | }; | |
399 | }; | |
400 | i2c0_pins_a: i2c0@0 { | |
401 | i2c { | |
402 | sirf,pins = "i2c0grp"; | |
403 | sirf,function = "i2c0"; | |
404 | }; | |
405 | }; | |
406 | i2c1_pins_a: i2c1@0 { | |
407 | i2c { | |
408 | sirf,pins = "i2c1grp"; | |
409 | sirf,function = "i2c1"; | |
410 | }; | |
411 | }; | |
412 | pwm0_pins_a: pwm0@0 { | |
413 | pwm { | |
414 | sirf,pins = "pwm0grp"; | |
415 | sirf,function = "pwm0"; | |
416 | }; | |
417 | }; | |
418 | pwm1_pins_a: pwm1@0 { | |
419 | pwm { | |
420 | sirf,pins = "pwm1grp"; | |
421 | sirf,function = "pwm1"; | |
422 | }; | |
423 | }; | |
424 | pwm2_pins_a: pwm2@0 { | |
425 | pwm { | |
426 | sirf,pins = "pwm2grp"; | |
427 | sirf,function = "pwm2"; | |
428 | }; | |
429 | }; | |
430 | pwm3_pins_a: pwm3@0 { | |
431 | pwm { | |
432 | sirf,pins = "pwm3grp"; | |
433 | sirf,function = "pwm3"; | |
434 | }; | |
435 | }; | |
436 | gps_pins_a: gps@0 { | |
437 | gps { | |
438 | sirf,pins = "gpsgrp"; | |
439 | sirf,function = "gps"; | |
440 | }; | |
441 | }; | |
442 | vip_pins_a: vip@0 { | |
443 | vip { | |
444 | sirf,pins = "vipgrp"; | |
445 | sirf,function = "vip"; | |
446 | }; | |
447 | }; | |
448 | sdmmc0_pins_a: sdmmc0@0 { | |
449 | sdmmc0 { | |
450 | sirf,pins = "sdmmc0grp"; | |
451 | sirf,function = "sdmmc0"; | |
452 | }; | |
453 | }; | |
454 | sdmmc1_pins_a: sdmmc1@0 { | |
455 | sdmmc1 { | |
456 | sirf,pins = "sdmmc1grp"; | |
457 | sirf,function = "sdmmc1"; | |
458 | }; | |
459 | }; | |
460 | sdmmc2_pins_a: sdmmc2@0 { | |
461 | sdmmc2 { | |
462 | sirf,pins = "sdmmc2grp"; | |
463 | sirf,function = "sdmmc2"; | |
464 | }; | |
465 | }; | |
466 | sdmmc3_pins_a: sdmmc3@0 { | |
467 | sdmmc3 { | |
468 | sirf,pins = "sdmmc3grp"; | |
469 | sirf,function = "sdmmc3"; | |
470 | }; | |
471 | }; | |
472 | sdmmc4_pins_a: sdmmc4@0 { | |
473 | sdmmc4 { | |
474 | sirf,pins = "sdmmc4grp"; | |
475 | sirf,function = "sdmmc4"; | |
476 | }; | |
477 | }; | |
478 | sdmmc5_pins_a: sdmmc5@0 { | |
479 | sdmmc5 { | |
480 | sirf,pins = "sdmmc5grp"; | |
481 | sirf,function = "sdmmc5"; | |
482 | }; | |
483 | }; | |
484 | i2s_pins_a: i2s@0 { | |
485 | i2s { | |
486 | sirf,pins = "i2sgrp"; | |
487 | sirf,function = "i2s"; | |
488 | }; | |
489 | }; | |
490 | ac97_pins_a: ac97@0 { | |
491 | ac97 { | |
492 | sirf,pins = "ac97grp"; | |
493 | sirf,function = "ac97"; | |
494 | }; | |
495 | }; | |
496 | nand_pins_a: nand@0 { | |
497 | nand { | |
498 | sirf,pins = "nandgrp"; | |
499 | sirf,function = "nand"; | |
500 | }; | |
501 | }; | |
502 | usp0_pins_a: usp0@0 { | |
503 | usp0 { | |
504 | sirf,pins = "usp0grp"; | |
505 | sirf,function = "usp0"; | |
506 | }; | |
507 | }; | |
508 | usp1_pins_a: usp1@0 { | |
509 | usp1 { | |
510 | sirf,pins = "usp1grp"; | |
511 | sirf,function = "usp1"; | |
512 | }; | |
513 | }; | |
514 | usp2_pins_a: usp2@0 { | |
515 | usp2 { | |
516 | sirf,pins = "usp2grp"; | |
517 | sirf,function = "usp2"; | |
518 | }; | |
519 | }; | |
520 | usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { | |
521 | usb0_utmi_drvbus { | |
522 | sirf,pins = "usb0_utmi_drvbusgrp"; | |
523 | sirf,function = "usb0_utmi_drvbus"; | |
524 | }; | |
525 | }; | |
526 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | |
527 | usb1_utmi_drvbus { | |
528 | sirf,pins = "usb1_utmi_drvbusgrp"; | |
529 | sirf,function = "usb1_utmi_drvbus"; | |
530 | }; | |
531 | }; | |
532 | warm_rst_pins_a: warm_rst@0 { | |
533 | warm_rst { | |
534 | sirf,pins = "warm_rstgrp"; | |
535 | sirf,function = "warm_rst"; | |
536 | }; | |
537 | }; | |
538 | pulse_count_pins_a: pulse_count@0 { | |
539 | pulse_count { | |
540 | sirf,pins = "pulse_countgrp"; | |
541 | sirf,function = "pulse_count"; | |
542 | }; | |
543 | }; | |
c8078de8 BS |
544 | cko0_pins_a: cko0@0 { |
545 | cko0 { | |
546 | sirf,pins = "cko0grp"; | |
547 | sirf,function = "cko0"; | |
056876f6 BS |
548 | }; |
549 | }; | |
c8078de8 BS |
550 | cko1_pins_a: cko1@0 { |
551 | cko1 { | |
552 | sirf,pins = "cko1grp"; | |
553 | sirf,function = "cko1"; | |
056876f6 BS |
554 | }; |
555 | }; | |
02c981c0 BD |
556 | }; |
557 | ||
558 | pwm@b0130000 { | |
559 | compatible = "sirf,prima2-pwm"; | |
560 | reg = <0xb0130000 0x10000>; | |
eb8b8f2e | 561 | clocks = <&clks 21>; |
02c981c0 BD |
562 | }; |
563 | ||
564 | efusesys@b0140000 { | |
565 | compatible = "sirf,prima2-efuse"; | |
566 | reg = <0xb0140000 0x10000>; | |
eb8b8f2e | 567 | clocks = <&clks 22>; |
02c981c0 BD |
568 | }; |
569 | ||
570 | pulsec@b0150000 { | |
571 | compatible = "sirf,prima2-pulsec"; | |
572 | reg = <0xb0150000 0x10000>; | |
573 | interrupts = <48>; | |
eb8b8f2e | 574 | clocks = <&clks 23>; |
02c981c0 BD |
575 | }; |
576 | ||
577 | pci-iobg { | |
578 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | |
579 | #address-cells = <1>; | |
580 | #size-cells = <1>; | |
581 | ranges = <0x56000000 0x56000000 0x1b00000>; | |
582 | ||
583 | sd0: sdhci@56000000 { | |
584 | cell-index = <0>; | |
585 | compatible = "sirf,prima2-sdhc"; | |
586 | reg = <0x56000000 0x100000>; | |
587 | interrupts = <38>; | |
588 | }; | |
589 | ||
590 | sd1: sdhci@56100000 { | |
591 | cell-index = <1>; | |
592 | compatible = "sirf,prima2-sdhc"; | |
593 | reg = <0x56100000 0x100000>; | |
594 | interrupts = <38>; | |
595 | }; | |
596 | ||
597 | sd2: sdhci@56200000 { | |
598 | cell-index = <2>; | |
599 | compatible = "sirf,prima2-sdhc"; | |
600 | reg = <0x56200000 0x100000>; | |
601 | interrupts = <23>; | |
602 | }; | |
603 | ||
604 | sd3: sdhci@56300000 { | |
605 | cell-index = <3>; | |
606 | compatible = "sirf,prima2-sdhc"; | |
607 | reg = <0x56300000 0x100000>; | |
608 | interrupts = <23>; | |
609 | }; | |
610 | ||
611 | sd4: sdhci@56400000 { | |
612 | cell-index = <4>; | |
613 | compatible = "sirf,prima2-sdhc"; | |
614 | reg = <0x56400000 0x100000>; | |
615 | interrupts = <39>; | |
616 | }; | |
617 | ||
618 | sd5: sdhci@56500000 { | |
619 | cell-index = <5>; | |
620 | compatible = "sirf,prima2-sdhc"; | |
621 | reg = <0x56500000 0x100000>; | |
622 | interrupts = <39>; | |
623 | }; | |
624 | ||
625 | pci-copy@57900000 { | |
626 | compatible = "sirf,prima2-pcicp"; | |
627 | reg = <0x57900000 0x100000>; | |
628 | interrupts = <40>; | |
629 | }; | |
630 | ||
631 | rom-interface@57a00000 { | |
632 | compatible = "sirf,prima2-romif"; | |
633 | reg = <0x57a00000 0x100000>; | |
634 | }; | |
635 | }; | |
636 | }; | |
637 | ||
638 | rtc-iobg { | |
e88b815e | 639 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; |
02c981c0 BD |
640 | #address-cells = <1>; |
641 | #size-cells = <1>; | |
642 | reg = <0x80030000 0x10000>; | |
643 | ||
644 | gpsrtc@1000 { | |
645 | compatible = "sirf,prima2-gpsrtc"; | |
646 | reg = <0x1000 0x1000>; | |
647 | interrupts = <55 56 57>; | |
648 | }; | |
649 | ||
650 | sysrtc@2000 { | |
651 | compatible = "sirf,prima2-sysrtc"; | |
652 | reg = <0x2000 0x1000>; | |
653 | interrupts = <52 53 54>; | |
654 | }; | |
655 | ||
656 | pwrc@3000 { | |
657 | compatible = "sirf,prima2-pwrc"; | |
658 | reg = <0x3000 0x1000>; | |
659 | interrupts = <32>; | |
660 | }; | |
661 | }; | |
662 | ||
663 | uus-iobg { | |
664 | compatible = "simple-bus"; | |
665 | #address-cells = <1>; | |
666 | #size-cells = <1>; | |
667 | ranges = <0xb8000000 0xb8000000 0x40000>; | |
668 | ||
669 | usb0: usb@b00e0000 { | |
670 | compatible = "chipidea,ci13611a-prima2"; | |
671 | reg = <0xb8000000 0x10000>; | |
672 | interrupts = <10>; | |
eb8b8f2e | 673 | clocks = <&clks 40>; |
02c981c0 BD |
674 | }; |
675 | ||
676 | usb1: usb@b00f0000 { | |
677 | compatible = "chipidea,ci13611a-prima2"; | |
678 | reg = <0xb8010000 0x10000>; | |
679 | interrupts = <11>; | |
eb8b8f2e | 680 | clocks = <&clks 41>; |
02c981c0 BD |
681 | }; |
682 | ||
683 | sata@b00f0000 { | |
684 | compatible = "synopsys,dwc-ahsata"; | |
685 | reg = <0xb8020000 0x10000>; | |
686 | interrupts = <37>; | |
687 | }; | |
688 | ||
689 | security@b00f0000 { | |
690 | compatible = "sirf,prima2-security"; | |
691 | reg = <0xb8030000 0x10000>; | |
692 | interrupts = <42>; | |
eb8b8f2e | 693 | clocks = <&clks 7>; |
02c981c0 BD |
694 | }; |
695 | }; | |
696 | }; | |
697 | }; |