projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 434e1c57 BS |
1 | /* |
| 2 | * DTS file for CSR SiRFprimaII SoC | |
| 3 | * | |
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | |
| 5 | * | |
| 6 | * Licensed under GPLv2 or later. | |
| 7 | */ | |
| 8 | ||
| 9 | /include/ "skeleton.dtsi" | |
| 02c981c0 | 10 | / { |
| 434e1c57 | 11 | compatible = "sirf,prima2"; |
| 02c981c0 BD |
12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; | |
| 14 | interrupt-parent = <&intc>; | |
| 15 | ||
| 02c981c0 BD |
16 | cpus { |
| 17 | #address-cells = <1>; | |
| 18 | #size-cells = <0>; | |
| 19 | ||
| 20 | cpu@0 { | |
| cc73f875 LP |
21 | compatible = "arm,cortex-a9"; |
| 22 | device_type = "cpu"; | |
| 02c981c0 BD |
23 | reg = <0x0>; |
| 24 | d-cache-line-size = <32>; | |
| 25 | i-cache-line-size = <32>; | |
| 26 | d-cache-size = <32768>; | |
| 27 | i-cache-size = <32768>; | |
| 28 | /* from bootloader */ | |
| 29 | timebase-frequency = <0>; | |
| 30 | bus-frequency = <0>; | |
| 31 | clock-frequency = <0>; | |
| 32 | }; | |
| 33 | }; | |
| 34 | ||
| 35 | axi { | |
| 36 | compatible = "simple-bus"; | |
| 37 | #address-cells = <1>; | |
| 38 | #size-cells = <1>; | |
| 39 | ranges = <0x40000000 0x40000000 0x80000000>; | |
| 40 | ||
| 41 | l2-cache-controller@80040000 { | |
| 917d8535 | 42 | compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; |
| 02c981c0 BD |
43 | reg = <0x80040000 0x1000>; |
| 44 | interrupts = <59>; | |
| 917d8535 BS |
45 | arm,tag-latency = <1 1 1>; |
| 46 | arm,data-latency = <1 1 1>; | |
| 47 | arm,filter-ranges = <0 0x40000000>; | |
| 02c981c0 BD |
48 | }; |
| 49 | ||
| 50 | intc: interrupt-controller@80020000 { | |
| 51 | #interrupt-cells = <1>; | |
| 52 | interrupt-controller; | |
| 53 | compatible = "sirf,prima2-intc"; | |
| 54 | reg = <0x80020000 0x1000>; | |
| 55 | }; | |
| 56 | ||
| 57 | sys-iobg { | |
| 58 | compatible = "simple-bus"; | |
| 59 | #address-cells = <1>; | |
| 60 | #size-cells = <1>; | |
| 61 | ranges = <0x88000000 0x88000000 0x40000>; | |
| 62 | ||
| eb8b8f2e | 63 | clks: clock-controller@88000000 { |
| 02c981c0 BD |
64 | compatible = "sirf,prima2-clkc"; |
| 65 | reg = <0x88000000 0x1000>; | |
| 66 | interrupts = <3>; | |
| eb8b8f2e | 67 | #clock-cells = <1>; |
| 02c981c0 BD |
68 | }; |
| 69 | ||
| 70 | reset-controller@88010000 { | |
| 71 | compatible = "sirf,prima2-rstc"; | |
| 72 | reg = <0x88010000 0x1000>; | |
| 73 | }; | |
| 073adf4f BS |
74 | |
| 75 | rsc-controller@88020000 { | |
| 76 | compatible = "sirf,prima2-rsc"; | |
| 77 | reg = <0x88020000 0x1000>; | |
| 78 | }; | |
| 02c981c0 BD |
79 | }; |
| 80 | ||
| 81 | mem-iobg { | |
| 82 | compatible = "simple-bus"; | |
| 83 | #address-cells = <1>; | |
| 84 | #size-cells = <1>; | |
| 85 | ranges = <0x90000000 0x90000000 0x10000>; | |
| 86 | ||
| 87 | memory-controller@90000000 { | |
| 88 | compatible = "sirf,prima2-memc"; | |
| 89 | reg = <0x90000000 0x10000>; | |
| 90 | interrupts = <27>; | |
| eb8b8f2e | 91 | clocks = <&clks 5>; |
| 02c981c0 BD |
92 | }; |
| 93 | }; | |
| 94 | ||
| 95 | disp-iobg { | |
| 96 | compatible = "simple-bus"; | |
| 97 | #address-cells = <1>; | |
| 98 | #size-cells = <1>; | |
| 99 | ranges = <0x90010000 0x90010000 0x30000>; | |
| 100 | ||
| 101 | display@90010000 { | |
| 102 | compatible = "sirf,prima2-lcd"; | |
| 103 | reg = <0x90010000 0x20000>; | |
| 104 | interrupts = <30>; | |
| 105 | }; | |
| 106 | ||
| 107 | vpp@90020000 { | |
| 108 | compatible = "sirf,prima2-vpp"; | |
| 109 | reg = <0x90020000 0x10000>; | |
| 110 | interrupts = <31>; | |
| eb8b8f2e | 111 | clocks = <&clks 35>; |
| 02c981c0 BD |
112 | }; |
| 113 | }; | |
| 114 | ||
| 115 | graphics-iobg { | |
| 116 | compatible = "simple-bus"; | |
| 117 | #address-cells = <1>; | |
| 118 | #size-cells = <1>; | |
| 119 | ranges = <0x98000000 0x98000000 0x8000000>; | |
| 120 | ||
| 121 | graphics@98000000 { | |
| 122 | compatible = "powervr,sgx531"; | |
| 123 | reg = <0x98000000 0x8000000>; | |
| 124 | interrupts = <6>; | |
| eb8b8f2e | 125 | clocks = <&clks 32>; |
| 02c981c0 BD |
126 | }; |
| 127 | }; | |
| 128 | ||
| 129 | multimedia-iobg { | |
| 130 | compatible = "simple-bus"; | |
| 131 | #address-cells = <1>; | |
| 132 | #size-cells = <1>; | |
| 133 | ranges = <0xa0000000 0xa0000000 0x8000000>; | |
| 134 | ||
| 135 | multimedia@a0000000 { | |
| 136 | compatible = "sirf,prima2-video-codec"; | |
| 137 | reg = <0xa0000000 0x8000000>; | |
| 138 | interrupts = <5>; | |
| eb8b8f2e | 139 | clocks = <&clks 33>; |
| 02c981c0 BD |
140 | }; |
| 141 | }; | |
| 142 | ||
| 143 | dsp-iobg { | |
| 144 | compatible = "simple-bus"; | |
| 145 | #address-cells = <1>; | |
| 146 | #size-cells = <1>; | |
| 147 | ranges = <0xa8000000 0xa8000000 0x2000000>; | |
| 148 | ||
| 149 | dspif@a8000000 { | |
| 150 | compatible = "sirf,prima2-dspif"; | |
| 151 | reg = <0xa8000000 0x10000>; | |
| 152 | interrupts = <9>; | |
| 153 | }; | |
| 154 | ||
| 155 | gps@a8010000 { | |
| 156 | compatible = "sirf,prima2-gps"; | |
| 157 | reg = <0xa8010000 0x10000>; | |
| 158 | interrupts = <7>; | |
| eb8b8f2e | 159 | clocks = <&clks 9>; |
| 02c981c0 BD |
160 | }; |
| 161 | ||
| 162 | dsp@a9000000 { | |
| 163 | compatible = "sirf,prima2-dsp"; | |
| 164 | reg = <0xa9000000 0x1000000>; | |
| 165 | interrupts = <8>; | |
| eb8b8f2e | 166 | clocks = <&clks 8>; |
| 02c981c0 BD |
167 | }; |
| 168 | }; | |
| 169 | ||
| 170 | peri-iobg { | |
| 171 | compatible = "simple-bus"; | |
| 172 | #address-cells = <1>; | |
| 173 | #size-cells = <1>; | |
| 174 | ranges = <0xb0000000 0xb0000000 0x180000>; | |
| 175 | ||
| 176 | timer@b0020000 { | |
| 177 | compatible = "sirf,prima2-tick"; | |
| 178 | reg = <0xb0020000 0x1000>; | |
| 179 | interrupts = <0>; | |
| 180 | }; | |
| 181 | ||
| 182 | nand@b0030000 { | |
| 183 | compatible = "sirf,prima2-nand"; | |
| 184 | reg = <0xb0030000 0x10000>; | |
| 185 | interrupts = <41>; | |
| eb8b8f2e | 186 | clocks = <&clks 26>; |
| 02c981c0 BD |
187 | }; |
| 188 | ||
| 189 | audio@b0040000 { | |
| 190 | compatible = "sirf,prima2-audio"; | |
| 191 | reg = <0xb0040000 0x10000>; | |
| 192 | interrupts = <35>; | |
| eb8b8f2e | 193 | clocks = <&clks 27>; |
| 02c981c0 BD |
194 | }; |
| 195 | ||
| 196 | uart0: uart@b0050000 { | |
| 197 | cell-index = <0>; | |
| 198 | compatible = "sirf,prima2-uart"; | |
| 199 | reg = <0xb0050000 0x10000>; | |
| 200 | interrupts = <17>; | |
| eb8b8f2e | 201 | clocks = <&clks 13>; |
| 02c981c0 BD |
202 | }; |
| 203 | ||
| 204 | uart1: uart@b0060000 { | |
| 205 | cell-index = <1>; | |
| 206 | compatible = "sirf,prima2-uart"; | |
| 207 | reg = <0xb0060000 0x10000>; | |
| 208 | interrupts = <18>; | |
| eb8b8f2e | 209 | clocks = <&clks 14>; |
| 02c981c0 BD |
210 | }; |
| 211 | ||
| 212 | uart2: uart@b0070000 { | |
| 213 | cell-index = <2>; | |
| 214 | compatible = "sirf,prima2-uart"; | |
| 215 | reg = <0xb0070000 0x10000>; | |
| 216 | interrupts = <19>; | |
| eb8b8f2e | 217 | clocks = <&clks 15>; |
| 02c981c0 BD |
218 | }; |
| 219 | ||
| 220 | usp0: usp@b0080000 { | |
| 221 | cell-index = <0>; | |
| 222 | compatible = "sirf,prima2-usp"; | |
| 223 | reg = <0xb0080000 0x10000>; | |
| 224 | interrupts = <20>; | |
| eb8b8f2e | 225 | clocks = <&clks 28>; |
| 02c981c0 BD |
226 | }; |
| 227 | ||
| 228 | usp1: usp@b0090000 { | |
| 229 | cell-index = <1>; | |
| 230 | compatible = "sirf,prima2-usp"; | |
| 231 | reg = <0xb0090000 0x10000>; | |
| 232 | interrupts = <21>; | |
| eb8b8f2e | 233 | clocks = <&clks 29>; |
| 02c981c0 BD |
234 | }; |
| 235 | ||
| 236 | usp2: usp@b00a0000 { | |
| 237 | cell-index = <2>; | |
| 238 | compatible = "sirf,prima2-usp"; | |
| 239 | reg = <0xb00a0000 0x10000>; | |
| 240 | interrupts = <22>; | |
| eb8b8f2e | 241 | clocks = <&clks 30>; |
| 02c981c0 BD |
242 | }; |
| 243 | ||
| 244 | dmac0: dma-controller@b00b0000 { | |
| 245 | cell-index = <0>; | |
| 246 | compatible = "sirf,prima2-dmac"; | |
| 247 | reg = <0xb00b0000 0x10000>; | |
| 248 | interrupts = <12>; | |
| eb8b8f2e | 249 | clocks = <&clks 24>; |
| 02c981c0 BD |
250 | }; |
| 251 | ||
| 252 | dmac1: dma-controller@b0160000 { | |
| 253 | cell-index = <1>; | |
| 254 | compatible = "sirf,prima2-dmac"; | |
| 255 | reg = <0xb0160000 0x10000>; | |
| 256 | interrupts = <13>; | |
| eb8b8f2e | 257 | clocks = <&clks 25>; |
| 02c981c0 BD |
258 | }; |
| 259 | ||
| 260 | vip@b00C0000 { | |
| 261 | compatible = "sirf,prima2-vip"; | |
| 262 | reg = <0xb00C0000 0x10000>; | |
| eb8b8f2e | 263 | clocks = <&clks 31>; |
| 02c981c0 BD |
264 | }; |
| 265 | ||
| 266 | spi0: spi@b00d0000 { | |
| 267 | cell-index = <0>; | |
| 268 | compatible = "sirf,prima2-spi"; | |
| 269 | reg = <0xb00d0000 0x10000>; | |
| 270 | interrupts = <15>; | |
| eb8b8f2e | 271 | clocks = <&clks 19>; |
| 02c981c0 BD |
272 | }; |
| 273 | ||
| 274 | spi1: spi@b0170000 { | |
| 275 | cell-index = <1>; | |
| 276 | compatible = "sirf,prima2-spi"; | |
| 277 | reg = <0xb0170000 0x10000>; | |
| 278 | interrupts = <16>; | |
| eb8b8f2e | 279 | clocks = <&clks 20>; |
| 02c981c0 BD |
280 | }; |
| 281 | ||
| 282 | i2c0: i2c@b00e0000 { | |
| 283 | cell-index = <0>; | |
| 284 | compatible = "sirf,prima2-i2c"; | |
| 285 | reg = <0xb00e0000 0x10000>; | |
| 286 | interrupts = <24>; | |
| eb8b8f2e | 287 | clocks = <&clks 17>; |
| 02c981c0 BD |
288 | }; |
| 289 | ||
| 290 | i2c1: i2c@b00f0000 { | |
| 291 | cell-index = <1>; | |
| 292 | compatible = "sirf,prima2-i2c"; | |
| 293 | reg = <0xb00f0000 0x10000>; | |
| 294 | interrupts = <25>; | |
| eb8b8f2e | 295 | clocks = <&clks 18>; |
| 02c981c0 BD |
296 | }; |
| 297 | ||
| 298 | tsc@b0110000 { | |
| 299 | compatible = "sirf,prima2-tsc"; | |
| 300 | reg = <0xb0110000 0x10000>; | |
| 301 | interrupts = <33>; | |
| eb8b8f2e | 302 | clocks = <&clks 16>; |
| 02c981c0 BD |
303 | }; |
| 304 | ||
| 056876f6 | 305 | gpio: pinctrl@b0120000 { |
| 02c981c0 BD |
306 | #gpio-cells = <2>; |
| 307 | #interrupt-cells = <2>; | |
| 056876f6 | 308 | compatible = "sirf,prima2-pinctrl"; |
| 02c981c0 | 309 | reg = <0xb0120000 0x10000>; |
| 500b6ae3 | 310 | interrupts = <43 44 45 46 47>; |
| 02c981c0 BD |
311 | gpio-controller; |
| 312 | interrupt-controller; | |
| 056876f6 BS |
313 | |
| 314 | lcd_16pins_a: lcd0@0 { | |
| 315 | lcd { | |
| 316 | sirf,pins = "lcd_16bitsgrp"; | |
| 317 | sirf,function = "lcd_16bits"; | |
| 318 | }; | |
| 319 | }; | |
| 320 | lcd_18pins_a: lcd0@1 { | |
| 321 | lcd { | |
| 322 | sirf,pins = "lcd_18bitsgrp"; | |
| 323 | sirf,function = "lcd_18bits"; | |
| 324 | }; | |
| 325 | }; | |
| 326 | lcd_24pins_a: lcd0@2 { | |
| 327 | lcd { | |
| 328 | sirf,pins = "lcd_24bitsgrp"; | |
| 329 | sirf,function = "lcd_24bits"; | |
| 330 | }; | |
| 331 | }; | |
| 332 | lcdrom_pins_a: lcdrom0@0 { | |
| 333 | lcd { | |
| 334 | sirf,pins = "lcdromgrp"; | |
| 335 | sirf,function = "lcdrom"; | |
| 336 | }; | |
| 337 | }; | |
| 338 | uart0_pins_a: uart0@0 { | |
| 339 | uart { | |
| 340 | sirf,pins = "uart0grp"; | |
| 341 | sirf,function = "uart0"; | |
| 342 | }; | |
| 343 | }; | |
| fb85f429 QL |
344 | uart0_noflow_pins_a: uart0@1 { |
| 345 | uart { | |
| 346 | sirf,pins = "uart0_nostreamctrlgrp"; | |
| 347 | sirf,function = "uart0_nostreamctrl"; | |
| 348 | }; | |
| 349 | }; | |
| 056876f6 BS |
350 | uart1_pins_a: uart1@0 { |
| 351 | uart { | |
| 352 | sirf,pins = "uart1grp"; | |
| 353 | sirf,function = "uart1"; | |
| 354 | }; | |
| 355 | }; | |
| 356 | uart2_pins_a: uart2@0 { | |
| 357 | uart { | |
| 358 | sirf,pins = "uart2grp"; | |
| 359 | sirf,function = "uart2"; | |
| 360 | }; | |
| 361 | }; | |
| 362 | uart2_noflow_pins_a: uart2@1 { | |
| 363 | uart { | |
| 364 | sirf,pins = "uart2_nostreamctrlgrp"; | |
| 365 | sirf,function = "uart2_nostreamctrl"; | |
| 366 | }; | |
| 367 | }; | |
| 368 | spi0_pins_a: spi0@0 { | |
| 369 | spi { | |
| 370 | sirf,pins = "spi0grp"; | |
| 371 | sirf,function = "spi0"; | |
| 372 | }; | |
| 373 | }; | |
| 374 | spi1_pins_a: spi1@0 { | |
| 375 | spi { | |
| 376 | sirf,pins = "spi1grp"; | |
| 377 | sirf,function = "spi1"; | |
| 378 | }; | |
| 379 | }; | |
| 380 | i2c0_pins_a: i2c0@0 { | |
| 381 | i2c { | |
| 382 | sirf,pins = "i2c0grp"; | |
| 383 | sirf,function = "i2c0"; | |
| 384 | }; | |
| 385 | }; | |
| 386 | i2c1_pins_a: i2c1@0 { | |
| 387 | i2c { | |
| 388 | sirf,pins = "i2c1grp"; | |
| 389 | sirf,function = "i2c1"; | |
| 390 | }; | |
| 391 | }; | |
| 392 | pwm0_pins_a: pwm0@0 { | |
| 393 | pwm { | |
| 394 | sirf,pins = "pwm0grp"; | |
| 395 | sirf,function = "pwm0"; | |
| 396 | }; | |
| 397 | }; | |
| 398 | pwm1_pins_a: pwm1@0 { | |
| 399 | pwm { | |
| 400 | sirf,pins = "pwm1grp"; | |
| 401 | sirf,function = "pwm1"; | |
| 402 | }; | |
| 403 | }; | |
| 404 | pwm2_pins_a: pwm2@0 { | |
| 405 | pwm { | |
| 406 | sirf,pins = "pwm2grp"; | |
| 407 | sirf,function = "pwm2"; | |
| 408 | }; | |
| 409 | }; | |
| 410 | pwm3_pins_a: pwm3@0 { | |
| 411 | pwm { | |
| 412 | sirf,pins = "pwm3grp"; | |
| 413 | sirf,function = "pwm3"; | |
| 414 | }; | |
| 415 | }; | |
| 416 | gps_pins_a: gps@0 { | |
| 417 | gps { | |
| 418 | sirf,pins = "gpsgrp"; | |
| 419 | sirf,function = "gps"; | |
| 420 | }; | |
| 421 | }; | |
| 422 | vip_pins_a: vip@0 { | |
| 423 | vip { | |
| 424 | sirf,pins = "vipgrp"; | |
| 425 | sirf,function = "vip"; | |
| 426 | }; | |
| 427 | }; | |
| 428 | sdmmc0_pins_a: sdmmc0@0 { | |
| 429 | sdmmc0 { | |
| 430 | sirf,pins = "sdmmc0grp"; | |
| 431 | sirf,function = "sdmmc0"; | |
| 432 | }; | |
| 433 | }; | |
| 434 | sdmmc1_pins_a: sdmmc1@0 { | |
| 435 | sdmmc1 { | |
| 436 | sirf,pins = "sdmmc1grp"; | |
| 437 | sirf,function = "sdmmc1"; | |
| 438 | }; | |
| 439 | }; | |
| 440 | sdmmc2_pins_a: sdmmc2@0 { | |
| 441 | sdmmc2 { | |
| 442 | sirf,pins = "sdmmc2grp"; | |
| 443 | sirf,function = "sdmmc2"; | |
| 444 | }; | |
| 445 | }; | |
| 446 | sdmmc3_pins_a: sdmmc3@0 { | |
| 447 | sdmmc3 { | |
| 448 | sirf,pins = "sdmmc3grp"; | |
| 449 | sirf,function = "sdmmc3"; | |
| 450 | }; | |
| 451 | }; | |
| 452 | sdmmc4_pins_a: sdmmc4@0 { | |
| 453 | sdmmc4 { | |
| 454 | sirf,pins = "sdmmc4grp"; | |
| 455 | sirf,function = "sdmmc4"; | |
| 456 | }; | |
| 457 | }; | |
| 458 | sdmmc5_pins_a: sdmmc5@0 { | |
| 459 | sdmmc5 { | |
| 460 | sirf,pins = "sdmmc5grp"; | |
| 461 | sirf,function = "sdmmc5"; | |
| 462 | }; | |
| 463 | }; | |
| 464 | i2s_pins_a: i2s@0 { | |
| 465 | i2s { | |
| 466 | sirf,pins = "i2sgrp"; | |
| 467 | sirf,function = "i2s"; | |
| 468 | }; | |
| 469 | }; | |
| 470 | ac97_pins_a: ac97@0 { | |
| 471 | ac97 { | |
| 472 | sirf,pins = "ac97grp"; | |
| 473 | sirf,function = "ac97"; | |
| 474 | }; | |
| 475 | }; | |
| 476 | nand_pins_a: nand@0 { | |
| 477 | nand { | |
| 478 | sirf,pins = "nandgrp"; | |
| 479 | sirf,function = "nand"; | |
| 480 | }; | |
| 481 | }; | |
| 482 | usp0_pins_a: usp0@0 { | |
| 483 | usp0 { | |
| 484 | sirf,pins = "usp0grp"; | |
| 485 | sirf,function = "usp0"; | |
| 486 | }; | |
| 487 | }; | |
| af614b23 QL |
488 | usp0_uart_nostreamctrl_pins_a: usp0@1 { |
| 489 | usp0 { | |
| 490 | sirf,pins = | |
| 491 | "usp0_uart_nostreamctrl_grp"; | |
| 492 | sirf,function = | |
| 493 | "usp0_uart_nostreamctrl"; | |
| 494 | }; | |
| 495 | }; | |
| 056876f6 BS |
496 | usp1_pins_a: usp1@0 { |
| 497 | usp1 { | |
| 498 | sirf,pins = "usp1grp"; | |
| 499 | sirf,function = "usp1"; | |
| 500 | }; | |
| 501 | }; | |
| af614b23 QL |
502 | usp1_uart_nostreamctrl_pins_a: usp1@1 { |
| 503 | usp1 { | |
| 504 | sirf,pins = | |
| 505 | "usp1_uart_nostreamctrl_grp"; | |
| 506 | sirf,function = | |
| 507 | "usp1_uart_nostreamctrl"; | |
| 508 | }; | |
| 509 | }; | |
| 056876f6 BS |
510 | usp2_pins_a: usp2@0 { |
| 511 | usp2 { | |
| 512 | sirf,pins = "usp2grp"; | |
| 513 | sirf,function = "usp2"; | |
| 514 | }; | |
| 515 | }; | |
| af614b23 QL |
516 | usp2_uart_nostreamctrl_pins_a: usp2@1 { |
| 517 | usp2 { | |
| 518 | sirf,pins = | |
| 519 | "usp2_uart_nostreamctrl_grp"; | |
| 520 | sirf,function = | |
| 521 | "usp2_uart_nostreamctrl"; | |
| 522 | }; | |
| 523 | }; | |
| 056876f6 BS |
524 | usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { |
| 525 | usb0_utmi_drvbus { | |
| 526 | sirf,pins = "usb0_utmi_drvbusgrp"; | |
| 527 | sirf,function = "usb0_utmi_drvbus"; | |
| 528 | }; | |
| 529 | }; | |
| 530 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | |
| 531 | usb1_utmi_drvbus { | |
| 532 | sirf,pins = "usb1_utmi_drvbusgrp"; | |
| 533 | sirf,function = "usb1_utmi_drvbus"; | |
| 534 | }; | |
| 535 | }; | |
| 536 | warm_rst_pins_a: warm_rst@0 { | |
| 537 | warm_rst { | |
| 538 | sirf,pins = "warm_rstgrp"; | |
| 539 | sirf,function = "warm_rst"; | |
| 540 | }; | |
| 541 | }; | |
| 542 | pulse_count_pins_a: pulse_count@0 { | |
| 543 | pulse_count { | |
| 544 | sirf,pins = "pulse_countgrp"; | |
| 545 | sirf,function = "pulse_count"; | |
| 546 | }; | |
| 547 | }; | |
| c8078de8 BS |
548 | cko0_pins_a: cko0@0 { |
| 549 | cko0 { | |
| 550 | sirf,pins = "cko0grp"; | |
| 551 | sirf,function = "cko0"; | |
| 056876f6 BS |
552 | }; |
| 553 | }; | |
| c8078de8 BS |
554 | cko1_pins_a: cko1@0 { |
| 555 | cko1 { | |
| 556 | sirf,pins = "cko1grp"; | |
| 557 | sirf,function = "cko1"; | |
| 056876f6 BS |
558 | }; |
| 559 | }; | |
| 02c981c0 BD |
560 | }; |
| 561 | ||
| 562 | pwm@b0130000 { | |
| 563 | compatible = "sirf,prima2-pwm"; | |
| 564 | reg = <0xb0130000 0x10000>; | |
| eb8b8f2e | 565 | clocks = <&clks 21>; |
| 02c981c0 BD |
566 | }; |
| 567 | ||
| 568 | efusesys@b0140000 { | |
| 569 | compatible = "sirf,prima2-efuse"; | |
| 570 | reg = <0xb0140000 0x10000>; | |
| eb8b8f2e | 571 | clocks = <&clks 22>; |
| 02c981c0 BD |
572 | }; |
| 573 | ||
| 574 | pulsec@b0150000 { | |
| 575 | compatible = "sirf,prima2-pulsec"; | |
| 576 | reg = <0xb0150000 0x10000>; | |
| 577 | interrupts = <48>; | |
| eb8b8f2e | 578 | clocks = <&clks 23>; |
| 02c981c0 BD |
579 | }; |
| 580 | ||
| 581 | pci-iobg { | |
| 582 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | |
| 583 | #address-cells = <1>; | |
| 584 | #size-cells = <1>; | |
| 585 | ranges = <0x56000000 0x56000000 0x1b00000>; | |
| 586 | ||
| 587 | sd0: sdhci@56000000 { | |
| 588 | cell-index = <0>; | |
| 589 | compatible = "sirf,prima2-sdhc"; | |
| 590 | reg = <0x56000000 0x100000>; | |
| 591 | interrupts = <38>; | |
| 592 | }; | |
| 593 | ||
| 594 | sd1: sdhci@56100000 { | |
| 595 | cell-index = <1>; | |
| 596 | compatible = "sirf,prima2-sdhc"; | |
| 597 | reg = <0x56100000 0x100000>; | |
| 598 | interrupts = <38>; | |
| 599 | }; | |
| 600 | ||
| 601 | sd2: sdhci@56200000 { | |
| 602 | cell-index = <2>; | |
| 603 | compatible = "sirf,prima2-sdhc"; | |
| 604 | reg = <0x56200000 0x100000>; | |
| 605 | interrupts = <23>; | |
| 606 | }; | |
| 607 | ||
| 608 | sd3: sdhci@56300000 { | |
| 609 | cell-index = <3>; | |
| 610 | compatible = "sirf,prima2-sdhc"; | |
| 611 | reg = <0x56300000 0x100000>; | |
| 612 | interrupts = <23>; | |
| 613 | }; | |
| 614 | ||
| 615 | sd4: sdhci@56400000 { | |
| 616 | cell-index = <4>; | |
| 617 | compatible = "sirf,prima2-sdhc"; | |
| 618 | reg = <0x56400000 0x100000>; | |
| 619 | interrupts = <39>; | |
| 620 | }; | |
| 621 | ||
| 622 | sd5: sdhci@56500000 { | |
| 623 | cell-index = <5>; | |
| 624 | compatible = "sirf,prima2-sdhc"; | |
| 625 | reg = <0x56500000 0x100000>; | |
| 626 | interrupts = <39>; | |
| 627 | }; | |
| 628 | ||
| 629 | pci-copy@57900000 { | |
| 630 | compatible = "sirf,prima2-pcicp"; | |
| 631 | reg = <0x57900000 0x100000>; | |
| 632 | interrupts = <40>; | |
| 633 | }; | |
| 634 | ||
| 635 | rom-interface@57a00000 { | |
| 636 | compatible = "sirf,prima2-romif"; | |
| 637 | reg = <0x57a00000 0x100000>; | |
| 638 | }; | |
| 639 | }; | |
| 640 | }; | |
| 641 | ||
| 642 | rtc-iobg { | |
| e88b815e | 643 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; |
| 02c981c0 BD |
644 | #address-cells = <1>; |
| 645 | #size-cells = <1>; | |
| 646 | reg = <0x80030000 0x10000>; | |
| 647 | ||
| 648 | gpsrtc@1000 { | |
| 649 | compatible = "sirf,prima2-gpsrtc"; | |
| 650 | reg = <0x1000 0x1000>; | |
| 651 | interrupts = <55 56 57>; | |
| 652 | }; | |
| 653 | ||
| 654 | sysrtc@2000 { | |
| 655 | compatible = "sirf,prima2-sysrtc"; | |
| 656 | reg = <0x2000 0x1000>; | |
| 657 | interrupts = <52 53 54>; | |
| 658 | }; | |
| 659 | ||
| 660 | pwrc@3000 { | |
| 661 | compatible = "sirf,prima2-pwrc"; | |
| 662 | reg = <0x3000 0x1000>; | |
| 663 | interrupts = <32>; | |
| 664 | }; | |
| 665 | }; | |
| 666 | ||
| 667 | uus-iobg { | |
| 668 | compatible = "simple-bus"; | |
| 669 | #address-cells = <1>; | |
| 670 | #size-cells = <1>; | |
| 671 | ranges = <0xb8000000 0xb8000000 0x40000>; | |
| 672 | ||
| 673 | usb0: usb@b00e0000 { | |
| 674 | compatible = "chipidea,ci13611a-prima2"; | |
| 675 | reg = <0xb8000000 0x10000>; | |
| 676 | interrupts = <10>; | |
| eb8b8f2e | 677 | clocks = <&clks 40>; |
| 02c981c0 BD |
678 | }; |
| 679 | ||
| 680 | usb1: usb@b00f0000 { | |
| 681 | compatible = "chipidea,ci13611a-prima2"; | |
| 682 | reg = <0xb8010000 0x10000>; | |
| 683 | interrupts = <11>; | |
| eb8b8f2e | 684 | clocks = <&clks 41>; |
| 02c981c0 BD |
685 | }; |
| 686 | ||
| 687 | sata@b00f0000 { | |
| 688 | compatible = "synopsys,dwc-ahsata"; | |
| 689 | reg = <0xb8020000 0x10000>; | |
| 690 | interrupts = <37>; | |
| 691 | }; | |
| 692 | ||
| 693 | security@b00f0000 { | |
| 694 | compatible = "sirf,prima2-security"; | |
| 695 | reg = <0xb8030000 0x10000>; | |
| 696 | interrupts = <42>; | |
| eb8b8f2e | 697 | clocks = <&clks 7>; |
| 02c981c0 BD |
698 | }; |
| 699 | }; | |
| 700 | }; | |
| 701 | }; |