projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 434e1c57 BS |
1 | /* |
| 2 | * DTS file for CSR SiRFprimaII SoC | |
| 3 | * | |
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | |
| 5 | * | |
| 6 | * Licensed under GPLv2 or later. | |
| 7 | */ | |
| 8 | ||
| 9 | /include/ "skeleton.dtsi" | |
| 02c981c0 | 10 | / { |
| 434e1c57 | 11 | compatible = "sirf,prima2"; |
| 02c981c0 BD |
12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; | |
| 14 | interrupt-parent = <&intc>; | |
| 15 | ||
| 02c981c0 BD |
16 | cpus { |
| 17 | #address-cells = <1>; | |
| 18 | #size-cells = <0>; | |
| 19 | ||
| 20 | cpu@0 { | |
| cc73f875 LP |
21 | compatible = "arm,cortex-a9"; |
| 22 | device_type = "cpu"; | |
| 02c981c0 BD |
23 | reg = <0x0>; |
| 24 | d-cache-line-size = <32>; | |
| 25 | i-cache-line-size = <32>; | |
| 26 | d-cache-size = <32768>; | |
| 27 | i-cache-size = <32768>; | |
| 28 | /* from bootloader */ | |
| 29 | timebase-frequency = <0>; | |
| 30 | bus-frequency = <0>; | |
| 31 | clock-frequency = <0>; | |
| 683659f3 RY |
32 | clocks = <&clks 12>; |
| 33 | operating-points = < | |
| 34 | /* kHz uV */ | |
| 35 | 200000 1025000 | |
| 36 | 400000 1025000 | |
| 37 | 664000 1050000 | |
| 38 | 800000 1100000 | |
| 39 | >; | |
| 40 | clock-latency = <150000>; | |
| 02c981c0 BD |
41 | }; |
| 42 | }; | |
| 43 | ||
| 44 | axi { | |
| 45 | compatible = "simple-bus"; | |
| 46 | #address-cells = <1>; | |
| 47 | #size-cells = <1>; | |
| 48 | ranges = <0x40000000 0x40000000 0x80000000>; | |
| 49 | ||
| 50 | l2-cache-controller@80040000 { | |
| 917d8535 | 51 | compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; |
| 02c981c0 BD |
52 | reg = <0x80040000 0x1000>; |
| 53 | interrupts = <59>; | |
| 917d8535 BS |
54 | arm,tag-latency = <1 1 1>; |
| 55 | arm,data-latency = <1 1 1>; | |
| 56 | arm,filter-ranges = <0 0x40000000>; | |
| 02c981c0 BD |
57 | }; |
| 58 | ||
| 59 | intc: interrupt-controller@80020000 { | |
| 60 | #interrupt-cells = <1>; | |
| 61 | interrupt-controller; | |
| 62 | compatible = "sirf,prima2-intc"; | |
| 63 | reg = <0x80020000 0x1000>; | |
| 64 | }; | |
| 65 | ||
| 66 | sys-iobg { | |
| 67 | compatible = "simple-bus"; | |
| 68 | #address-cells = <1>; | |
| 69 | #size-cells = <1>; | |
| 70 | ranges = <0x88000000 0x88000000 0x40000>; | |
| 71 | ||
| eb8b8f2e | 72 | clks: clock-controller@88000000 { |
| 02c981c0 BD |
73 | compatible = "sirf,prima2-clkc"; |
| 74 | reg = <0x88000000 0x1000>; | |
| 75 | interrupts = <3>; | |
| eb8b8f2e | 76 | #clock-cells = <1>; |
| 02c981c0 BD |
77 | }; |
| 78 | ||
| 79 | reset-controller@88010000 { | |
| 80 | compatible = "sirf,prima2-rstc"; | |
| 81 | reg = <0x88010000 0x1000>; | |
| 82 | }; | |
| 073adf4f BS |
83 | |
| 84 | rsc-controller@88020000 { | |
| 85 | compatible = "sirf,prima2-rsc"; | |
| 86 | reg = <0x88020000 0x1000>; | |
| 87 | }; | |
| 0671840c BS |
88 | |
| 89 | cphifbg@88030000 { | |
| 90 | compatible = "sirf,prima2-cphifbg"; | |
| 91 | reg = <0x88030000 0x1000>; | |
| 794f8b21 | 92 | clocks = <&clks 42>; |
| 0671840c | 93 | }; |
| 02c981c0 BD |
94 | }; |
| 95 | ||
| 96 | mem-iobg { | |
| 97 | compatible = "simple-bus"; | |
| 98 | #address-cells = <1>; | |
| 99 | #size-cells = <1>; | |
| 100 | ranges = <0x90000000 0x90000000 0x10000>; | |
| 101 | ||
| 102 | memory-controller@90000000 { | |
| 103 | compatible = "sirf,prima2-memc"; | |
| 5fadea22 | 104 | reg = <0x90000000 0x2000>; |
| 02c981c0 | 105 | interrupts = <27>; |
| eb8b8f2e | 106 | clocks = <&clks 5>; |
| 02c981c0 | 107 | }; |
| 5fadea22 YH |
108 | |
| 109 | memc-monitor { | |
| 110 | compatible = "sirf,prima2-memcmon"; | |
| 111 | reg = <0x90002000 0x200>; | |
| 112 | interrupts = <4>; | |
| 113 | clocks = <&clks 32>; | |
| 114 | }; | |
| 02c981c0 BD |
115 | }; |
| 116 | ||
| 117 | disp-iobg { | |
| 118 | compatible = "simple-bus"; | |
| 119 | #address-cells = <1>; | |
| 120 | #size-cells = <1>; | |
| 121 | ranges = <0x90010000 0x90010000 0x30000>; | |
| 122 | ||
| 123 | display@90010000 { | |
| 124 | compatible = "sirf,prima2-lcd"; | |
| 125 | reg = <0x90010000 0x20000>; | |
| 126 | interrupts = <30>; | |
| 127 | }; | |
| 128 | ||
| 129 | vpp@90020000 { | |
| 130 | compatible = "sirf,prima2-vpp"; | |
| 131 | reg = <0x90020000 0x10000>; | |
| 132 | interrupts = <31>; | |
| eb8b8f2e | 133 | clocks = <&clks 35>; |
| 02c981c0 BD |
134 | }; |
| 135 | }; | |
| 136 | ||
| 137 | graphics-iobg { | |
| 138 | compatible = "simple-bus"; | |
| 139 | #address-cells = <1>; | |
| 140 | #size-cells = <1>; | |
| 141 | ranges = <0x98000000 0x98000000 0x8000000>; | |
| 142 | ||
| 143 | graphics@98000000 { | |
| 144 | compatible = "powervr,sgx531"; | |
| 145 | reg = <0x98000000 0x8000000>; | |
| 146 | interrupts = <6>; | |
| eb8b8f2e | 147 | clocks = <&clks 32>; |
| 02c981c0 BD |
148 | }; |
| 149 | }; | |
| 150 | ||
| 151 | multimedia-iobg { | |
| 152 | compatible = "simple-bus"; | |
| 153 | #address-cells = <1>; | |
| 154 | #size-cells = <1>; | |
| 155 | ranges = <0xa0000000 0xa0000000 0x8000000>; | |
| 156 | ||
| 157 | multimedia@a0000000 { | |
| 158 | compatible = "sirf,prima2-video-codec"; | |
| 159 | reg = <0xa0000000 0x8000000>; | |
| 160 | interrupts = <5>; | |
| eb8b8f2e | 161 | clocks = <&clks 33>; |
| 02c981c0 BD |
162 | }; |
| 163 | }; | |
| 164 | ||
| 165 | dsp-iobg { | |
| 166 | compatible = "simple-bus"; | |
| 167 | #address-cells = <1>; | |
| 168 | #size-cells = <1>; | |
| 169 | ranges = <0xa8000000 0xa8000000 0x2000000>; | |
| 170 | ||
| 171 | dspif@a8000000 { | |
| 172 | compatible = "sirf,prima2-dspif"; | |
| 173 | reg = <0xa8000000 0x10000>; | |
| 174 | interrupts = <9>; | |
| 175 | }; | |
| 176 | ||
| 177 | gps@a8010000 { | |
| 178 | compatible = "sirf,prima2-gps"; | |
| 179 | reg = <0xa8010000 0x10000>; | |
| 180 | interrupts = <7>; | |
| eb8b8f2e | 181 | clocks = <&clks 9>; |
| 02c981c0 BD |
182 | }; |
| 183 | ||
| 184 | dsp@a9000000 { | |
| 185 | compatible = "sirf,prima2-dsp"; | |
| 186 | reg = <0xa9000000 0x1000000>; | |
| 187 | interrupts = <8>; | |
| eb8b8f2e | 188 | clocks = <&clks 8>; |
| 02c981c0 BD |
189 | }; |
| 190 | }; | |
| 191 | ||
| 192 | peri-iobg { | |
| 193 | compatible = "simple-bus"; | |
| 194 | #address-cells = <1>; | |
| 195 | #size-cells = <1>; | |
| 9e85b9d1 BS |
196 | ranges = <0xb0000000 0xb0000000 0x180000>, |
| 197 | <0x56000000 0x56000000 0x1b00000>; | |
| 02c981c0 BD |
198 | |
| 199 | timer@b0020000 { | |
| 200 | compatible = "sirf,prima2-tick"; | |
| 201 | reg = <0xb0020000 0x1000>; | |
| 202 | interrupts = <0>; | |
| 203 | }; | |
| 204 | ||
| 205 | nand@b0030000 { | |
| 206 | compatible = "sirf,prima2-nand"; | |
| 207 | reg = <0xb0030000 0x10000>; | |
| 208 | interrupts = <41>; | |
| eb8b8f2e | 209 | clocks = <&clks 26>; |
| 02c981c0 BD |
210 | }; |
| 211 | ||
| 212 | audio@b0040000 { | |
| 213 | compatible = "sirf,prima2-audio"; | |
| 214 | reg = <0xb0040000 0x10000>; | |
| 215 | interrupts = <35>; | |
| eb8b8f2e | 216 | clocks = <&clks 27>; |
| 02c981c0 BD |
217 | }; |
| 218 | ||
| 219 | uart0: uart@b0050000 { | |
| 220 | cell-index = <0>; | |
| 221 | compatible = "sirf,prima2-uart"; | |
| a1369978 | 222 | reg = <0xb0050000 0x1000>; |
| 02c981c0 | 223 | interrupts = <17>; |
| a1369978 | 224 | fifosize = <128>; |
| eb8b8f2e | 225 | clocks = <&clks 13>; |
| a1369978 QL |
226 | sirf,uart-dma-rx-channel = <21>; |
| 227 | sirf,uart-dma-tx-channel = <2>; | |
| 02c981c0 BD |
228 | }; |
| 229 | ||
| 230 | uart1: uart@b0060000 { | |
| 231 | cell-index = <1>; | |
| 232 | compatible = "sirf,prima2-uart"; | |
| a1369978 | 233 | reg = <0xb0060000 0x1000>; |
| 02c981c0 | 234 | interrupts = <18>; |
| a1369978 | 235 | fifosize = <32>; |
| eb8b8f2e | 236 | clocks = <&clks 14>; |
| 02c981c0 BD |
237 | }; |
| 238 | ||
| 239 | uart2: uart@b0070000 { | |
| 240 | cell-index = <2>; | |
| 241 | compatible = "sirf,prima2-uart"; | |
| a1369978 | 242 | reg = <0xb0070000 0x1000>; |
| 02c981c0 | 243 | interrupts = <19>; |
| a1369978 | 244 | fifosize = <128>; |
| eb8b8f2e | 245 | clocks = <&clks 15>; |
| a1369978 QL |
246 | sirf,uart-dma-rx-channel = <6>; |
| 247 | sirf,uart-dma-tx-channel = <7>; | |
| 02c981c0 BD |
248 | }; |
| 249 | ||
| 250 | usp0: usp@b0080000 { | |
| 251 | cell-index = <0>; | |
| 252 | compatible = "sirf,prima2-usp"; | |
| 253 | reg = <0xb0080000 0x10000>; | |
| 254 | interrupts = <20>; | |
| a1369978 | 255 | fifosize = <128>; |
| eb8b8f2e | 256 | clocks = <&clks 28>; |
| a1369978 QL |
257 | sirf,usp-dma-rx-channel = <17>; |
| 258 | sirf,usp-dma-tx-channel = <18>; | |
| 02c981c0 BD |
259 | }; |
| 260 | ||
| 261 | usp1: usp@b0090000 { | |
| 262 | cell-index = <1>; | |
| 263 | compatible = "sirf,prima2-usp"; | |
| 264 | reg = <0xb0090000 0x10000>; | |
| 265 | interrupts = <21>; | |
| a1369978 | 266 | fifosize = <128>; |
| eb8b8f2e | 267 | clocks = <&clks 29>; |
| a1369978 QL |
268 | sirf,usp-dma-rx-channel = <14>; |
| 269 | sirf,usp-dma-tx-channel = <15>; | |
| 02c981c0 BD |
270 | }; |
| 271 | ||
| 272 | usp2: usp@b00a0000 { | |
| 273 | cell-index = <2>; | |
| 274 | compatible = "sirf,prima2-usp"; | |
| 275 | reg = <0xb00a0000 0x10000>; | |
| 276 | interrupts = <22>; | |
| a1369978 | 277 | fifosize = <128>; |
| eb8b8f2e | 278 | clocks = <&clks 30>; |
| a1369978 QL |
279 | sirf,usp-dma-rx-channel = <10>; |
| 280 | sirf,usp-dma-tx-channel = <11>; | |
| 02c981c0 BD |
281 | }; |
| 282 | ||
| 283 | dmac0: dma-controller@b00b0000 { | |
| 284 | cell-index = <0>; | |
| 285 | compatible = "sirf,prima2-dmac"; | |
| 286 | reg = <0xb00b0000 0x10000>; | |
| 287 | interrupts = <12>; | |
| eb8b8f2e | 288 | clocks = <&clks 24>; |
| 02c981c0 BD |
289 | }; |
| 290 | ||
| 291 | dmac1: dma-controller@b0160000 { | |
| 292 | cell-index = <1>; | |
| 293 | compatible = "sirf,prima2-dmac"; | |
| 294 | reg = <0xb0160000 0x10000>; | |
| 295 | interrupts = <13>; | |
| eb8b8f2e | 296 | clocks = <&clks 25>; |
| 02c981c0 BD |
297 | }; |
| 298 | ||
| 299 | vip@b00C0000 { | |
| 300 | compatible = "sirf,prima2-vip"; | |
| 301 | reg = <0xb00C0000 0x10000>; | |
| eb8b8f2e | 302 | clocks = <&clks 31>; |
| 262bcc1d RW |
303 | interrupts = <14>; |
| 304 | sirf,vip-dma-rx-channel = <16>; | |
| 02c981c0 BD |
305 | }; |
| 306 | ||
| 307 | spi0: spi@b00d0000 { | |
| 308 | cell-index = <0>; | |
| 309 | compatible = "sirf,prima2-spi"; | |
| 310 | reg = <0xb00d0000 0x10000>; | |
| 311 | interrupts = <15>; | |
| 6f425115 BS |
312 | sirf,spi-num-chipselects = <1>; |
| 313 | sirf,spi-dma-rx-channel = <25>; | |
| 314 | sirf,spi-dma-tx-channel = <20>; | |
| 315 | #address-cells = <1>; | |
| 316 | #size-cells = <0>; | |
| eb8b8f2e | 317 | clocks = <&clks 19>; |
| 6f425115 | 318 | status = "disabled"; |
| 02c981c0 BD |
319 | }; |
| 320 | ||
| 321 | spi1: spi@b0170000 { | |
| 322 | cell-index = <1>; | |
| 323 | compatible = "sirf,prima2-spi"; | |
| 324 | reg = <0xb0170000 0x10000>; | |
| 325 | interrupts = <16>; | |
| 6f425115 BS |
326 | sirf,spi-num-chipselects = <1>; |
| 327 | sirf,spi-dma-rx-channel = <12>; | |
| 328 | sirf,spi-dma-tx-channel = <13>; | |
| 329 | #address-cells = <1>; | |
| 330 | #size-cells = <0>; | |
| eb8b8f2e | 331 | clocks = <&clks 20>; |
| 6f425115 | 332 | status = "disabled"; |
| 02c981c0 BD |
333 | }; |
| 334 | ||
| 335 | i2c0: i2c@b00e0000 { | |
| 336 | cell-index = <0>; | |
| 337 | compatible = "sirf,prima2-i2c"; | |
| 338 | reg = <0xb00e0000 0x10000>; | |
| 339 | interrupts = <24>; | |
| eb8b8f2e | 340 | clocks = <&clks 17>; |
| 7a54a4ba RW |
341 | #address-cells = <1>; |
| 342 | #size-cells = <0>; | |
| 02c981c0 BD |
343 | }; |
| 344 | ||
| 345 | i2c1: i2c@b00f0000 { | |
| 346 | cell-index = <1>; | |
| 347 | compatible = "sirf,prima2-i2c"; | |
| 348 | reg = <0xb00f0000 0x10000>; | |
| 349 | interrupts = <25>; | |
| eb8b8f2e | 350 | clocks = <&clks 18>; |
| 7a54a4ba RW |
351 | #address-cells = <1>; |
| 352 | #size-cells = <0>; | |
| 02c981c0 BD |
353 | }; |
| 354 | ||
| 355 | tsc@b0110000 { | |
| 356 | compatible = "sirf,prima2-tsc"; | |
| 357 | reg = <0xb0110000 0x10000>; | |
| 358 | interrupts = <33>; | |
| eb8b8f2e | 359 | clocks = <&clks 16>; |
| 02c981c0 BD |
360 | }; |
| 361 | ||
| 056876f6 | 362 | gpio: pinctrl@b0120000 { |
| 02c981c0 BD |
363 | #gpio-cells = <2>; |
| 364 | #interrupt-cells = <2>; | |
| 056876f6 | 365 | compatible = "sirf,prima2-pinctrl"; |
| 02c981c0 | 366 | reg = <0xb0120000 0x10000>; |
| 500b6ae3 | 367 | interrupts = <43 44 45 46 47>; |
| 02c981c0 BD |
368 | gpio-controller; |
| 369 | interrupt-controller; | |
| 056876f6 BS |
370 | |
| 371 | lcd_16pins_a: lcd0@0 { | |
| 372 | lcd { | |
| 373 | sirf,pins = "lcd_16bitsgrp"; | |
| 374 | sirf,function = "lcd_16bits"; | |
| 375 | }; | |
| 376 | }; | |
| 377 | lcd_18pins_a: lcd0@1 { | |
| 378 | lcd { | |
| 379 | sirf,pins = "lcd_18bitsgrp"; | |
| 380 | sirf,function = "lcd_18bits"; | |
| 381 | }; | |
| 382 | }; | |
| 383 | lcd_24pins_a: lcd0@2 { | |
| 384 | lcd { | |
| 385 | sirf,pins = "lcd_24bitsgrp"; | |
| 386 | sirf,function = "lcd_24bits"; | |
| 387 | }; | |
| 388 | }; | |
| 389 | lcdrom_pins_a: lcdrom0@0 { | |
| 390 | lcd { | |
| 391 | sirf,pins = "lcdromgrp"; | |
| 392 | sirf,function = "lcdrom"; | |
| 393 | }; | |
| 394 | }; | |
| 395 | uart0_pins_a: uart0@0 { | |
| 396 | uart { | |
| 397 | sirf,pins = "uart0grp"; | |
| 398 | sirf,function = "uart0"; | |
| 399 | }; | |
| 400 | }; | |
| fb85f429 QL |
401 | uart0_noflow_pins_a: uart0@1 { |
| 402 | uart { | |
| 403 | sirf,pins = "uart0_nostreamctrlgrp"; | |
| 404 | sirf,function = "uart0_nostreamctrl"; | |
| 405 | }; | |
| 406 | }; | |
| 056876f6 BS |
407 | uart1_pins_a: uart1@0 { |
| 408 | uart { | |
| 409 | sirf,pins = "uart1grp"; | |
| 410 | sirf,function = "uart1"; | |
| 411 | }; | |
| 412 | }; | |
| 413 | uart2_pins_a: uart2@0 { | |
| 414 | uart { | |
| 415 | sirf,pins = "uart2grp"; | |
| 416 | sirf,function = "uart2"; | |
| 417 | }; | |
| 418 | }; | |
| 419 | uart2_noflow_pins_a: uart2@1 { | |
| 420 | uart { | |
| 421 | sirf,pins = "uart2_nostreamctrlgrp"; | |
| 422 | sirf,function = "uart2_nostreamctrl"; | |
| 423 | }; | |
| 424 | }; | |
| 425 | spi0_pins_a: spi0@0 { | |
| 426 | spi { | |
| 427 | sirf,pins = "spi0grp"; | |
| 428 | sirf,function = "spi0"; | |
| 429 | }; | |
| 430 | }; | |
| 431 | spi1_pins_a: spi1@0 { | |
| 432 | spi { | |
| 433 | sirf,pins = "spi1grp"; | |
| 434 | sirf,function = "spi1"; | |
| 435 | }; | |
| 436 | }; | |
| 437 | i2c0_pins_a: i2c0@0 { | |
| 438 | i2c { | |
| 439 | sirf,pins = "i2c0grp"; | |
| 440 | sirf,function = "i2c0"; | |
| 441 | }; | |
| 442 | }; | |
| 443 | i2c1_pins_a: i2c1@0 { | |
| 444 | i2c { | |
| 445 | sirf,pins = "i2c1grp"; | |
| 446 | sirf,function = "i2c1"; | |
| 447 | }; | |
| 448 | }; | |
| 449 | pwm0_pins_a: pwm0@0 { | |
| 450 | pwm { | |
| 451 | sirf,pins = "pwm0grp"; | |
| 452 | sirf,function = "pwm0"; | |
| 453 | }; | |
| 454 | }; | |
| 455 | pwm1_pins_a: pwm1@0 { | |
| 456 | pwm { | |
| 457 | sirf,pins = "pwm1grp"; | |
| 458 | sirf,function = "pwm1"; | |
| 459 | }; | |
| 460 | }; | |
| 461 | pwm2_pins_a: pwm2@0 { | |
| 462 | pwm { | |
| 463 | sirf,pins = "pwm2grp"; | |
| 464 | sirf,function = "pwm2"; | |
| 465 | }; | |
| 466 | }; | |
| 467 | pwm3_pins_a: pwm3@0 { | |
| 468 | pwm { | |
| 469 | sirf,pins = "pwm3grp"; | |
| 470 | sirf,function = "pwm3"; | |
| 471 | }; | |
| 472 | }; | |
| 473 | gps_pins_a: gps@0 { | |
| 474 | gps { | |
| 475 | sirf,pins = "gpsgrp"; | |
| 476 | sirf,function = "gps"; | |
| 477 | }; | |
| 478 | }; | |
| 479 | vip_pins_a: vip@0 { | |
| 480 | vip { | |
| 481 | sirf,pins = "vipgrp"; | |
| 482 | sirf,function = "vip"; | |
| 483 | }; | |
| 484 | }; | |
| 485 | sdmmc0_pins_a: sdmmc0@0 { | |
| 486 | sdmmc0 { | |
| 487 | sirf,pins = "sdmmc0grp"; | |
| 488 | sirf,function = "sdmmc0"; | |
| 489 | }; | |
| 490 | }; | |
| 491 | sdmmc1_pins_a: sdmmc1@0 { | |
| 492 | sdmmc1 { | |
| 493 | sirf,pins = "sdmmc1grp"; | |
| 494 | sirf,function = "sdmmc1"; | |
| 495 | }; | |
| 496 | }; | |
| 497 | sdmmc2_pins_a: sdmmc2@0 { | |
| 498 | sdmmc2 { | |
| 499 | sirf,pins = "sdmmc2grp"; | |
| 500 | sirf,function = "sdmmc2"; | |
| 501 | }; | |
| 502 | }; | |
| 503 | sdmmc3_pins_a: sdmmc3@0 { | |
| 504 | sdmmc3 { | |
| 505 | sirf,pins = "sdmmc3grp"; | |
| 506 | sirf,function = "sdmmc3"; | |
| 507 | }; | |
| 508 | }; | |
| 509 | sdmmc4_pins_a: sdmmc4@0 { | |
| 510 | sdmmc4 { | |
| 511 | sirf,pins = "sdmmc4grp"; | |
| 512 | sirf,function = "sdmmc4"; | |
| 513 | }; | |
| 514 | }; | |
| 515 | sdmmc5_pins_a: sdmmc5@0 { | |
| 516 | sdmmc5 { | |
| 517 | sirf,pins = "sdmmc5grp"; | |
| 518 | sirf,function = "sdmmc5"; | |
| 519 | }; | |
| 520 | }; | |
| 521 | i2s_pins_a: i2s@0 { | |
| 522 | i2s { | |
| 523 | sirf,pins = "i2sgrp"; | |
| 524 | sirf,function = "i2s"; | |
| 525 | }; | |
| 526 | }; | |
| 527 | ac97_pins_a: ac97@0 { | |
| 528 | ac97 { | |
| 529 | sirf,pins = "ac97grp"; | |
| 530 | sirf,function = "ac97"; | |
| 531 | }; | |
| 532 | }; | |
| 533 | nand_pins_a: nand@0 { | |
| 534 | nand { | |
| 535 | sirf,pins = "nandgrp"; | |
| 536 | sirf,function = "nand"; | |
| 537 | }; | |
| 538 | }; | |
| 539 | usp0_pins_a: usp0@0 { | |
| 540 | usp0 { | |
| 541 | sirf,pins = "usp0grp"; | |
| 542 | sirf,function = "usp0"; | |
| 543 | }; | |
| 544 | }; | |
| af614b23 QL |
545 | usp0_uart_nostreamctrl_pins_a: usp0@1 { |
| 546 | usp0 { | |
| 547 | sirf,pins = | |
| 548 | "usp0_uart_nostreamctrl_grp"; | |
| 549 | sirf,function = | |
| 550 | "usp0_uart_nostreamctrl"; | |
| 551 | }; | |
| 552 | }; | |
| 056876f6 BS |
553 | usp1_pins_a: usp1@0 { |
| 554 | usp1 { | |
| 555 | sirf,pins = "usp1grp"; | |
| 556 | sirf,function = "usp1"; | |
| 557 | }; | |
| 558 | }; | |
| af614b23 QL |
559 | usp1_uart_nostreamctrl_pins_a: usp1@1 { |
| 560 | usp1 { | |
| 561 | sirf,pins = | |
| 562 | "usp1_uart_nostreamctrl_grp"; | |
| 563 | sirf,function = | |
| 564 | "usp1_uart_nostreamctrl"; | |
| 565 | }; | |
| 566 | }; | |
| 056876f6 BS |
567 | usp2_pins_a: usp2@0 { |
| 568 | usp2 { | |
| 569 | sirf,pins = "usp2grp"; | |
| 570 | sirf,function = "usp2"; | |
| 571 | }; | |
| 572 | }; | |
| af614b23 QL |
573 | usp2_uart_nostreamctrl_pins_a: usp2@1 { |
| 574 | usp2 { | |
| 575 | sirf,pins = | |
| 576 | "usp2_uart_nostreamctrl_grp"; | |
| 577 | sirf,function = | |
| 578 | "usp2_uart_nostreamctrl"; | |
| 579 | }; | |
| 580 | }; | |
| 056876f6 BS |
581 | usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { |
| 582 | usb0_utmi_drvbus { | |
| 583 | sirf,pins = "usb0_utmi_drvbusgrp"; | |
| 584 | sirf,function = "usb0_utmi_drvbus"; | |
| 585 | }; | |
| 586 | }; | |
| 587 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | |
| 588 | usb1_utmi_drvbus { | |
| 589 | sirf,pins = "usb1_utmi_drvbusgrp"; | |
| 590 | sirf,function = "usb1_utmi_drvbus"; | |
| 591 | }; | |
| 592 | }; | |
| 6a08a92e RW |
593 | usb1_dp_dn_pins_a: usb1_dp_dn@0 { |
| 594 | usb1_dp_dn { | |
| 595 | sirf,pins = "usb1_dp_dngrp"; | |
| 596 | sirf,function = "usb1_dp_dn"; | |
| 597 | }; | |
| 598 | }; | |
| 599 | uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { | |
| 600 | uart1_route_io_usb1 { | |
| 601 | sirf,pins = "uart1_route_io_usb1grp"; | |
| 602 | sirf,function = "uart1_route_io_usb1"; | |
| 603 | }; | |
| 604 | }; | |
| 056876f6 BS |
605 | warm_rst_pins_a: warm_rst@0 { |
| 606 | warm_rst { | |
| 607 | sirf,pins = "warm_rstgrp"; | |
| 608 | sirf,function = "warm_rst"; | |
| 609 | }; | |
| 610 | }; | |
| 611 | pulse_count_pins_a: pulse_count@0 { | |
| 612 | pulse_count { | |
| 613 | sirf,pins = "pulse_countgrp"; | |
| 614 | sirf,function = "pulse_count"; | |
| 615 | }; | |
| 616 | }; | |
| c8078de8 BS |
617 | cko0_pins_a: cko0@0 { |
| 618 | cko0 { | |
| 619 | sirf,pins = "cko0grp"; | |
| 620 | sirf,function = "cko0"; | |
| 056876f6 BS |
621 | }; |
| 622 | }; | |
| c8078de8 BS |
623 | cko1_pins_a: cko1@0 { |
| 624 | cko1 { | |
| 625 | sirf,pins = "cko1grp"; | |
| 626 | sirf,function = "cko1"; | |
| 056876f6 BS |
627 | }; |
| 628 | }; | |
| 02c981c0 BD |
629 | }; |
| 630 | ||
| 631 | pwm@b0130000 { | |
| 632 | compatible = "sirf,prima2-pwm"; | |
| 633 | reg = <0xb0130000 0x10000>; | |
| eb8b8f2e | 634 | clocks = <&clks 21>; |
| 02c981c0 BD |
635 | }; |
| 636 | ||
| 637 | efusesys@b0140000 { | |
| 638 | compatible = "sirf,prima2-efuse"; | |
| 639 | reg = <0xb0140000 0x10000>; | |
| eb8b8f2e | 640 | clocks = <&clks 22>; |
| 02c981c0 BD |
641 | }; |
| 642 | ||
| 643 | pulsec@b0150000 { | |
| 644 | compatible = "sirf,prima2-pulsec"; | |
| 645 | reg = <0xb0150000 0x10000>; | |
| 646 | interrupts = <48>; | |
| eb8b8f2e | 647 | clocks = <&clks 23>; |
| 02c981c0 BD |
648 | }; |
| 649 | ||
| 650 | pci-iobg { | |
| 651 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | |
| 652 | #address-cells = <1>; | |
| 653 | #size-cells = <1>; | |
| 654 | ranges = <0x56000000 0x56000000 0x1b00000>; | |
| 655 | ||
| 656 | sd0: sdhci@56000000 { | |
| 657 | cell-index = <0>; | |
| 658 | compatible = "sirf,prima2-sdhc"; | |
| 659 | reg = <0x56000000 0x100000>; | |
| 660 | interrupts = <38>; | |
| 7f97c303 BS |
661 | status = "disabled"; |
| 662 | bus-width = <8>; | |
| 663 | clocks = <&clks 36>; | |
| 02c981c0 BD |
664 | }; |
| 665 | ||
| 666 | sd1: sdhci@56100000 { | |
| 667 | cell-index = <1>; | |
| 668 | compatible = "sirf,prima2-sdhc"; | |
| 669 | reg = <0x56100000 0x100000>; | |
| 670 | interrupts = <38>; | |
| 7f97c303 BS |
671 | status = "disabled"; |
| 672 | bus-width = <4>; | |
| 673 | clocks = <&clks 36>; | |
| 02c981c0 BD |
674 | }; |
| 675 | ||
| 676 | sd2: sdhci@56200000 { | |
| 677 | cell-index = <2>; | |
| 678 | compatible = "sirf,prima2-sdhc"; | |
| 679 | reg = <0x56200000 0x100000>; | |
| 680 | interrupts = <23>; | |
| 7f97c303 BS |
681 | status = "disabled"; |
| 682 | clocks = <&clks 37>; | |
| 02c981c0 BD |
683 | }; |
| 684 | ||
| 685 | sd3: sdhci@56300000 { | |
| 686 | cell-index = <3>; | |
| 687 | compatible = "sirf,prima2-sdhc"; | |
| 688 | reg = <0x56300000 0x100000>; | |
| 689 | interrupts = <23>; | |
| 7f97c303 BS |
690 | status = "disabled"; |
| 691 | clocks = <&clks 37>; | |
| 02c981c0 BD |
692 | }; |
| 693 | ||
| 694 | sd4: sdhci@56400000 { | |
| 695 | cell-index = <4>; | |
| 696 | compatible = "sirf,prima2-sdhc"; | |
| 697 | reg = <0x56400000 0x100000>; | |
| 698 | interrupts = <39>; | |
| 7f97c303 BS |
699 | status = "disabled"; |
| 700 | clocks = <&clks 38>; | |
| 02c981c0 BD |
701 | }; |
| 702 | ||
| 703 | sd5: sdhci@56500000 { | |
| 704 | cell-index = <5>; | |
| 705 | compatible = "sirf,prima2-sdhc"; | |
| 706 | reg = <0x56500000 0x100000>; | |
| 707 | interrupts = <39>; | |
| 7f97c303 | 708 | clocks = <&clks 38>; |
| 02c981c0 BD |
709 | }; |
| 710 | ||
| 711 | pci-copy@57900000 { | |
| 712 | compatible = "sirf,prima2-pcicp"; | |
| 713 | reg = <0x57900000 0x100000>; | |
| 714 | interrupts = <40>; | |
| 715 | }; | |
| 716 | ||
| 717 | rom-interface@57a00000 { | |
| 718 | compatible = "sirf,prima2-romif"; | |
| 719 | reg = <0x57a00000 0x100000>; | |
| 720 | }; | |
| 721 | }; | |
| 722 | }; | |
| 723 | ||
| 724 | rtc-iobg { | |
| e88b815e | 725 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; |
| 02c981c0 BD |
726 | #address-cells = <1>; |
| 727 | #size-cells = <1>; | |
| 728 | reg = <0x80030000 0x10000>; | |
| 729 | ||
| 730 | gpsrtc@1000 { | |
| 731 | compatible = "sirf,prima2-gpsrtc"; | |
| 732 | reg = <0x1000 0x1000>; | |
| 733 | interrupts = <55 56 57>; | |
| 734 | }; | |
| 735 | ||
| 736 | sysrtc@2000 { | |
| 737 | compatible = "sirf,prima2-sysrtc"; | |
| 738 | reg = <0x2000 0x1000>; | |
| 739 | interrupts = <52 53 54>; | |
| 740 | }; | |
| 741 | ||
| 423ef791 XD |
742 | minigpsrtc@2000 { |
| 743 | compatible = "sirf,prima2-minigpsrtc"; | |
| 744 | reg = <0x2000 0x1000>; | |
| 745 | interrupts = <54>; | |
| 746 | }; | |
| 747 | ||
| 02c981c0 BD |
748 | pwrc@3000 { |
| 749 | compatible = "sirf,prima2-pwrc"; | |
| 750 | reg = <0x3000 0x1000>; | |
| 751 | interrupts = <32>; | |
| 752 | }; | |
| 753 | }; | |
| 754 | ||
| 755 | uus-iobg { | |
| 756 | compatible = "simple-bus"; | |
| 757 | #address-cells = <1>; | |
| 758 | #size-cells = <1>; | |
| 759 | ranges = <0xb8000000 0xb8000000 0x40000>; | |
| 760 | ||
| 761 | usb0: usb@b00e0000 { | |
| 762 | compatible = "chipidea,ci13611a-prima2"; | |
| 763 | reg = <0xb8000000 0x10000>; | |
| 764 | interrupts = <10>; | |
| eb8b8f2e | 765 | clocks = <&clks 40>; |
| 02c981c0 BD |
766 | }; |
| 767 | ||
| 768 | usb1: usb@b00f0000 { | |
| 769 | compatible = "chipidea,ci13611a-prima2"; | |
| 770 | reg = <0xb8010000 0x10000>; | |
| 771 | interrupts = <11>; | |
| eb8b8f2e | 772 | clocks = <&clks 41>; |
| 02c981c0 BD |
773 | }; |
| 774 | ||
| 775 | sata@b00f0000 { | |
| 776 | compatible = "synopsys,dwc-ahsata"; | |
| 777 | reg = <0xb8020000 0x10000>; | |
| 778 | interrupts = <37>; | |
| 779 | }; | |
| 780 | ||
| 781 | security@b00f0000 { | |
| 782 | compatible = "sirf,prima2-security"; | |
| 783 | reg = <0xb8030000 0x10000>; | |
| 784 | interrupts = <42>; | |
| eb8b8f2e | 785 | clocks = <&clks 7>; |
| 02c981c0 BD |
786 | }; |
| 787 | }; | |
| 788 | }; | |
| 789 | }; |