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ff290fc3 HZ |
1 | /* |
2 | * Copyright (C) 2012 Marvell Technology Group Ltd. | |
3 | * Author: Haojian Zhuang <haojian.zhuang@marvell.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * publishhed by the Free Software Foundation. | |
8 | */ | |
9 | ||
51454eb4 | 10 | #include "skeleton.dtsi" |
d41ef540 | 11 | #include <dt-bindings/clock/marvell,pxa910.h> |
ff290fc3 HZ |
12 | |
13 | / { | |
14 | aliases { | |
15 | serial0 = &uart1; | |
16 | serial1 = &uart2; | |
17 | serial2 = &uart3; | |
18 | i2c0 = &twsi1; | |
19 | i2c1 = &twsi2; | |
20 | }; | |
21 | ||
22 | soc { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <1>; | |
25 | compatible = "simple-bus"; | |
26 | interrupt-parent = <&intc>; | |
27 | ranges; | |
28 | ||
a03d8b1e HZ |
29 | L2: l2-cache { |
30 | compatible = "marvell,tauros2-cache"; | |
31 | marvell,tauros2-cache-features = <0x3>; | |
32 | }; | |
33 | ||
ff290fc3 HZ |
34 | axi@d4200000 { /* AXI */ |
35 | compatible = "mrvl,axi-bus", "simple-bus"; | |
36 | #address-cells = <1>; | |
37 | #size-cells = <1>; | |
38 | reg = <0xd4200000 0x00200000>; | |
39 | ranges; | |
40 | ||
41 | intc: interrupt-controller@d4282000 { | |
42 | compatible = "mrvl,mmp-intc"; | |
43 | interrupt-controller; | |
44 | #interrupt-cells = <1>; | |
45 | reg = <0xd4282000 0x1000>; | |
46 | mrvl,intc-nr-irqs = <64>; | |
47 | }; | |
48 | ||
49 | }; | |
50 | ||
51 | apb@d4000000 { /* APB */ | |
52 | compatible = "mrvl,apb-bus", "simple-bus"; | |
53 | #address-cells = <1>; | |
54 | #size-cells = <1>; | |
55 | reg = <0xd4000000 0x00200000>; | |
56 | ranges; | |
57 | ||
58 | timer0: timer@d4014000 { | |
59 | compatible = "mrvl,mmp-timer"; | |
60 | reg = <0xd4014000 0x100>; | |
61 | interrupts = <13>; | |
62 | }; | |
63 | ||
64 | timer1: timer@d4016000 { | |
65 | compatible = "mrvl,mmp-timer"; | |
66 | reg = <0xd4016000 0x100>; | |
67 | interrupts = <29>; | |
68 | status = "disabled"; | |
69 | }; | |
70 | ||
71 | uart1: uart@d4017000 { | |
72 | compatible = "mrvl,mmp-uart"; | |
73 | reg = <0xd4017000 0x1000>; | |
74 | interrupts = <27>; | |
d41ef540 CX |
75 | clocks = <&soc_clocks PXA910_CLK_UART0>; |
76 | resets = <&soc_clocks PXA910_CLK_UART0>; | |
ff290fc3 HZ |
77 | status = "disabled"; |
78 | }; | |
79 | ||
80 | uart2: uart@d4018000 { | |
81 | compatible = "mrvl,mmp-uart"; | |
82 | reg = <0xd4018000 0x1000>; | |
83 | interrupts = <28>; | |
d41ef540 CX |
84 | clocks = <&soc_clocks PXA910_CLK_UART1>; |
85 | resets = <&soc_clocks PXA910_CLK_UART1>; | |
ff290fc3 HZ |
86 | status = "disabled"; |
87 | }; | |
88 | ||
89 | uart3: uart@d4036000 { | |
90 | compatible = "mrvl,mmp-uart"; | |
91 | reg = <0xd4036000 0x1000>; | |
92 | interrupts = <59>; | |
d41ef540 CX |
93 | clocks = <&soc_clocks PXA910_CLK_UART2>; |
94 | resets = <&soc_clocks PXA910_CLK_UART2>; | |
ff290fc3 HZ |
95 | status = "disabled"; |
96 | }; | |
97 | ||
98 | gpio@d4019000 { | |
f8731174 | 99 | compatible = "marvell,mmp-gpio"; |
ff290fc3 HZ |
100 | #address-cells = <1>; |
101 | #size-cells = <1>; | |
102 | reg = <0xd4019000 0x1000>; | |
103 | gpio-controller; | |
104 | #gpio-cells = <2>; | |
105 | interrupts = <49>; | |
106 | interrupt-names = "gpio_mux"; | |
d41ef540 CX |
107 | clocks = <&soc_clocks PXA910_CLK_GPIO>; |
108 | resets = <&soc_clocks PXA910_CLK_GPIO>; | |
ff290fc3 HZ |
109 | interrupt-controller; |
110 | #interrupt-cells = <1>; | |
111 | ranges; | |
112 | ||
113 | gcb0: gpio@d4019000 { | |
114 | reg = <0xd4019000 0x4>; | |
115 | }; | |
116 | ||
117 | gcb1: gpio@d4019004 { | |
118 | reg = <0xd4019004 0x4>; | |
119 | }; | |
120 | ||
121 | gcb2: gpio@d4019008 { | |
122 | reg = <0xd4019008 0x4>; | |
123 | }; | |
124 | ||
125 | gcb3: gpio@d4019100 { | |
126 | reg = <0xd4019100 0x4>; | |
127 | }; | |
128 | }; | |
129 | ||
130 | twsi1: i2c@d4011000 { | |
131 | compatible = "mrvl,mmp-twsi"; | |
74d83781 HZ |
132 | #address-cells = <1>; |
133 | #size-cells = <0>; | |
ff290fc3 HZ |
134 | reg = <0xd4011000 0x1000>; |
135 | interrupts = <7>; | |
d41ef540 CX |
136 | clocks = <&soc_clocks PXA910_CLK_TWSI0>; |
137 | resets = <&soc_clocks PXA910_CLK_TWSI0>; | |
ff290fc3 HZ |
138 | mrvl,i2c-fast-mode; |
139 | status = "disabled"; | |
140 | }; | |
141 | ||
142 | twsi2: i2c@d4037000 { | |
143 | compatible = "mrvl,mmp-twsi"; | |
74d83781 HZ |
144 | #address-cells = <1>; |
145 | #size-cells = <0>; | |
ff290fc3 HZ |
146 | reg = <0xd4037000 0x1000>; |
147 | interrupts = <54>; | |
d41ef540 CX |
148 | clocks = <&soc_clocks PXA910_CLK_TWSI1>; |
149 | resets = <&soc_clocks PXA910_CLK_TWSI1>; | |
ff290fc3 HZ |
150 | status = "disabled"; |
151 | }; | |
152 | ||
153 | rtc: rtc@d4010000 { | |
154 | compatible = "mrvl,mmp-rtc"; | |
155 | reg = <0xd4010000 0x1000>; | |
156 | interrupts = <5 6>; | |
157 | interrupt-names = "rtc 1Hz", "rtc alarm"; | |
d41ef540 CX |
158 | clocks = <&soc_clocks PXA910_CLK_RTC>; |
159 | resets = <&soc_clocks PXA910_CLK_RTC>; | |
ff290fc3 HZ |
160 | status = "disabled"; |
161 | }; | |
162 | }; | |
d41ef540 CX |
163 | |
164 | soc_clocks: clocks{ | |
165 | compatible = "marvell,pxa910-clock"; | |
166 | reg = <0xd4050000 0x1000>, | |
167 | <0xd4282800 0x400>, | |
168 | <0xd4015000 0x1000>, | |
169 | <0xd403b000 0x1000>; | |
170 | reg-names = "mpmu", "apmu", "apbc", "apbcp"; | |
171 | #clock-cells = <1>; | |
172 | #reset-cells = <1>; | |
173 | }; | |
ff290fc3 HZ |
174 | }; |
175 | }; |