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Commit | Line | Data |
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f335b8af KG |
1 | /dts-v1/; |
2 | ||
3 | #include "skeleton.dtsi" | |
4 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | |
3fe5e3ce | 5 | #include <dt-bindings/clock/qcom,mmcc-msm8960.h> |
f335b8af | 6 | #include <dt-bindings/soc/qcom,gsbi.h> |
8b8936fc | 7 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
f335b8af KG |
8 | |
9 | / { | |
10 | model = "Qualcomm APQ8064"; | |
11 | compatible = "qcom,apq8064"; | |
12 | interrupt-parent = <&intc>; | |
13 | ||
14 | cpus { | |
15 | #address-cells = <1>; | |
16 | #size-cells = <0>; | |
17 | ||
18 | cpu@0 { | |
19 | compatible = "qcom,krait"; | |
20 | enable-method = "qcom,kpss-acc-v1"; | |
21 | device_type = "cpu"; | |
22 | reg = <0>; | |
23 | next-level-cache = <&L2>; | |
24 | qcom,acc = <&acc0>; | |
25 | qcom,saw = <&saw0>; | |
26 | }; | |
27 | ||
28 | cpu@1 { | |
29 | compatible = "qcom,krait"; | |
30 | enable-method = "qcom,kpss-acc-v1"; | |
31 | device_type = "cpu"; | |
32 | reg = <1>; | |
33 | next-level-cache = <&L2>; | |
34 | qcom,acc = <&acc1>; | |
35 | qcom,saw = <&saw1>; | |
36 | }; | |
37 | ||
38 | cpu@2 { | |
39 | compatible = "qcom,krait"; | |
40 | enable-method = "qcom,kpss-acc-v1"; | |
41 | device_type = "cpu"; | |
42 | reg = <2>; | |
43 | next-level-cache = <&L2>; | |
44 | qcom,acc = <&acc2>; | |
45 | qcom,saw = <&saw2>; | |
46 | }; | |
47 | ||
48 | cpu@3 { | |
49 | compatible = "qcom,krait"; | |
50 | enable-method = "qcom,kpss-acc-v1"; | |
51 | device_type = "cpu"; | |
52 | reg = <3>; | |
53 | next-level-cache = <&L2>; | |
54 | qcom,acc = <&acc3>; | |
55 | qcom,saw = <&saw3>; | |
56 | }; | |
57 | ||
58 | L2: l2-cache { | |
59 | compatible = "cache"; | |
60 | cache-level = <2>; | |
61 | }; | |
62 | }; | |
63 | ||
64 | cpu-pmu { | |
65 | compatible = "qcom,krait-pmu"; | |
66 | interrupts = <1 10 0x304>; | |
67 | }; | |
68 | ||
69 | soc: soc { | |
70 | #address-cells = <1>; | |
71 | #size-cells = <1>; | |
72 | ranges; | |
73 | compatible = "simple-bus"; | |
74 | ||
8b8936fc PG |
75 | tlmm_pinmux: pinctrl@800000 { |
76 | compatible = "qcom,apq8064-pinctrl"; | |
77 | reg = <0x800000 0x4000>; | |
78 | ||
79 | gpio-controller; | |
80 | #gpio-cells = <2>; | |
81 | interrupt-controller; | |
82 | #interrupt-cells = <2>; | |
83 | interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; | |
cd6dd11a PG |
84 | |
85 | pinctrl-names = "default"; | |
86 | pinctrl-0 = <&ps_hold>; | |
87 | ||
0be5fef1 SK |
88 | sdc4_gpios: sdc4-gpios { |
89 | pios { | |
90 | pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; | |
91 | function = "sdc4"; | |
92 | }; | |
93 | }; | |
94 | ||
cd6dd11a PG |
95 | ps_hold: ps_hold { |
96 | mux { | |
97 | pins = "gpio78"; | |
98 | function = "ps_hold"; | |
99 | }; | |
100 | }; | |
8b8936fc PG |
101 | }; |
102 | ||
f335b8af KG |
103 | intc: interrupt-controller@2000000 { |
104 | compatible = "qcom,msm-qgic2"; | |
105 | interrupt-controller; | |
106 | #interrupt-cells = <3>; | |
107 | reg = <0x02000000 0x1000>, | |
108 | <0x02002000 0x1000>; | |
109 | }; | |
110 | ||
111 | timer@200a000 { | |
112 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | |
113 | interrupts = <1 1 0x301>, | |
114 | <1 2 0x301>, | |
115 | <1 3 0x301>; | |
116 | reg = <0x0200a000 0x100>; | |
117 | clock-frequency = <27000000>, | |
118 | <32768>; | |
119 | cpu-offset = <0x80000>; | |
120 | }; | |
121 | ||
122 | acc0: clock-controller@2088000 { | |
123 | compatible = "qcom,kpss-acc-v1"; | |
124 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | |
125 | }; | |
126 | ||
127 | acc1: clock-controller@2098000 { | |
128 | compatible = "qcom,kpss-acc-v1"; | |
129 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | |
130 | }; | |
131 | ||
132 | acc2: clock-controller@20a8000 { | |
133 | compatible = "qcom,kpss-acc-v1"; | |
134 | reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; | |
135 | }; | |
136 | ||
137 | acc3: clock-controller@20b8000 { | |
138 | compatible = "qcom,kpss-acc-v1"; | |
139 | reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; | |
140 | }; | |
141 | ||
142 | saw0: regulator@2089000 { | |
143 | compatible = "qcom,saw2"; | |
144 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; | |
145 | regulator; | |
146 | }; | |
147 | ||
148 | saw1: regulator@2099000 { | |
149 | compatible = "qcom,saw2"; | |
150 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; | |
151 | regulator; | |
152 | }; | |
153 | ||
154 | saw2: regulator@20a9000 { | |
155 | compatible = "qcom,saw2"; | |
156 | reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; | |
157 | regulator; | |
158 | }; | |
159 | ||
160 | saw3: regulator@20b9000 { | |
161 | compatible = "qcom,saw2"; | |
162 | reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; | |
163 | regulator; | |
164 | }; | |
165 | ||
8c3166f5 | 166 | gsbi1: gsbi@12440000 { |
167 | status = "disabled"; | |
168 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 169 | cell-index = <1>; |
8c3166f5 | 170 | reg = <0x12440000 0x100>; |
171 | clocks = <&gcc GSBI1_H_CLK>; | |
172 | clock-names = "iface"; | |
173 | #address-cells = <1>; | |
174 | #size-cells = <1>; | |
175 | ranges; | |
176 | ||
4105d9d6 AG |
177 | syscon-tcsr = <&tcsr>; |
178 | ||
8c3166f5 | 179 | i2c1: i2c@12460000 { |
180 | compatible = "qcom,i2c-qup-v1.1.1"; | |
181 | reg = <0x12460000 0x1000>; | |
182 | interrupts = <0 194 IRQ_TYPE_NONE>; | |
183 | clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; | |
184 | clock-names = "core", "iface"; | |
185 | #address-cells = <1>; | |
186 | #size-cells = <0>; | |
187 | }; | |
188 | }; | |
189 | ||
190 | gsbi2: gsbi@12480000 { | |
191 | status = "disabled"; | |
192 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 193 | cell-index = <2>; |
8c3166f5 | 194 | reg = <0x12480000 0x100>; |
195 | clocks = <&gcc GSBI2_H_CLK>; | |
196 | clock-names = "iface"; | |
197 | #address-cells = <1>; | |
198 | #size-cells = <1>; | |
199 | ranges; | |
200 | ||
4105d9d6 AG |
201 | syscon-tcsr = <&tcsr>; |
202 | ||
8c3166f5 | 203 | i2c2: i2c@124a0000 { |
204 | compatible = "qcom,i2c-qup-v1.1.1"; | |
205 | reg = <0x124a0000 0x1000>; | |
206 | interrupts = <0 196 IRQ_TYPE_NONE>; | |
207 | clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; | |
208 | clock-names = "core", "iface"; | |
209 | #address-cells = <1>; | |
210 | #size-cells = <0>; | |
211 | }; | |
212 | }; | |
213 | ||
f335b8af KG |
214 | gsbi7: gsbi@16600000 { |
215 | status = "disabled"; | |
216 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 217 | cell-index = <7>; |
f335b8af KG |
218 | reg = <0x16600000 0x100>; |
219 | clocks = <&gcc GSBI7_H_CLK>; | |
220 | clock-names = "iface"; | |
221 | #address-cells = <1>; | |
222 | #size-cells = <1>; | |
223 | ranges; | |
224 | ||
4105d9d6 AG |
225 | syscon-tcsr = <&tcsr>; |
226 | ||
f335b8af KG |
227 | serial@16640000 { |
228 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
229 | reg = <0x16640000 0x1000>, | |
230 | <0x16600000 0x1000>; | |
231 | interrupts = <0 158 0x0>; | |
232 | clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; | |
233 | clock-names = "core", "iface"; | |
234 | status = "disabled"; | |
235 | }; | |
236 | }; | |
237 | ||
238 | qcom,ssbi@500000 { | |
239 | compatible = "qcom,ssbi"; | |
240 | reg = <0x00500000 0x1000>; | |
241 | qcom,controller-type = "pmic-arbiter"; | |
242 | }; | |
243 | ||
244 | gcc: clock-controller@900000 { | |
245 | compatible = "qcom,gcc-apq8064"; | |
246 | reg = <0x00900000 0x4000>; | |
247 | #clock-cells = <1>; | |
248 | #reset-cells = <1>; | |
249 | }; | |
3fe5e3ce SB |
250 | |
251 | mmcc: clock-controller@4000000 { | |
252 | compatible = "qcom,mmcc-apq8064"; | |
253 | reg = <0x4000000 0x1000>; | |
254 | #clock-cells = <1>; | |
255 | #reset-cells = <1>; | |
256 | }; | |
045644ff SK |
257 | |
258 | /* Temporary fixed regulator */ | |
259 | vsdcc_fixed: vsdcc-regulator { | |
260 | compatible = "regulator-fixed"; | |
261 | regulator-name = "SDCC Power"; | |
262 | regulator-min-microvolt = <2700000>; | |
263 | regulator-max-microvolt = <2700000>; | |
264 | regulator-always-on; | |
265 | }; | |
266 | ||
edb81ca3 SK |
267 | sdcc1bam:dma@12402000{ |
268 | compatible = "qcom,bam-v1.3.0"; | |
269 | reg = <0x12402000 0x8000>; | |
270 | interrupts = <0 98 0>; | |
271 | clocks = <&gcc SDC1_H_CLK>; | |
272 | clock-names = "bam_clk"; | |
273 | #dma-cells = <1>; | |
274 | qcom,ee = <0>; | |
275 | }; | |
276 | ||
277 | sdcc3bam:dma@12182000{ | |
278 | compatible = "qcom,bam-v1.3.0"; | |
279 | reg = <0x12182000 0x8000>; | |
280 | interrupts = <0 96 0>; | |
281 | clocks = <&gcc SDC3_H_CLK>; | |
282 | clock-names = "bam_clk"; | |
283 | #dma-cells = <1>; | |
284 | qcom,ee = <0>; | |
285 | }; | |
286 | ||
0be5fef1 SK |
287 | sdcc4bam:dma@121c2000{ |
288 | compatible = "qcom,bam-v1.3.0"; | |
289 | reg = <0x121c2000 0x8000>; | |
290 | interrupts = <0 95 0>; | |
291 | clocks = <&gcc SDC4_H_CLK>; | |
292 | clock-names = "bam_clk"; | |
293 | #dma-cells = <1>; | |
294 | qcom,ee = <0>; | |
295 | }; | |
296 | ||
045644ff SK |
297 | amba { |
298 | compatible = "arm,amba-bus"; | |
299 | #address-cells = <1>; | |
300 | #size-cells = <1>; | |
301 | ranges; | |
302 | sdcc1: sdcc@12400000 { | |
303 | status = "disabled"; | |
304 | compatible = "arm,pl18x", "arm,primecell"; | |
305 | arm,primecell-periphid = <0x00051180>; | |
306 | reg = <0x12400000 0x2000>; | |
307 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
308 | interrupt-names = "cmd_irq"; | |
309 | clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; | |
310 | clock-names = "mclk", "apb_pclk"; | |
311 | bus-width = <8>; | |
312 | max-frequency = <96000000>; | |
313 | non-removable; | |
314 | cap-sd-highspeed; | |
315 | cap-mmc-highspeed; | |
316 | vmmc-supply = <&vsdcc_fixed>; | |
edb81ca3 SK |
317 | dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; |
318 | dma-names = "tx", "rx"; | |
045644ff SK |
319 | }; |
320 | ||
321 | sdcc3: sdcc@12180000 { | |
322 | compatible = "arm,pl18x", "arm,primecell"; | |
323 | arm,primecell-periphid = <0x00051180>; | |
324 | status = "disabled"; | |
325 | reg = <0x12180000 0x2000>; | |
326 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
327 | interrupt-names = "cmd_irq"; | |
328 | clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; | |
329 | clock-names = "mclk", "apb_pclk"; | |
330 | bus-width = <4>; | |
331 | cap-sd-highspeed; | |
332 | cap-mmc-highspeed; | |
333 | max-frequency = <192000000>; | |
334 | no-1-8-v; | |
335 | vmmc-supply = <&vsdcc_fixed>; | |
edb81ca3 SK |
336 | dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; |
337 | dma-names = "tx", "rx"; | |
045644ff | 338 | }; |
0be5fef1 SK |
339 | |
340 | sdcc4: sdcc@121c0000 { | |
341 | compatible = "arm,pl18x", "arm,primecell"; | |
342 | arm,primecell-periphid = <0x00051180>; | |
343 | status = "disabled"; | |
344 | reg = <0x121c0000 0x2000>; | |
345 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
346 | interrupt-names = "cmd_irq"; | |
347 | clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; | |
348 | clock-names = "mclk", "apb_pclk"; | |
349 | bus-width = <4>; | |
350 | cap-sd-highspeed; | |
351 | cap-mmc-highspeed; | |
352 | max-frequency = <48000000>; | |
353 | vmmc-supply = <&vsdcc_fixed>; | |
354 | vqmmc-supply = <&vsdcc_fixed>; | |
355 | dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; | |
356 | dma-names = "tx", "rx"; | |
357 | pinctrl-names = "default"; | |
358 | pinctrl-0 = <&sdc4_gpios>; | |
359 | }; | |
045644ff | 360 | }; |
4105d9d6 AG |
361 | |
362 | tcsr: syscon@1a400000 { | |
363 | compatible = "qcom,tcsr-apq8064", "syscon"; | |
364 | reg = <0x1a400000 0x100>; | |
365 | }; | |
f335b8af KG |
366 | }; |
367 | }; |