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bec6ba4c MM |
1 | /* |
2 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | /dts-v1/; | |
15 | ||
16 | #include "skeleton.dtsi" | |
17 | #include <dt-bindings/clock/qcom,gcc-ipq4019.h> | |
13ad4fd3 MM |
18 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
19 | #include <dt-bindings/interrupt-controller/irq.h> | |
bec6ba4c MM |
20 | |
21 | / { | |
22 | model = "Qualcomm Technologies, Inc. IPQ4019"; | |
23 | compatible = "qcom,ipq4019"; | |
24 | interrupt-parent = <&intc>; | |
25 | ||
13ad4fd3 MM |
26 | aliases { |
27 | spi0 = &spi_0; | |
e76b4284 | 28 | i2c0 = &i2c_0; |
13ad4fd3 MM |
29 | }; |
30 | ||
bec6ba4c MM |
31 | cpus { |
32 | #address-cells = <1>; | |
33 | #size-cells = <0>; | |
34 | cpu@0 { | |
35 | device_type = "cpu"; | |
36 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
37 | enable-method = "qcom,kpss-acc-v1"; |
38 | qcom,acc = <&acc0>; | |
39 | qcom,saw = <&saw0>; | |
bec6ba4c MM |
40 | reg = <0x0>; |
41 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 42 | clock-frequency = <0>; |
15689ec2 MM |
43 | operating-points = < |
44 | /* kHz uV (fixed) */ | |
45 | 48000 1100000 | |
46 | 200000 1100000 | |
47 | 500000 1100000 | |
48 | 666000 1100000 | |
49 | >; | |
50 | clock-latency = <256000>; | |
bec6ba4c MM |
51 | }; |
52 | ||
53 | cpu@1 { | |
54 | device_type = "cpu"; | |
55 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
56 | enable-method = "qcom,kpss-acc-v1"; |
57 | qcom,acc = <&acc1>; | |
58 | qcom,saw = <&saw1>; | |
bec6ba4c MM |
59 | reg = <0x1>; |
60 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 61 | clock-frequency = <0>; |
bec6ba4c MM |
62 | }; |
63 | ||
64 | cpu@2 { | |
65 | device_type = "cpu"; | |
66 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
67 | enable-method = "qcom,kpss-acc-v1"; |
68 | qcom,acc = <&acc2>; | |
69 | qcom,saw = <&saw2>; | |
bec6ba4c MM |
70 | reg = <0x2>; |
71 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 72 | clock-frequency = <0>; |
bec6ba4c MM |
73 | }; |
74 | ||
75 | cpu@3 { | |
76 | device_type = "cpu"; | |
77 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
78 | enable-method = "qcom,kpss-acc-v1"; |
79 | qcom,acc = <&acc3>; | |
80 | qcom,saw = <&saw3>; | |
bec6ba4c MM |
81 | reg = <0x3>; |
82 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 83 | clock-frequency = <0>; |
bec6ba4c MM |
84 | }; |
85 | }; | |
86 | ||
c3d53130 TP |
87 | pmu { |
88 | compatible = "arm,cortex-a7-pmu"; | |
89 | interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | | |
90 | IRQ_TYPE_LEVEL_HIGH)>; | |
91 | }; | |
92 | ||
bec6ba4c MM |
93 | clocks { |
94 | sleep_clk: sleep_clk { | |
95 | compatible = "fixed-clock"; | |
96 | clock-frequency = <32768>; | |
97 | #clock-cells = <0>; | |
98 | }; | |
75ea98ac VN |
99 | |
100 | xo: xo { | |
101 | compatible = "fixed-clock"; | |
102 | clock-frequency = <48000000>; | |
103 | #clock-cells = <0>; | |
104 | }; | |
105 | }; | |
106 | ||
107 | timer { | |
108 | compatible = "arm,armv7-timer"; | |
109 | interrupts = <1 2 0xf08>, | |
110 | <1 3 0xf08>, | |
111 | <1 4 0xf08>, | |
112 | <1 1 0xf08>; | |
113 | clock-frequency = <48000000>; | |
bec6ba4c MM |
114 | }; |
115 | ||
116 | soc { | |
117 | #address-cells = <1>; | |
118 | #size-cells = <1>; | |
119 | ranges; | |
120 | compatible = "simple-bus"; | |
121 | ||
122 | intc: interrupt-controller@b000000 { | |
123 | compatible = "qcom,msm-qgic2"; | |
124 | interrupt-controller; | |
125 | #interrupt-cells = <3>; | |
126 | reg = <0x0b000000 0x1000>, | |
127 | <0x0b002000 0x1000>; | |
128 | }; | |
129 | ||
130 | gcc: clock-controller@1800000 { | |
131 | compatible = "qcom,gcc-ipq4019"; | |
132 | #clock-cells = <1>; | |
133 | #reset-cells = <1>; | |
134 | reg = <0x1800000 0x60000>; | |
135 | }; | |
136 | ||
6bfe03dd CL |
137 | rng@22000 { |
138 | compatible = "qcom,prng"; | |
139 | reg = <0x22000 0x140>; | |
140 | clocks = <&gcc GCC_PRNG_AHB_CLK>; | |
141 | clock-names = "core"; | |
142 | status = "disabled"; | |
143 | }; | |
144 | ||
ba4ca27b | 145 | tlmm: pinctrl@1000000 { |
bec6ba4c MM |
146 | compatible = "qcom,ipq4019-pinctrl"; |
147 | reg = <0x01000000 0x300000>; | |
148 | gpio-controller; | |
149 | #gpio-cells = <2>; | |
150 | interrupt-controller; | |
151 | #interrupt-cells = <2>; | |
152 | interrupts = <0 208 0>; | |
153 | }; | |
154 | ||
9ca595f0 MM |
155 | blsp_dma: dma@7884000 { |
156 | compatible = "qcom,bam-v1.7.0"; | |
157 | reg = <0x07884000 0x23000>; | |
158 | interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; | |
159 | clocks = <&gcc GCC_BLSP1_AHB_CLK>; | |
160 | clock-names = "bam_clk"; | |
161 | #dma-cells = <1>; | |
162 | qcom,ee = <0>; | |
163 | status = "disabled"; | |
164 | }; | |
165 | ||
13ad4fd3 MM |
166 | spi_0: spi@78b5000 { |
167 | compatible = "qcom,spi-qup-v2.2.1"; | |
168 | reg = <0x78b5000 0x600>; | |
169 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
170 | clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, | |
171 | <&gcc GCC_BLSP1_AHB_CLK>; | |
172 | clock-names = "core", "iface"; | |
173 | #address-cells = <1>; | |
174 | #size-cells = <0>; | |
175 | status = "disabled"; | |
176 | }; | |
177 | ||
e76b4284 MM |
178 | i2c_0: i2c@78b7000 { |
179 | compatible = "qcom,i2c-qup-v2.2.1"; | |
650df439 | 180 | reg = <0x78b7000 0x600>; |
e76b4284 MM |
181 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
182 | clocks = <&gcc GCC_BLSP1_AHB_CLK>, | |
650df439 | 183 | <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; |
e76b4284 MM |
184 | clock-names = "iface", "core"; |
185 | #address-cells = <1>; | |
186 | #size-cells = <0>; | |
187 | status = "disabled"; | |
188 | }; | |
189 | ||
fd6fd386 MM |
190 | |
191 | cryptobam: dma@8e04000 { | |
192 | compatible = "qcom,bam-v1.7.0"; | |
193 | reg = <0x08e04000 0x20000>; | |
194 | interrupts = <GIC_SPI 207 0>; | |
195 | clocks = <&gcc GCC_CRYPTO_AHB_CLK>; | |
196 | clock-names = "bam_clk"; | |
197 | #dma-cells = <1>; | |
198 | qcom,ee = <1>; | |
199 | qcom,controlled-remotely; | |
200 | status = "disabled"; | |
201 | }; | |
202 | ||
203 | crypto@8e3a000 { | |
204 | compatible = "qcom,crypto-v5.1"; | |
205 | reg = <0x08e3a000 0x6000>; | |
206 | clocks = <&gcc GCC_CRYPTO_AHB_CLK>, | |
207 | <&gcc GCC_CRYPTO_AXI_CLK>, | |
208 | <&gcc GCC_CRYPTO_CLK>; | |
209 | clock-names = "iface", "bus", "core"; | |
210 | dmas = <&cryptobam 2>, <&cryptobam 3>; | |
211 | dma-names = "rx", "tx"; | |
212 | status = "disabled"; | |
213 | }; | |
214 | ||
595b30c7 MM |
215 | acc0: clock-controller@b088000 { |
216 | compatible = "qcom,kpss-acc-v1"; | |
217 | reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; | |
218 | }; | |
219 | ||
220 | acc1: clock-controller@b098000 { | |
221 | compatible = "qcom,kpss-acc-v1"; | |
222 | reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; | |
223 | }; | |
224 | ||
225 | acc2: clock-controller@b0a8000 { | |
226 | compatible = "qcom,kpss-acc-v1"; | |
227 | reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; | |
228 | }; | |
229 | ||
230 | acc3: clock-controller@b0b8000 { | |
231 | compatible = "qcom,kpss-acc-v1"; | |
232 | reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; | |
233 | }; | |
234 | ||
235 | saw0: regulator@b089000 { | |
236 | compatible = "qcom,saw2"; | |
237 | reg = <0x02089000 0x1000>, <0x0b009000 0x1000>; | |
238 | regulator; | |
239 | }; | |
240 | ||
241 | saw1: regulator@b099000 { | |
242 | compatible = "qcom,saw2"; | |
243 | reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; | |
244 | regulator; | |
245 | }; | |
246 | ||
247 | saw2: regulator@b0a9000 { | |
248 | compatible = "qcom,saw2"; | |
249 | reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; | |
250 | regulator; | |
251 | }; | |
252 | ||
253 | saw3: regulator@b0b9000 { | |
254 | compatible = "qcom,saw2"; | |
255 | reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; | |
256 | regulator; | |
257 | }; | |
258 | ||
bec6ba4c MM |
259 | serial@78af000 { |
260 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
261 | reg = <0x78af000 0x200>; | |
262 | interrupts = <0 107 0>; | |
263 | status = "disabled"; | |
264 | clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, | |
265 | <&gcc GCC_BLSP1_AHB_CLK>; | |
266 | clock-names = "core", "iface"; | |
9ca595f0 MM |
267 | dmas = <&blsp_dma 1>, <&blsp_dma 0>; |
268 | dma-names = "rx", "tx"; | |
bec6ba4c MM |
269 | }; |
270 | ||
271 | serial@78b0000 { | |
272 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
273 | reg = <0x78b0000 0x200>; | |
274 | interrupts = <0 108 0>; | |
275 | status = "disabled"; | |
276 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, | |
277 | <&gcc GCC_BLSP1_AHB_CLK>; | |
278 | clock-names = "core", "iface"; | |
9ca595f0 MM |
279 | dmas = <&blsp_dma 3>, <&blsp_dma 2>; |
280 | dma-names = "rx", "tx"; | |
bec6ba4c | 281 | }; |
40057afd MM |
282 | |
283 | watchdog@b017000 { | |
f0d9d0f4 | 284 | compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; |
40057afd MM |
285 | reg = <0xb017000 0x40>; |
286 | clocks = <&sleep_clk>; | |
287 | timeout-sec = <10>; | |
288 | status = "disabled"; | |
289 | }; | |
8196dd5e MM |
290 | |
291 | restart@4ab000 { | |
292 | compatible = "qcom,pshold"; | |
293 | reg = <0x4ab000 0x4>; | |
294 | }; | |
bec6ba4c MM |
295 | }; |
296 | }; |