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bec6ba4c MM |
1 | /* |
2 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | /dts-v1/; | |
15 | ||
16 | #include "skeleton.dtsi" | |
17 | #include <dt-bindings/clock/qcom,gcc-ipq4019.h> | |
13ad4fd3 MM |
18 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
19 | #include <dt-bindings/interrupt-controller/irq.h> | |
bec6ba4c MM |
20 | |
21 | / { | |
22 | model = "Qualcomm Technologies, Inc. IPQ4019"; | |
23 | compatible = "qcom,ipq4019"; | |
24 | interrupt-parent = <&intc>; | |
25 | ||
13ad4fd3 MM |
26 | aliases { |
27 | spi0 = &spi_0; | |
e76b4284 | 28 | i2c0 = &i2c_0; |
13ad4fd3 MM |
29 | }; |
30 | ||
bec6ba4c MM |
31 | cpus { |
32 | #address-cells = <1>; | |
33 | #size-cells = <0>; | |
34 | cpu@0 { | |
35 | device_type = "cpu"; | |
36 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
37 | enable-method = "qcom,kpss-acc-v1"; |
38 | qcom,acc = <&acc0>; | |
39 | qcom,saw = <&saw0>; | |
bec6ba4c MM |
40 | reg = <0x0>; |
41 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 42 | clock-frequency = <0>; |
15689ec2 MM |
43 | operating-points = < |
44 | /* kHz uV (fixed) */ | |
45 | 48000 1100000 | |
46 | 200000 1100000 | |
47 | 500000 1100000 | |
48 | 666000 1100000 | |
49 | >; | |
50 | clock-latency = <256000>; | |
bec6ba4c MM |
51 | }; |
52 | ||
53 | cpu@1 { | |
54 | device_type = "cpu"; | |
55 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
56 | enable-method = "qcom,kpss-acc-v1"; |
57 | qcom,acc = <&acc1>; | |
58 | qcom,saw = <&saw1>; | |
bec6ba4c MM |
59 | reg = <0x1>; |
60 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 61 | clock-frequency = <0>; |
bec6ba4c MM |
62 | }; |
63 | ||
64 | cpu@2 { | |
65 | device_type = "cpu"; | |
66 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
67 | enable-method = "qcom,kpss-acc-v1"; |
68 | qcom,acc = <&acc2>; | |
69 | qcom,saw = <&saw2>; | |
bec6ba4c MM |
70 | reg = <0x2>; |
71 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 72 | clock-frequency = <0>; |
bec6ba4c MM |
73 | }; |
74 | ||
75 | cpu@3 { | |
76 | device_type = "cpu"; | |
77 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
78 | enable-method = "qcom,kpss-acc-v1"; |
79 | qcom,acc = <&acc3>; | |
80 | qcom,saw = <&saw3>; | |
bec6ba4c MM |
81 | reg = <0x3>; |
82 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 83 | clock-frequency = <0>; |
bec6ba4c MM |
84 | }; |
85 | }; | |
86 | ||
c3d53130 TP |
87 | pmu { |
88 | compatible = "arm,cortex-a7-pmu"; | |
89 | interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | | |
90 | IRQ_TYPE_LEVEL_HIGH)>; | |
91 | }; | |
92 | ||
bec6ba4c MM |
93 | clocks { |
94 | sleep_clk: sleep_clk { | |
95 | compatible = "fixed-clock"; | |
96 | clock-frequency = <32768>; | |
97 | #clock-cells = <0>; | |
98 | }; | |
99 | }; | |
100 | ||
101 | soc { | |
102 | #address-cells = <1>; | |
103 | #size-cells = <1>; | |
104 | ranges; | |
105 | compatible = "simple-bus"; | |
106 | ||
107 | intc: interrupt-controller@b000000 { | |
108 | compatible = "qcom,msm-qgic2"; | |
109 | interrupt-controller; | |
110 | #interrupt-cells = <3>; | |
111 | reg = <0x0b000000 0x1000>, | |
112 | <0x0b002000 0x1000>; | |
113 | }; | |
114 | ||
115 | gcc: clock-controller@1800000 { | |
116 | compatible = "qcom,gcc-ipq4019"; | |
117 | #clock-cells = <1>; | |
118 | #reset-cells = <1>; | |
119 | reg = <0x1800000 0x60000>; | |
120 | }; | |
121 | ||
122 | tlmm: pinctrl@0x01000000 { | |
123 | compatible = "qcom,ipq4019-pinctrl"; | |
124 | reg = <0x01000000 0x300000>; | |
125 | gpio-controller; | |
126 | #gpio-cells = <2>; | |
127 | interrupt-controller; | |
128 | #interrupt-cells = <2>; | |
129 | interrupts = <0 208 0>; | |
130 | }; | |
131 | ||
9ca595f0 MM |
132 | blsp_dma: dma@7884000 { |
133 | compatible = "qcom,bam-v1.7.0"; | |
134 | reg = <0x07884000 0x23000>; | |
135 | interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; | |
136 | clocks = <&gcc GCC_BLSP1_AHB_CLK>; | |
137 | clock-names = "bam_clk"; | |
138 | #dma-cells = <1>; | |
139 | qcom,ee = <0>; | |
140 | status = "disabled"; | |
141 | }; | |
142 | ||
13ad4fd3 MM |
143 | spi_0: spi@78b5000 { |
144 | compatible = "qcom,spi-qup-v2.2.1"; | |
145 | reg = <0x78b5000 0x600>; | |
146 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
147 | clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, | |
148 | <&gcc GCC_BLSP1_AHB_CLK>; | |
149 | clock-names = "core", "iface"; | |
150 | #address-cells = <1>; | |
151 | #size-cells = <0>; | |
152 | status = "disabled"; | |
153 | }; | |
154 | ||
e76b4284 MM |
155 | i2c_0: i2c@78b7000 { |
156 | compatible = "qcom,i2c-qup-v2.2.1"; | |
157 | reg = <0x78b7000 0x6000>; | |
158 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
159 | clocks = <&gcc GCC_BLSP1_AHB_CLK>, | |
160 | <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; | |
161 | clock-names = "iface", "core"; | |
162 | #address-cells = <1>; | |
163 | #size-cells = <0>; | |
164 | status = "disabled"; | |
165 | }; | |
166 | ||
fd6fd386 MM |
167 | |
168 | cryptobam: dma@8e04000 { | |
169 | compatible = "qcom,bam-v1.7.0"; | |
170 | reg = <0x08e04000 0x20000>; | |
171 | interrupts = <GIC_SPI 207 0>; | |
172 | clocks = <&gcc GCC_CRYPTO_AHB_CLK>; | |
173 | clock-names = "bam_clk"; | |
174 | #dma-cells = <1>; | |
175 | qcom,ee = <1>; | |
176 | qcom,controlled-remotely; | |
177 | status = "disabled"; | |
178 | }; | |
179 | ||
180 | crypto@8e3a000 { | |
181 | compatible = "qcom,crypto-v5.1"; | |
182 | reg = <0x08e3a000 0x6000>; | |
183 | clocks = <&gcc GCC_CRYPTO_AHB_CLK>, | |
184 | <&gcc GCC_CRYPTO_AXI_CLK>, | |
185 | <&gcc GCC_CRYPTO_CLK>; | |
186 | clock-names = "iface", "bus", "core"; | |
187 | dmas = <&cryptobam 2>, <&cryptobam 3>; | |
188 | dma-names = "rx", "tx"; | |
189 | status = "disabled"; | |
190 | }; | |
191 | ||
595b30c7 MM |
192 | acc0: clock-controller@b088000 { |
193 | compatible = "qcom,kpss-acc-v1"; | |
194 | reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; | |
195 | }; | |
196 | ||
197 | acc1: clock-controller@b098000 { | |
198 | compatible = "qcom,kpss-acc-v1"; | |
199 | reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; | |
200 | }; | |
201 | ||
202 | acc2: clock-controller@b0a8000 { | |
203 | compatible = "qcom,kpss-acc-v1"; | |
204 | reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; | |
205 | }; | |
206 | ||
207 | acc3: clock-controller@b0b8000 { | |
208 | compatible = "qcom,kpss-acc-v1"; | |
209 | reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; | |
210 | }; | |
211 | ||
212 | saw0: regulator@b089000 { | |
213 | compatible = "qcom,saw2"; | |
214 | reg = <0x02089000 0x1000>, <0x0b009000 0x1000>; | |
215 | regulator; | |
216 | }; | |
217 | ||
218 | saw1: regulator@b099000 { | |
219 | compatible = "qcom,saw2"; | |
220 | reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; | |
221 | regulator; | |
222 | }; | |
223 | ||
224 | saw2: regulator@b0a9000 { | |
225 | compatible = "qcom,saw2"; | |
226 | reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; | |
227 | regulator; | |
228 | }; | |
229 | ||
230 | saw3: regulator@b0b9000 { | |
231 | compatible = "qcom,saw2"; | |
232 | reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; | |
233 | regulator; | |
234 | }; | |
235 | ||
bec6ba4c MM |
236 | serial@78af000 { |
237 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
238 | reg = <0x78af000 0x200>; | |
239 | interrupts = <0 107 0>; | |
240 | status = "disabled"; | |
241 | clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, | |
242 | <&gcc GCC_BLSP1_AHB_CLK>; | |
243 | clock-names = "core", "iface"; | |
9ca595f0 MM |
244 | dmas = <&blsp_dma 1>, <&blsp_dma 0>; |
245 | dma-names = "rx", "tx"; | |
bec6ba4c MM |
246 | }; |
247 | ||
248 | serial@78b0000 { | |
249 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
250 | reg = <0x78b0000 0x200>; | |
251 | interrupts = <0 108 0>; | |
252 | status = "disabled"; | |
253 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, | |
254 | <&gcc GCC_BLSP1_AHB_CLK>; | |
255 | clock-names = "core", "iface"; | |
9ca595f0 MM |
256 | dmas = <&blsp_dma 3>, <&blsp_dma 2>; |
257 | dma-names = "rx", "tx"; | |
bec6ba4c | 258 | }; |
40057afd MM |
259 | |
260 | watchdog@b017000 { | |
f0d9d0f4 | 261 | compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; |
40057afd MM |
262 | reg = <0xb017000 0x40>; |
263 | clocks = <&sleep_clk>; | |
264 | timeout-sec = <10>; | |
265 | status = "disabled"; | |
266 | }; | |
8196dd5e MM |
267 | |
268 | restart@4ab000 { | |
269 | compatible = "qcom,pshold"; | |
270 | reg = <0x4ab000 0x4>; | |
271 | }; | |
bec6ba4c MM |
272 | }; |
273 | }; |