[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / qcom-ipq4019.dtsi

/*
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;

#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "Qualcomm Technologies, Inc. IPQ4019";
	compatible = "qcom,ipq4019";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;

		smem_region: smem@87e00000 {
			reg = <0x87e00000 0x080000>;
			no-map;
		};

		tz@87e80000 {
			reg = <0x87e80000 0x180000>;
			no-map;
		};
	};

	aliases {
		spi0 = &blsp1_spi1;
		spi1 = &blsp1_spi2;
		i2c0 = &blsp1_i2c3;
		i2c1 = &blsp1_i2c4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			reg = <0x0>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			operating-points = <
				/* kHz	uV (fixed) */
				48000	1100000
				200000	1100000
				500000	1100000
				716000  1100000
			>;
			clock-latency = <256000>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			reg = <0x1>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			operating-points = <
				/* kHz	uV (fixed) */
				48000	1100000
				200000	1100000
				500000	1100000
				666000	1100000
			>;
			clock-latency = <256000>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			reg = <0x2>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			operating-points = <
				/* kHz	uV (fixed) */
				48000	1100000
				200000	1100000
				500000	1100000
				666000	1100000
			>;
			clock-latency = <256000>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			reg = <0x3>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			operating-points = <
				/* kHz	uV (fixed) */
				48000	1100000
				200000	1100000
				500000	1100000
				666000	1100000
			>;
			clock-latency = <256000>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
					 IRQ_TYPE_LEVEL_HIGH)>;
	};

	clocks {
		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			#clock-cells = <0>;
		};

		xo: xo {
			compatible = "fixed-clock";
			clock-frequency = <48000000>;
			#clock-cells = <0>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-ipq4019";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <48000000>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x0b000000 0x1000>,
			<0x0b002000 0x1000>;
		};

		gcc: clock-controller@1800000 {
			compatible = "qcom,gcc-ipq4019";
			#clock-cells = <1>;
			#reset-cells = <1>;
			reg = <0x1800000 0x60000>;
		};

		rng@22000 {
			compatible = "qcom,prng";
			reg = <0x22000 0x140>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
			status = "disabled";
		};

		tlmm: pinctrl@1000000 {
			compatible = "qcom,ipq4019-pinctrl";
			reg = <0x01000000 0x300000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		};

		blsp_dma: dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x23000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x78b5000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x78b6000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 7>, <&blsp_dma 6>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b7000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b8000 0x600>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 11>, <&blsp_dma 10>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		cryptobam: dma@8e04000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x08e04000 0x20000>;
			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <1>;
			qcom,controlled-remotely;
			status = "disabled";
		};

		crypto@8e3a000 {
			compatible = "qcom,crypto-v5.1";
			reg = <0x08e3a000 0x6000>;
			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
				 <&gcc GCC_CRYPTO_AXI_CLK>,
				 <&gcc GCC_CRYPTO_CLK>;
			clock-names = "iface", "bus", "core";
			dmas = <&cryptobam 2>, <&cryptobam 3>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

                acc0: clock-controller@b088000 {
                        compatible = "qcom,kpss-acc-v2";
                        reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
                };

                acc1: clock-controller@b098000 {
                        compatible = "qcom,kpss-acc-v2";
                        reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
                };

                acc2: clock-controller@b0a8000 {
                        compatible = "qcom,kpss-acc-v2";
                        reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
                };

                acc3: clock-controller@b0b8000 {
                        compatible = "qcom,kpss-acc-v2";
                        reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
                };

                saw0: regulator@b089000 {
                        compatible = "qcom,saw2";
                        reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
                        regulator;
                };

                saw1: regulator@b099000 {
                        compatible = "qcom,saw2";
                        reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
                        regulator;
                };

                saw2: regulator@b0a9000 {
                        compatible = "qcom,saw2";
                        reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
                        regulator;
                };

                saw3: regulator@b0b9000 {
                        compatible = "qcom,saw2";
                        reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
                        regulator;
                };

		blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
			dma-names = "rx", "tx";
		};

		blsp1_uart2: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
			dma-names = "rx", "tx";
		};

		watchdog@b017000 {
			compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
			reg = <0xb017000 0x40>;
			clocks = <&sleep_clk>;
			timeout-sec = <10>;
			status = "disabled";
		};

		restart@4ab000 {
			compatible = "qcom,pshold";
			reg = <0x4ab000 0x4>;
		};

		pcie0: pci@40000000 {
			compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
			reg =  <0x40000000 0xf1d
				0x40000f20 0xa8
				0x80000 0x2000
				0x40100000 0x1000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
				  0x82000000 0 0x48000000 0x48000000 0 0x10000000>;

			interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
			clocks = <&gcc GCC_PCIE_AHB_CLK>,
				 <&gcc GCC_PCIE_AXI_M_CLK>,
				 <&gcc GCC_PCIE_AXI_S_CLK>;
			clock-names = "aux",
				      "master_bus",
				      "slave_bus";

			resets = <&gcc PCIE_AXI_M_ARES>,
				 <&gcc PCIE_AXI_S_ARES>,
				 <&gcc PCIE_PIPE_ARES>,
				 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
				 <&gcc PCIE_AXI_S_XPU_ARES>,
				 <&gcc PCIE_PARF_XPU_ARES>,
				 <&gcc PCIE_PHY_ARES>,
				 <&gcc PCIE_AXI_M_STICKY_ARES>,
				 <&gcc PCIE_PIPE_STICKY_ARES>,
				 <&gcc PCIE_PWR_ARES>,
				 <&gcc PCIE_AHB_ARES>,
				 <&gcc PCIE_PHY_AHB_ARES>;
			reset-names = "axi_m",
				      "axi_s",
				      "pipe",
				      "axi_m_vmid",
				      "axi_s_xpu",
				      "parf",
				      "phy",
				      "axi_m_sticky",
				      "pipe_sticky",
				      "pwr",
				      "ahb",
				      "phy_ahb";

			status = "disabled";
		};

		qpic_bam: dma@7984000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x7984000 0x1a000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_QPIC_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		nand: qpic-nand@79b0000 {
			compatible = "qcom,ipq4019-nand";
			reg = <0x79b0000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&gcc GCC_QPIC_CLK>,
				 <&gcc GCC_QPIC_AHB_CLK>;
			clock-names = "core", "aon";

			dmas = <&qpic_bam 0>,
			       <&qpic_bam 1>,
			       <&qpic_bam 2>;
			dma-names = "tx", "rx", "cmd";
			status = "disabled";

			nand@0 {
				reg = <0>;

				nand-ecc-strength = <4>;
				nand-ecc-step-size = <512>;
				nand-bus-width = <8>;
			};
		};

		wifi0: wifi@a000000 {
			compatible = "qcom,ipq4019-wifi";
			reg = <0xa000000 0x200000>;
			resets = <&gcc WIFI0_CPU_INIT_RESET>,
				 <&gcc WIFI0_RADIO_SRIF_RESET>,
				 <&gcc WIFI0_RADIO_WARM_RESET>,
				 <&gcc WIFI0_RADIO_COLD_RESET>,
				 <&gcc WIFI0_CORE_WARM_RESET>,
				 <&gcc WIFI0_CORE_COLD_RESET>;
			reset-names = "wifi_cpu_init", "wifi_radio_srif",
				      "wifi_radio_warm", "wifi_radio_cold",
				      "wifi_core_warm", "wifi_core_cold";
			clocks = <&gcc GCC_WCSS2G_CLK>,
				 <&gcc GCC_WCSS2G_REF_CLK>,
				 <&gcc GCC_WCSS2G_RTC_CLK>;
			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
				      "wifi_wcss_rtc";
			interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
					   "msi4",  "msi5",  "msi6",  "msi7",
					   "msi8",  "msi9", "msi10", "msi11",
					  "msi12", "msi13", "msi14", "msi15",
					  "legacy";
			status = "disabled";
		};

		wifi1: wifi@a800000 {
			compatible = "qcom,ipq4019-wifi";
			reg = <0xa800000 0x200000>;
			resets = <&gcc WIFI1_CPU_INIT_RESET>,
				 <&gcc WIFI1_RADIO_SRIF_RESET>,
				 <&gcc WIFI1_RADIO_WARM_RESET>,
				 <&gcc WIFI1_RADIO_COLD_RESET>,
				 <&gcc WIFI1_CORE_WARM_RESET>,
				 <&gcc WIFI1_CORE_COLD_RESET>;
			reset-names = "wifi_cpu_init", "wifi_radio_srif",
				      "wifi_radio_warm", "wifi_radio_cold",
				      "wifi_core_warm", "wifi_core_cold";
			clocks = <&gcc GCC_WCSS5G_CLK>,
				 <&gcc GCC_WCSS5G_REF_CLK>,
				 <&gcc GCC_WCSS5G_RTC_CLK>;
			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
				      "wifi_wcss_rtc";
			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
					   "msi4",  "msi5",  "msi6",  "msi7",
					   "msi8",  "msi9", "msi10", "msi11",
					  "msi12", "msi13", "msi14", "msi15",
					  "legacy";
			status = "disabled";
		};
	};
};
Commit	Line	Data
bec6ba4c MM	1	/*
	2	* Copyright (c) 2015, The Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	/dts-v1/;
	15
	16	#include "skeleton.dtsi"
	17	#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
13ad4fd3 MM	18	#include <dt-bindings/interrupt-controller/arm-gic.h>
13ad4fd3 MM	19	#include <dt-bindings/interrupt-controller/irq.h>
bec6ba4c MM	20
	21	/ {
	22	model = "Qualcomm Technologies, Inc. IPQ4019";
	23	compatible = "qcom,ipq4019";
	24	interrupt-parent = <&intc>;
	25
4ccd111f SE	26	reserved-memory {
	27	#address-cells = <0x1>;
	28	#size-cells = <0x1>;
	29	ranges;
	30
	31	smem_region: smem@87e00000 {
	32	reg = <0x87e00000 0x080000>;
	33	no-map;
	34	};
	35
	36	tz@87e80000 {
	37	reg = <0x87e80000 0x180000>;
	38	no-map;
	39	};
	40	};
	41
13ad4fd3	42	aliases {
18751940 S	43	spi0 = &blsp1_spi1;
	44	spi1 = &blsp1_spi2;
	45	i2c0 = &blsp1_i2c3;
	46	i2c1 = &blsp1_i2c4;
13ad4fd3 MM	47	};
13ad4fd3 MM	48
bec6ba4c MM	49	cpus {
	50	#address-cells = <1>;
	51	#size-cells = <0>;
	52	cpu@0 {
	53	device_type = "cpu";
	54	compatible = "arm,cortex-a7";
233c77d4 MM	55	enable-method = "qcom,kpss-acc-v2";
233c77d4 MM	56	next-level-cache = <&L2>;
595b30c7 MM	57	qcom,acc = <&acc0>;
595b30c7 MM	58	qcom,saw = <&saw0>;
bec6ba4c MM	59	reg = <0x0>;
bec6ba4c MM	60	clocks = <&gcc GCC_APPS_CLK_SRC>;
595b30c7	61	clock-frequency = <0>;
15689ec2 MM	62	operating-points = <
	63	/* kHz uV (fixed) */
	64	48000 1100000
	65	200000 1100000
	66	500000 1100000
bd1ab036	67	716000 1100000
15689ec2 MM	68	>;
15689ec2 MM	69	clock-latency = <256000>;
bec6ba4c MM	70	};
	71
	72	cpu@1 {
	73	device_type = "cpu";
	74	compatible = "arm,cortex-a7";
233c77d4 MM	75	enable-method = "qcom,kpss-acc-v2";
233c77d4 MM	76	next-level-cache = <&L2>;
595b30c7 MM	77	qcom,acc = <&acc1>;
595b30c7 MM	78	qcom,saw = <&saw1>;
bec6ba4c MM	79	reg = <0x1>;
bec6ba4c MM	80	clocks = <&gcc GCC_APPS_CLK_SRC>;
595b30c7	81	clock-frequency = <0>;
b0c28f27 VK	82	operating-points = <
	83	/* kHz uV (fixed) */
	84	48000 1100000
	85	200000 1100000
	86	500000 1100000
	87	666000 1100000
	88	>;
	89	clock-latency = <256000>;
bec6ba4c MM	90	};
	91
	92	cpu@2 {
	93	device_type = "cpu";
	94	compatible = "arm,cortex-a7";
233c77d4 MM	95	enable-method = "qcom,kpss-acc-v2";
233c77d4 MM	96	next-level-cache = <&L2>;
595b30c7 MM	97	qcom,acc = <&acc2>;
595b30c7 MM	98	qcom,saw = <&saw2>;
bec6ba4c MM	99	reg = <0x2>;
bec6ba4c MM	100	clocks = <&gcc GCC_APPS_CLK_SRC>;
595b30c7	101	clock-frequency = <0>;
b0c28f27 VK	102	operating-points = <
	103	/* kHz uV (fixed) */
	104	48000 1100000
	105	200000 1100000
	106	500000 1100000
	107	666000 1100000
	108	>;
	109	clock-latency = <256000>;
bec6ba4c MM	110	};
	111
	112	cpu@3 {
	113	device_type = "cpu";
	114	compatible = "arm,cortex-a7";
233c77d4 MM	115	enable-method = "qcom,kpss-acc-v2";
233c77d4 MM	116	next-level-cache = <&L2>;
595b30c7 MM	117	qcom,acc = <&acc3>;
595b30c7 MM	118	qcom,saw = <&saw3>;
bec6ba4c MM	119	reg = <0x3>;
bec6ba4c MM	120	clocks = <&gcc GCC_APPS_CLK_SRC>;
595b30c7	121	clock-frequency = <0>;
b0c28f27 VK	122	operating-points = <
	123	/* kHz uV (fixed) */
	124	48000 1100000
	125	200000 1100000
	126	500000 1100000
	127	666000 1100000
	128	>;
	129	clock-latency = <256000>;
bec6ba4c	130	};
233c77d4 MM	131
	132	L2: l2-cache {
	133	compatible = "cache";
	134	cache-level = <2>;
	135	};
bec6ba4c MM	136	};
bec6ba4c MM	137
c3d53130 TP	138	pmu {
	139	compatible = "arm,cortex-a7-pmu";
	140	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) \|
	141	IRQ_TYPE_LEVEL_HIGH)>;
	142	};
	143
bec6ba4c MM	144	clocks {
	145	sleep_clk: sleep_clk {
	146	compatible = "fixed-clock";
	147	clock-frequency = <32768>;
	148	#clock-cells = <0>;
	149	};
75ea98ac VN	150
	151	xo: xo {
	152	compatible = "fixed-clock";
	153	clock-frequency = <48000000>;
	154	#clock-cells = <0>;
	155	};
	156	};
	157
18751940 S	158	firmware {
	159	scm {
	160	compatible = "qcom,scm-ipq4019";
	161	};
	162	};
	163
75ea98ac VN	164	timer {
	165	compatible = "arm,armv7-timer";
	166	interrupts = <1 2 0xf08>,
	167	<1 3 0xf08>,
	168	<1 4 0xf08>,
	169	<1 1 0xf08>;
	170	clock-frequency = <48000000>;
bec6ba4c MM	171	};
	172
	173	soc {
	174	#address-cells = <1>;
	175	#size-cells = <1>;
	176	ranges;
	177	compatible = "simple-bus";
	178
	179	intc: interrupt-controller@b000000 {
	180	compatible = "qcom,msm-qgic2";
	181	interrupt-controller;
	182	#interrupt-cells = <3>;
	183	reg = <0x0b000000 0x1000>,
	184	<0x0b002000 0x1000>;
	185	};
	186
	187	gcc: clock-controller@1800000 {
	188	compatible = "qcom,gcc-ipq4019";
	189	#clock-cells = <1>;
	190	#reset-cells = <1>;
	191	reg = <0x1800000 0x60000>;
	192	};
	193
6bfe03dd CL	194	rng@22000 {
	195	compatible = "qcom,prng";
	196	reg = <0x22000 0x140>;
	197	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	198	clock-names = "core";
	199	status = "disabled";
	200	};
	201
ba4ca27b	202	tlmm: pinctrl@1000000 {
bec6ba4c MM	203	compatible = "qcom,ipq4019-pinctrl";
	204	reg = <0x01000000 0x300000>;
	205	gpio-controller;
	206	#gpio-cells = <2>;
	207	interrupt-controller;
	208	#interrupt-cells = <2>;
18751940	209	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
bec6ba4c MM	210	};
bec6ba4c MM	211
9ca595f0 MM	212	blsp_dma: dma@7884000 {
	213	compatible = "qcom,bam-v1.7.0";
	214	reg = <0x07884000 0x23000>;
18751940	215	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
9ca595f0 MM	216	clocks = <&gcc GCC_BLSP1_AHB_CLK>;
	217	clock-names = "bam_clk";
	218	#dma-cells = <1>;
	219	qcom,ee = <0>;
	220	status = "disabled";
	221	};
	222
18751940	223	blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
13ad4fd3 MM	224	compatible = "qcom,spi-qup-v2.2.1";
	225	reg = <0x78b5000 0x600>;
	226	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	227	clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
	228	<&gcc GCC_BLSP1_AHB_CLK>;
	229	clock-names = "core", "iface";
	230	#address-cells = <1>;
	231	#size-cells = <0>;
18751940 S	232	dmas = <&blsp_dma 5>, <&blsp_dma 4>;
	233	dma-names = "rx", "tx";
	234	status = "disabled";
	235	};
	236
	237	blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
	238	compatible = "qcom,spi-qup-v2.2.1";
	239	reg = <0x78b6000 0x600>;
	240	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	241	clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
	242	<&gcc GCC_BLSP1_AHB_CLK>;
	243	clock-names = "core", "iface";
	244	#address-cells = <1>;
	245	#size-cells = <0>;
	246	dmas = <&blsp_dma 7>, <&blsp_dma 6>;
	247	dma-names = "rx", "tx";
13ad4fd3 MM	248	status = "disabled";
	249	};
	250
18751940	251	blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
e76b4284	252	compatible = "qcom,i2c-qup-v2.2.1";
650df439	253	reg = <0x78b7000 0x600>;
e76b4284 MM	254	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
e76b4284 MM	255	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
650df439	256	<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
e76b4284 MM	257	clock-names = "iface", "core";
	258	#address-cells = <1>;
	259	#size-cells = <0>;
18751940 S	260	dmas = <&blsp_dma 9>, <&blsp_dma 8>;
18751940 S	261	dma-names = "rx", "tx";
e76b4284 MM	262	status = "disabled";
	263	};
	264
18751940 S	265	blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
	266	compatible = "qcom,i2c-qup-v2.2.1";
	267	reg = <0x78b8000 0x600>;
	268	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	269	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	270	<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
	271	clock-names = "iface", "core";
	272	#address-cells = <1>;
	273	#size-cells = <0>;
	274	dmas = <&blsp_dma 11>, <&blsp_dma 10>;
	275	dma-names = "rx", "tx";
	276	status = "disabled";
	277	};
fd6fd386 MM	278
	279	cryptobam: dma@8e04000 {
	280	compatible = "qcom,bam-v1.7.0";
	281	reg = <0x08e04000 0x20000>;
18751940	282	interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
fd6fd386 MM	283	clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
	284	clock-names = "bam_clk";
	285	#dma-cells = <1>;
	286	qcom,ee = <1>;
	287	qcom,controlled-remotely;
	288	status = "disabled";
	289	};
	290
	291	crypto@8e3a000 {
	292	compatible = "qcom,crypto-v5.1";
	293	reg = <0x08e3a000 0x6000>;
	294	clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
	295	<&gcc GCC_CRYPTO_AXI_CLK>,
	296	<&gcc GCC_CRYPTO_CLK>;
	297	clock-names = "iface", "bus", "core";
	298	dmas = <&cryptobam 2>, <&cryptobam 3>;
	299	dma-names = "rx", "tx";
	300	status = "disabled";
	301	};
	302
595b30c7	303	acc0: clock-controller@b088000 {
233c77d4	304	compatible = "qcom,kpss-acc-v2";
595b30c7 MM	305	reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
	306	};
	307
	308	acc1: clock-controller@b098000 {
233c77d4	309	compatible = "qcom,kpss-acc-v2";
595b30c7 MM	310	reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
	311	};
	312
	313	acc2: clock-controller@b0a8000 {
233c77d4	314	compatible = "qcom,kpss-acc-v2";
595b30c7 MM	315	reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
	316	};
	317
	318	acc3: clock-controller@b0b8000 {
233c77d4	319	compatible = "qcom,kpss-acc-v2";
595b30c7 MM	320	reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
	321	};
	322
	323	saw0: regulator@b089000 {
	324	compatible = "qcom,saw2";
	325	reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
	326	regulator;
	327	};
	328
	329	saw1: regulator@b099000 {
	330	compatible = "qcom,saw2";
	331	reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
	332	regulator;
	333	};
	334
	335	saw2: regulator@b0a9000 {
	336	compatible = "qcom,saw2";
	337	reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
	338	regulator;
	339	};
	340
	341	saw3: regulator@b0b9000 {
	342	compatible = "qcom,saw2";
	343	reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
	344	regulator;
	345	};
	346
c696a020	347	blsp1_uart1: serial@78af000 {
bec6ba4c MM	348	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
bec6ba4c MM	349	reg = <0x78af000 0x200>;
18751940	350	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
bec6ba4c MM	351	status = "disabled";
	352	clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
	353	<&gcc GCC_BLSP1_AHB_CLK>;
	354	clock-names = "core", "iface";
9ca595f0 MM	355	dmas = <&blsp_dma 1>, <&blsp_dma 0>;
9ca595f0 MM	356	dma-names = "rx", "tx";
bec6ba4c MM	357	};
bec6ba4c MM	358
76a914b9	359	blsp1_uart2: serial@78b0000 {
bec6ba4c MM	360	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
bec6ba4c MM	361	reg = <0x78b0000 0x200>;
18751940	362	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
bec6ba4c MM	363	status = "disabled";
	364	clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
	365	<&gcc GCC_BLSP1_AHB_CLK>;
	366	clock-names = "core", "iface";
9ca595f0 MM	367	dmas = <&blsp_dma 3>, <&blsp_dma 2>;
9ca595f0 MM	368	dma-names = "rx", "tx";
bec6ba4c	369	};
40057afd MM	370
40057afd MM	371	watchdog@b017000 {
f0d9d0f4	372	compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
40057afd MM	373	reg = <0xb017000 0x40>;
	374	clocks = <&sleep_clk>;
	375	timeout-sec = <10>;
	376	status = "disabled";
	377	};
8196dd5e MM	378
	379	restart@4ab000 {
	380	compatible = "qcom,pshold";
	381	reg = <0x4ab000 0x4>;
	382	};
0d363594	383
18751940 S	384	pcie0: pci@40000000 {
	385	compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
	386	reg = <0x40000000 0xf1d
	387	0x40000f20 0xa8
	388	0x80000 0x2000
	389	0x40100000 0x1000>;
	390	reg-names = "dbi", "elbi", "parf", "config";
	391	device_type = "pci";
	392	linux,pci-domain = <0>;
	393	bus-range = <0x00 0xff>;
	394	num-lanes = <1>;
	395	#address-cells = <3>;
	396	#size-cells = <2>;
	397
	398	ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
	399	0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
	400
	401	interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
	402	interrupt-names = "msi";
	403	#interrupt-cells = <1>;
	404	interrupt-map-mask = <0 0 0 0x7>;
	405	interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	406	<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	407	<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	408	<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	409	clocks = <&gcc GCC_PCIE_AHB_CLK>,
	410	<&gcc GCC_PCIE_AXI_M_CLK>,
	411	<&gcc GCC_PCIE_AXI_S_CLK>;
	412	clock-names = "aux",
	413	"master_bus",
	414	"slave_bus";
	415
	416	resets = <&gcc PCIE_AXI_M_ARES>,
	417	<&gcc PCIE_AXI_S_ARES>,
	418	<&gcc PCIE_PIPE_ARES>,
	419	<&gcc PCIE_AXI_M_VMIDMT_ARES>,
	420	<&gcc PCIE_AXI_S_XPU_ARES>,
	421	<&gcc PCIE_PARF_XPU_ARES>,
	422	<&gcc PCIE_PHY_ARES>,
	423	<&gcc PCIE_AXI_M_STICKY_ARES>,
	424	<&gcc PCIE_PIPE_STICKY_ARES>,
	425	<&gcc PCIE_PWR_ARES>,
	426	<&gcc PCIE_AHB_ARES>,
	427	<&gcc PCIE_PHY_AHB_ARES>;
	428	reset-names = "axi_m",
	429	"axi_s",
	430	"pipe",
	431	"axi_m_vmid",
	432	"axi_s_xpu",
	433	"parf",
	434	"phy",
	435	"axi_m_sticky",
	436	"pipe_sticky",
	437	"pwr",
	438	"ahb",
	439	"phy_ahb";
	440
	441	status = "disabled";
	442	};
	443
	444	qpic_bam: dma@7984000 {
	445	compatible = "qcom,bam-v1.7.0";
	446	reg = <0x7984000 0x1a000>;
	447	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
448	clocks = <&gcc GCC_QPIC_CLK>;
449	clock-names = "bam_clk";
450	#dma-cells = <1>;
451	qcom,ee = <0>;
452	status = "disabled";
453	};
454
455	nand: qpic-nand@79b0000 {
456	compatible = "qcom,ipq4019-nand";
457	reg = <0x79b0000 0x1000>;
458	#address-cells = <1>;
459	#size-cells = <0>;
460	clocks = <&gcc GCC_QPIC_CLK>,
461	<&gcc GCC_QPIC_AHB_CLK>;
462	clock-names = "core", "aon";
463
464	dmas = <&qpic_bam 0>,
465	<&qpic_bam 1>,
466	<&qpic_bam 2>;
467	dma-names = "tx", "rx", "cmd";
468	status = "disabled";
469
470	nand@0 {
471	reg = <0>;
472
473	nand-ecc-strength = <4>;
474	nand-ecc-step-size = <512>;
475	nand-bus-width = <8>;
476	};
477	};
478
0d363594 CL	479	wifi0: wifi@a000000 {
	480	compatible = "qcom,ipq4019-wifi";
	481	reg = <0xa000000 0x200000>;
	482	resets = <&gcc WIFI0_CPU_INIT_RESET>,
	483	<&gcc WIFI0_RADIO_SRIF_RESET>,
	484	<&gcc WIFI0_RADIO_WARM_RESET>,
	485	<&gcc WIFI0_RADIO_COLD_RESET>,
	486	<&gcc WIFI0_CORE_WARM_RESET>,
	487	<&gcc WIFI0_CORE_COLD_RESET>;
	488	reset-names = "wifi_cpu_init", "wifi_radio_srif",
	489	"wifi_radio_warm", "wifi_radio_cold",
	490	"wifi_core_warm", "wifi_core_cold";
	491	clocks = <&gcc GCC_WCSS2G_CLK>,
	492	<&gcc GCC_WCSS2G_REF_CLK>,
	493	<&gcc GCC_WCSS2G_RTC_CLK>;
	494	clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
	495	"wifi_wcss_rtc";
	496	interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
	497	<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
	498	<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
	499	<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
	500	<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
	501	<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
	502	<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
	503	<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
	504	<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
	505	<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
	506	<GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
	507	<GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
	508	<GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
	509	<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
	510	<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
	511	<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
18751940	512	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
0d363594 CL	513	interrupt-names = "msi0", "msi1", "msi2", "msi3",
	514	"msi4", "msi5", "msi6", "msi7",
	515	"msi8", "msi9", "msi10", "msi11",
	516	"msi12", "msi13", "msi14", "msi15",
	517	"legacy";
	518	status = "disabled";
	519	};
	520
	521	wifi1: wifi@a800000 {
	522	compatible = "qcom,ipq4019-wifi";
	523	reg = <0xa800000 0x200000>;
	524	resets = <&gcc WIFI1_CPU_INIT_RESET>,
	525	<&gcc WIFI1_RADIO_SRIF_RESET>,
	526	<&gcc WIFI1_RADIO_WARM_RESET>,
	527	<&gcc WIFI1_RADIO_COLD_RESET>,
	528	<&gcc WIFI1_CORE_WARM_RESET>,
	529	<&gcc WIFI1_CORE_COLD_RESET>;
	530	reset-names = "wifi_cpu_init", "wifi_radio_srif",
	531	"wifi_radio_warm", "wifi_radio_cold",
	532	"wifi_core_warm", "wifi_core_cold";
	533	clocks = <&gcc GCC_WCSS5G_CLK>,
	534	<&gcc GCC_WCSS5G_REF_CLK>,
	535	<&gcc GCC_WCSS5G_RTC_CLK>;
	536	clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
	537	"wifi_wcss_rtc";
	538	interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
	539	<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
	540	<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
	541	<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
	542	<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
	543	<GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
	544	<GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
	545	<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
	546	<GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
	547	<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
	548	<GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
	549	<GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
	550	<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
	551	<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
	552	<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
	553	<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
18751940	554	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
0d363594 CL	555	interrupt-names = "msi0", "msi1", "msi2", "msi3",
	556	"msi4", "msi5", "msi6", "msi7",
	557	"msi8", "msi9", "msi10", "msi11",
	558	"msi12", "msi13", "msi14", "msi15",
	559	"legacy";
	560	status = "disabled";
	561	};
bec6ba4c MM	562	};
bec6ba4c MM	563	};