[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / qcom-ipq8064.dtsi

/dts-v1/;

#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
#include <dt-bindings/soc/qcom,gsbi.h>

/ {
	model = "Qualcomm IPQ8064";
	compatible = "qcom,ipq8064";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 10 0x304>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		nss@40000000 {
			reg = <0x40000000 0x1000000>;
			no-map;
		};

		smem@41000000 {
			reg = <0x41000000 0x200000>;
			no-map;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		qcom_pinmux: pinmux@800000 {
			compatible = "qcom,ipq8064-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 16 0x4>;
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer", "qcom,msm-timer";
			interrupts = <1 1 0x301>,
				     <1 2 0x301>,
				     <1 3 0x301>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <25000000>,
					  <32768>;
			cpu-offset = <0x80000>;
		};

		acc0: clock-controller@2088000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
		};

		acc1: clock-controller@2098000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
		};

		saw0: regulator@2089000 {
			compatible = "qcom,saw2";
			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw1: regulator@2099000 {
			compatible = "qcom,saw2";
			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		gsbi2: gsbi@12480000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x12480000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			syscon-tcsr = <&tcsr>;

			serial@12490000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x12490000 0x1000>,
				      <0x12480000 0x1000>;
				interrupts = <0 195 0x0>;
				clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			i2c@124a0000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x124a0000 0x1000>;
				interrupts = <0 196 0>;

				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";

				#address-cells = <1>;
				#size-cells = <0>;
			};

		};

		gsbi4: gsbi@16300000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <4>;
			reg = <0x16300000 0x100>;
			clocks = <&gcc GSBI4_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			syscon-tcsr = <&tcsr>;

			serial@16340000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16340000 0x1000>,
				      <0x16300000 0x1000>;
				interrupts = <0 152 0x0>;
				clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			i2c@16380000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x16380000 0x1000>;
				interrupts = <0 153 0>;

				clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";

				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi5: gsbi@1a200000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <5>;
			reg = <0x1a200000 0x100>;
			clocks = <&gcc GSBI5_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			syscon-tcsr = <&tcsr>;

			serial@1a240000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x1a240000 0x1000>,
				      <0x1a200000 0x1000>;
				interrupts = <0 154 0x0>;
				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			i2c@1a280000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x1a280000 0x1000>;
				interrupts = <0 155 0>;

				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";

				#address-cells = <1>;
				#size-cells = <0>;
			};

			spi@1a280000 {
				compatible = "qcom,spi-qup-v1.1.1";
				reg = <0x1a280000 0x1000>;
				interrupts = <0 155 0>;

				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";

				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		sata_phy: sata-phy@1b400000 {
			compatible = "qcom,ipq806x-sata-phy";
			reg = <0x1b400000 0x200>;

			clocks = <&gcc SATA_PHY_CFG_CLK>;
			clock-names = "cfg";

			#phy-cells = <0>;
			status = "disabled";
		};

		sata@29000000 {
			compatible = "qcom,ipq806x-ahci", "generic-ahci";
			reg = <0x29000000 0x180>;

			interrupts = <0 209 0x0>;

			clocks = <&gcc SFAB_SATA_S_H_CLK>,
				 <&gcc SATA_H_CLK>,
				 <&gcc SATA_A_CLK>,
				 <&gcc SATA_RXOOB_CLK>,
				 <&gcc SATA_PMALIVE_CLK>;
			clock-names = "slave_face", "iface", "core",
					"rxoob", "pmalive";

			assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
			assigned-clock-rates = <100000000>, <100000000>;

			phys = <&sata_phy>;
			phy-names = "sata-phy";
			status = "disabled";
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x00500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-ipq8064";
			reg = <0x00900000 0x4000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-ipq8064", "syscon";
			reg = <0x1a400000 0x100>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-ipq8064";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

	};
};
Commit	Line	Data
68de308b KG	1	/dts-v1/;
	2
	3	#include "skeleton.dtsi"
	4	#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
	5	#include <dt-bindings/soc/qcom,gsbi.h>
	6
	7	/ {
	8	model = "Qualcomm IPQ8064";
	9	compatible = "qcom,ipq8064";
	10	interrupt-parent = <&intc>;
	11
	12	cpus {
	13	#address-cells = <1>;
	14	#size-cells = <0>;
	15
	16	cpu@0 {
	17	compatible = "qcom,krait";
	18	enable-method = "qcom,kpss-acc-v1";
	19	device_type = "cpu";
	20	reg = <0>;
	21	next-level-cache = <&L2>;
	22	qcom,acc = <&acc0>;
	23	qcom,saw = <&saw0>;
	24	};
	25
	26	cpu@1 {
	27	compatible = "qcom,krait";
	28	enable-method = "qcom,kpss-acc-v1";
	29	device_type = "cpu";
	30	reg = <1>;
	31	next-level-cache = <&L2>;
	32	qcom,acc = <&acc1>;
	33	qcom,saw = <&saw1>;
	34	};
	35
	36	L2: l2-cache {
	37	compatible = "cache";
	38	cache-level = <2>;
	39	};
	40	};
	41
	42	cpu-pmu {
	43	compatible = "qcom,krait-pmu";
	44	interrupts = <1 10 0x304>;
	45	};
	46
	47	reserved-memory {
	48	#address-cells = <1>;
	49	#size-cells = <1>;
	50	ranges;
	51
	52	nss@40000000 {
	53	reg = <0x40000000 0x1000000>;
	54	no-map;
	55	};
	56
	57	smem@41000000 {
	58	reg = <0x41000000 0x200000>;
	59	no-map;
	60	};
	61	};
	62
	63	soc: soc {
	64	#address-cells = <1>;
65	#size-cells = <1>;
66	ranges;
67	compatible = "simple-bus";
68
69	qcom_pinmux: pinmux@800000 {
70	compatible = "qcom,ipq8064-pinctrl";
71	reg = <0x800000 0x4000>;
72
73	gpio-controller;
74	#gpio-cells = <2>;
75	interrupt-controller;
76	#interrupt-cells = <2>;
bb901bd6	77	interrupts = <0 16 0x4>;
68de308b KG	78	};
	79
	80	intc: interrupt-controller@2000000 {
	81	compatible = "qcom,msm-qgic2";
	82	interrupt-controller;
	83	#interrupt-cells = <3>;
	84	reg = <0x02000000 0x1000>,
	85	<0x02002000 0x1000>;
	86	};
	87
	88	timer@200a000 {
	89	compatible = "qcom,kpss-timer", "qcom,msm-timer";
	90	interrupts = <1 1 0x301>,
	91	<1 2 0x301>,
	92	<1 3 0x301>;
	93	reg = <0x0200a000 0x100>;
	94	clock-frequency = <25000000>,
	95	<32768>;
	96	cpu-offset = <0x80000>;
	97	};
	98
	99	acc0: clock-controller@2088000 {
	100	compatible = "qcom,kpss-acc-v1";
	101	reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
	102	};
	103
	104	acc1: clock-controller@2098000 {
	105	compatible = "qcom,kpss-acc-v1";
	106	reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
	107	};
	108
	109	saw0: regulator@2089000 {
	110	compatible = "qcom,saw2";
	111	reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
	112	regulator;
	113	};
	114
	115	saw1: regulator@2099000 {
	116	compatible = "qcom,saw2";
	117	reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
	118	regulator;
	119	};
	120
	121	gsbi2: gsbi@12480000 {
	122	compatible = "qcom,gsbi-v1.0.0";
4d9b766b	123	cell-index = <2>;
68de308b KG	124	reg = <0x12480000 0x100>;
	125	clocks = <&gcc GSBI2_H_CLK>;
	126	clock-names = "iface";
	127	#address-cells = <1>;
	128	#size-cells = <1>;
	129	ranges;
	130	status = "disabled";
	131
4d9b766b AG	132	syscon-tcsr = <&tcsr>;
4d9b766b AG	133
68de308b KG	134	serial@12490000 {
	135	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	136	reg = <0x12490000 0x1000>,
	137	<0x12480000 0x1000>;
	138	interrupts = <0 195 0x0>;
	139	clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
	140	clock-names = "core", "iface";
	141	status = "disabled";
	142	};
	143
	144	i2c@124a0000 {
	145	compatible = "qcom,i2c-qup-v1.1.1";
	146	reg = <0x124a0000 0x1000>;
	147	interrupts = <0 196 0>;
	148
	149	clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
	150	clock-names = "core", "iface";
	151	status = "disabled";
	152
	153	#address-cells = <1>;
	154	#size-cells = <0>;
	155	};
	156
	157	};
	158
	159	gsbi4: gsbi@16300000 {
	160	compatible = "qcom,gsbi-v1.0.0";
4d9b766b	161	cell-index = <4>;
68de308b KG	162	reg = <0x16300000 0x100>;
	163	clocks = <&gcc GSBI4_H_CLK>;
	164	clock-names = "iface";
	165	#address-cells = <1>;
	166	#size-cells = <1>;
	167	ranges;
	168	status = "disabled";
	169
4d9b766b AG	170	syscon-tcsr = <&tcsr>;
4d9b766b AG	171
68de308b KG	172	serial@16340000 {
	173	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	174	reg = <0x16340000 0x1000>,
	175	<0x16300000 0x1000>;
	176	interrupts = <0 152 0x0>;
	177	clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
	178	clock-names = "core", "iface";
	179	status = "disabled";
	180	};
	181
	182	i2c@16380000 {
	183	compatible = "qcom,i2c-qup-v1.1.1";
	184	reg = <0x16380000 0x1000>;
	185	interrupts = <0 153 0>;
	186
	187	clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
	188	clock-names = "core", "iface";
	189	status = "disabled";
	190
	191	#address-cells = <1>;
	192	#size-cells = <0>;
	193	};
	194	};
	195
	196	gsbi5: gsbi@1a200000 {
	197	compatible = "qcom,gsbi-v1.0.0";
4d9b766b	198	cell-index = <5>;
68de308b KG	199	reg = <0x1a200000 0x100>;
	200	clocks = <&gcc GSBI5_H_CLK>;
	201	clock-names = "iface";
	202	#address-cells = <1>;
	203	#size-cells = <1>;
	204	ranges;
	205	status = "disabled";
	206
4d9b766b AG	207	syscon-tcsr = <&tcsr>;
4d9b766b AG	208
68de308b KG	209	serial@1a240000 {
	210	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	211	reg = <0x1a240000 0x1000>,
	212	<0x1a200000 0x1000>;
	213	interrupts = <0 154 0x0>;
	214	clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
	215	clock-names = "core", "iface";
	216	status = "disabled";
	217	};
	218
	219	i2c@1a280000 {
	220	compatible = "qcom,i2c-qup-v1.1.1";
	221	reg = <0x1a280000 0x1000>;
	222	interrupts = <0 155 0>;
	223
	224	clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
	225	clock-names = "core", "iface";
	226	status = "disabled";
	227
	228	#address-cells = <1>;
	229	#size-cells = <0>;
	230	};
	231
	232	spi@1a280000 {
	233	compatible = "qcom,spi-qup-v1.1.1";
	234	reg = <0x1a280000 0x1000>;
	235	interrupts = <0 155 0>;
	236
	237	clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
	238	clock-names = "core", "iface";
	239	status = "disabled";
	240
	241	#address-cells = <1>;
	242	#size-cells = <0>;
	243	};
	244	};
	245
e512448f KG	246	sata_phy: sata-phy@1b400000 {
	247	compatible = "qcom,ipq806x-sata-phy";
	248	reg = <0x1b400000 0x200>;
	249
	250	clocks = <&gcc SATA_PHY_CFG_CLK>;
	251	clock-names = "cfg";
	252
	253	#phy-cells = <0>;
	254	status = "disabled";
	255	};
	256
	257	sata@29000000 {
	258	compatible = "qcom,ipq806x-ahci", "generic-ahci";
	259	reg = <0x29000000 0x180>;
	260
	261	interrupts = <0 209 0x0>;
	262
	263	clocks = <&gcc SFAB_SATA_S_H_CLK>,
	264	<&gcc SATA_H_CLK>,
	265	<&gcc SATA_A_CLK>,
	266	<&gcc SATA_RXOOB_CLK>,
	267	<&gcc SATA_PMALIVE_CLK>;
	268	clock-names = "slave_face", "iface", "core",
	269	"rxoob", "pmalive";
	270
	271	assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
	272	assigned-clock-rates = <100000000>, <100000000>;
	273
	274	phys = <&sata_phy>;
	275	phy-names = "sata-phy";
	276	status = "disabled";
	277	};
	278
68de308b KG	279	qcom,ssbi@500000 {
	280	compatible = "qcom,ssbi";
	281	reg = <0x00500000 0x1000>;
	282	qcom,controller-type = "pmic-arbiter";
	283	};
	284
	285	gcc: clock-controller@900000 {
	286	compatible = "qcom,gcc-ipq8064";
	287	reg = <0x00900000 0x4000>;
	288	#clock-cells = <1>;
	289	#reset-cells = <1>;
	290	};
4d9b766b AG	291
	292	tcsr: syscon@1a400000 {
	293	compatible = "qcom,tcsr-ipq8064", "syscon";
	294	reg = <0x1a400000 0x100>;
	295	};
1e1177bf KG	296
	297	lcc: clock-controller@28000000 {
	298	compatible = "qcom,lcc-ipq8064";
	299	reg = <0x28000000 0x1000>;
	300	#clock-cells = <1>;
	301	#reset-cells = <1>;
	302	};
	303
68de308b KG	304	};
68de308b KG	305	};