[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / qcom-msm8660.dtsi

// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

/include/ "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
#include <dt-bindings/soc/qcom,gsbi.h>

/ {
	model = "Qualcomm MSM8660";
	compatible = "qcom,msm8660";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "qcom,scorpion";
			enable-method = "qcom,gcc-msm8660";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			compatible = "qcom,scorpion";
			enable-method = "qcom,gcc-msm8660";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	cpu-pmu {
		compatible = "qcom,scorpion-mp-pmu";
		interrupts = <1 9 0x304>;
	};

	clocks {
		cxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		pxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	/*
	 * These channels from the ADC are simply hardware monitors.
	 * That is why the ADC is referred to as "HKADC" - HouseKeeping
	 * ADC.
	 */
	iio-hwmon {
		compatible = "iio-hwmon";
		io-channels = <&xoadc 0x00 0x01>, /* Battery */
			    <&xoadc 0x00 0x02>, /* DC in (charger) */
			    <&xoadc 0x00 0x04>, /* VPH the main system voltage */
			    <&xoadc 0x00 0x0b>, /* Die temperature */
			    <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
			    <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
			    <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@2080000 {
			compatible = "qcom,msm-8660-qgic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = < 0x02080000 0x1000 >,
			      < 0x02081000 0x1000 >;
		};

		timer@2000000 {
			compatible = "qcom,scss-timer", "qcom,msm-timer";
			interrupts = <1 0 0x301>,
				     <1 1 0x301>,
				     <1 2 0x301>;
			reg = <0x02000000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x40000>;
		};

		tlmm: pinctrl@800000 {
			compatible = "qcom,msm8660-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <0 16 0x4>;
			interrupt-controller;
			#interrupt-cells = <2>;

		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-msm8660";
			#clock-cells = <1>;
			#reset-cells = <1>;
			reg = <0x900000 0x4000>;
		};

		gsbi6: gsbi@16500000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <12>;
			reg = <0x16500000 0x100>;
			clocks = <&gcc GSBI6_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi6_serial: serial@16540000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16540000 0x1000>,
				      <0x16500000 0x1000>;
				interrupts = <GIC_SPI 156 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi6_i2c: i2c@16580000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x16580000 0x1000>;
				interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gsbi7: gsbi@16600000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <12>;
			reg = <0x16600000 0x100>;
			clocks = <&gcc GSBI7_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi7_serial: serial@16640000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16640000 0x1000>,
				      <0x16600000 0x1000>;
				interrupts = <GIC_SPI 158 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi7_i2c: i2c@16680000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x16680000 0x1000>;
				interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gsbi8: gsbi@19800000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <12>;
			reg = <0x19800000 0x100>;
			clocks = <&gcc GSBI8_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi8_i2c: i2c@19880000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x19880000 0x1000>;
				interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gsbi12: gsbi@19c00000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <12>;
			reg = <0x19c00000 0x100>;
			clocks = <&gcc GSBI12_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi12_serial: serial@19c40000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x19c40000 0x1000>,
				      <0x19c00000 0x1000>;
				interrupts = <0 195 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi12_i2c: i2c@19c80000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x19c80000 0x1000>;
				interrupts = <0 196 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		external-bus@1a100000 {
			compatible = "qcom,msm8660-ebi2";
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0 0x0 0x1a800000 0x00800000>,
				 <1 0x0 0x1b000000 0x00800000>,
				 <2 0x0 0x1b800000 0x00800000>,
				 <3 0x0 0x1d000000 0x08000000>,
				 <4 0x0 0x1c800000 0x00800000>,
				 <5 0x0 0x1c000000 0x00800000>;
			reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
			reg-names = "ebi2", "xmem";
			clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
			clock-names = "ebi2x", "ebi2";
			status = "disabled";
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pm8058: pmic@0 {
				compatible = "qcom,pm8058";
				interrupt-parent = <&tlmm>;
				interrupts = <88 8>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pm8058_gpio: gpio@150 {
					compatible = "qcom,pm8058-gpio",
						     "qcom,ssbi-gpio";
					reg = <0x150>;
					interrupt-parent = <&pm8058>;
					interrupts = <192 IRQ_TYPE_NONE>,
						     <193 IRQ_TYPE_NONE>,
						     <194 IRQ_TYPE_NONE>,
						     <195 IRQ_TYPE_NONE>,
						     <196 IRQ_TYPE_NONE>,
						     <197 IRQ_TYPE_NONE>,
						     <198 IRQ_TYPE_NONE>,
						     <199 IRQ_TYPE_NONE>,
						     <200 IRQ_TYPE_NONE>,
						     <201 IRQ_TYPE_NONE>,
						     <202 IRQ_TYPE_NONE>,
						     <203 IRQ_TYPE_NONE>,
						     <204 IRQ_TYPE_NONE>,
						     <205 IRQ_TYPE_NONE>,
						     <206 IRQ_TYPE_NONE>,
						     <207 IRQ_TYPE_NONE>,
						     <208 IRQ_TYPE_NONE>,
						     <209 IRQ_TYPE_NONE>,
						     <210 IRQ_TYPE_NONE>,
						     <211 IRQ_TYPE_NONE>,
						     <212 IRQ_TYPE_NONE>,
						     <213 IRQ_TYPE_NONE>,
						     <214 IRQ_TYPE_NONE>,
						     <215 IRQ_TYPE_NONE>,
						     <216 IRQ_TYPE_NONE>,
						     <217 IRQ_TYPE_NONE>,
						     <218 IRQ_TYPE_NONE>,
						     <219 IRQ_TYPE_NONE>,
						     <220 IRQ_TYPE_NONE>,
						     <221 IRQ_TYPE_NONE>,
						     <222 IRQ_TYPE_NONE>,
						     <223 IRQ_TYPE_NONE>,
						     <224 IRQ_TYPE_NONE>,
						     <225 IRQ_TYPE_NONE>,
						     <226 IRQ_TYPE_NONE>,
						     <227 IRQ_TYPE_NONE>,
						     <228 IRQ_TYPE_NONE>,
						     <229 IRQ_TYPE_NONE>,
						     <230 IRQ_TYPE_NONE>,
						     <231 IRQ_TYPE_NONE>,
						     <232 IRQ_TYPE_NONE>,
						     <233 IRQ_TYPE_NONE>,
						     <234 IRQ_TYPE_NONE>,
						     <235 IRQ_TYPE_NONE>;
					gpio-controller;
					#gpio-cells = <2>;

				};

				pm8058_mpps: mpps@50 {
					compatible = "qcom,pm8058-mpp",
						     "qcom,ssbi-mpp";
					reg = <0x50>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-parent = <&pm8058>;
					interrupts =
					<128 IRQ_TYPE_NONE>,
					<129 IRQ_TYPE_NONE>,
					<130 IRQ_TYPE_NONE>,
					<131 IRQ_TYPE_NONE>,
					<132 IRQ_TYPE_NONE>,
					<133 IRQ_TYPE_NONE>,
					<134 IRQ_TYPE_NONE>,
					<135 IRQ_TYPE_NONE>,
					<136 IRQ_TYPE_NONE>,
					<137 IRQ_TYPE_NONE>,
					<138 IRQ_TYPE_NONE>,
					<139 IRQ_TYPE_NONE>;
				};

				pwrkey@1c {
					compatible = "qcom,pm8058-pwrkey";
					reg = <0x1c>;
					interrupt-parent = <&pm8058>;
					interrupts = <50 1>, <51 1>;
					debounce = <15625>;
					pull-up;
				};

				keypad@148 {
					compatible = "qcom,pm8058-keypad";
					reg = <0x148>;
					interrupt-parent = <&pm8058>;
					interrupts = <74 1>, <75 1>;
					debounce = <15>;
					scan-delay = <32>;
					row-hold = <91500>;
				};

				xoadc: xoadc@197 {
					compatible = "qcom,pm8058-adc";
					reg = <0x197>;
					interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
					#address-cells = <2>;
					#size-cells = <0>;
					#io-channel-cells = <2>;

					vcoin: adc-channel@0 {
						reg = <0x00 0x00>;
					};
					vbat: adc-channel@1 {
						reg = <0x00 0x01>;
					};
					dcin: adc-channel@2 {
						reg = <0x00 0x02>;
					};
					ichg: adc-channel@3 {
						reg = <0x00 0x03>;
					};
					vph_pwr: adc-channel@4 {
						reg = <0x00 0x04>;
					};
					usb_vbus: adc-channel@a {
						reg = <0x00 0x0a>;
					};
					die_temp: adc-channel@b {
						reg = <0x00 0x0b>;
					};
					ref_625mv: adc-channel@c {
						reg = <0x00 0x0c>;
					};
					ref_1250mv: adc-channel@d {
						reg = <0x00 0x0d>;
					};
					ref_325mv: adc-channel@e {
						reg = <0x00 0x0e>;
					};
					ref_muxoff: adc-channel@f {
						reg = <0x00 0x0f>;
					};
				};

				rtc@1e8 {
					compatible = "qcom,pm8058-rtc";
					reg = <0x1e8>;
					interrupt-parent = <&pm8058>;
					interrupts = <39 1>;
					allow-set-time;
				};

				vibrator@4a {
					compatible = "qcom,pm8058-vib";
					reg = <0x4a>;
				};
			};
		};

		l2cc: clock-controller@2082000 {
			compatible	= "syscon";
			reg		= <0x02082000 0x1000>;
		};

		rpm: rpm@104000 {
			compatible	= "qcom,rpm-msm8660";
			reg		= <0x00104000 0x1000>;
			qcom,ipc	= <&l2cc 0x8 2>;

			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names	= "ack", "err", "wakeup";
			clocks = <&gcc RPM_MSG_RAM_H_CLK>;
			clock-names = "ram";

			rpmcc: clock-controller {
				compatible	= "qcom,rpmcc-msm8660", "qcom,rpmcc";
				#clock-cells = <1>;
			};

			pm8901-regulators {
				compatible = "qcom,rpm-pm8901-regulators";

				pm8901_l0: l0 {};
				pm8901_l1: l1 {};
				pm8901_l2: l2 {};
				pm8901_l3: l3 {};
				pm8901_l4: l4 {};
				pm8901_l5: l5 {};
				pm8901_l6: l6 {};

				/* S0 and S1 Handled as SAW regulators by SPM */
				pm8901_s2: s2 {};
				pm8901_s3: s3 {};
				pm8901_s4: s4 {};

				pm8901_lvs0: lvs0 {};
				pm8901_lvs1: lvs1 {};
				pm8901_lvs2: lvs2 {};
				pm8901_lvs3: lvs3 {};

				pm8901_mvs: mvs {};
			};

			pm8058-regulators {
				compatible = "qcom,rpm-pm8058-regulators";

				pm8058_l0: l0 {};
				pm8058_l1: l1 {};
				pm8058_l2: l2 {};
				pm8058_l3: l3 {};
				pm8058_l4: l4 {};
				pm8058_l5: l5 {};
				pm8058_l6: l6 {};
				pm8058_l7: l7 {};
				pm8058_l8: l8 {};
				pm8058_l9: l9 {};
				pm8058_l10: l10 {};
				pm8058_l11: l11 {};
				pm8058_l12: l12 {};
				pm8058_l13: l13 {};
				pm8058_l14: l14 {};
				pm8058_l15: l15 {};
				pm8058_l16: l16 {};
				pm8058_l17: l17 {};
				pm8058_l18: l18 {};
				pm8058_l19: l19 {};
				pm8058_l20: l20 {};
				pm8058_l21: l21 {};
				pm8058_l22: l22 {};
				pm8058_l23: l23 {};
				pm8058_l24: l24 {};
				pm8058_l25: l25 {};

				pm8058_s0: s0 {};
				pm8058_s1: s1 {};
				pm8058_s2: s2 {};
				pm8058_s3: s3 {};
				pm8058_s4: s4 {};

				pm8058_lvs0: lvs0 {};
				pm8058_lvs1: lvs1 {};

				pm8058_ncp: ncp {};
			};
		};

		amba {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			sdcc1: sdcc@12400000 {
				status		= "disabled";
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg		= <0x12400000 0x8000>;
				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <8>;
				max-frequency	= <48000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
			};

			sdcc2: sdcc@12140000 {
				status		= "disabled";
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg		= <0x12140000 0x8000>;
				interrupts	= <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <8>;
				max-frequency	= <48000000>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
			};

			sdcc3: sdcc@12180000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12180000 0x8000>;
				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <48000000>;
				no-1-8-v;
			};

			sdcc4: sdcc@121c0000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x121c0000 0x8000>;
				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				max-frequency	= <48000000>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
			};

			sdcc5: sdcc@12200000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12200000 0x8000>;
				interrupts	= <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <48000000>;
			};
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-msm8660", "syscon";
			reg = <0x1a400000 0x100>;
		};
	};

};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
cc60a1a4 KG	2	/dts-v1/;
	3
	4	/include/ "skeleton.dtsi"
	5
dcf5907e	6	#include <dt-bindings/interrupt-controller/irq.h>
55602a09	7	#include <dt-bindings/interrupt-controller/arm-gic.h>
cc60a1a4	8	#include <dt-bindings/clock/qcom,gcc-msm8660.h>
66a6c317	9	#include <dt-bindings/soc/qcom,gsbi.h>
cc60a1a4 KG	10
	11	/ {
	12	model = "Qualcomm MSM8660";
	13	compatible = "qcom,msm8660";
	14	interrupt-parent = <&intc>;
	15
2ab27991 RV	16	cpus {
	17	#address-cells = <1>;
	18	#size-cells = <0>;
2ab27991 RV	19
2ab27991 RV	20	cpu@0 {
66a6c317 KG	21	compatible = "qcom,scorpion";
66a6c317 KG	22	enable-method = "qcom,gcc-msm8660";
2ab27991 RV	23	device_type = "cpu";
	24	reg = <0>;
	25	next-level-cache = <&L2>;
	26	};
	27
	28	cpu@1 {
66a6c317 KG	29	compatible = "qcom,scorpion";
66a6c317 KG	30	enable-method = "qcom,gcc-msm8660";
2ab27991 RV	31	device_type = "cpu";
	32	reg = <1>;
	33	next-level-cache = <&L2>;
	34	};
	35
	36	L2: l2-cache {
	37	compatible = "cache";
	38	cache-level = <2>;
	39	};
	40	};
	41
b73b3157 SB	42	cpu-pmu {
	43	compatible = "qcom,scorpion-mp-pmu";
	44	interrupts = <1 9 0x304>;
	45	};
	46
30fc4212 SB	47	clocks {
	48	cxo_board {
	49	compatible = "fixed-clock";
	50	#clock-cells = <0>;
	51	clock-frequency = <19200000>;
	52	};
	53
	54	pxo_board {
	55	compatible = "fixed-clock";
	56	#clock-cells = <0>;
	57	clock-frequency = <27000000>;
	58	};
	59
	60	sleep_clk {
	61	compatible = "fixed-clock";
	62	#clock-cells = <0>;
	63	clock-frequency = <32768>;
	64	};
	65	};
	66
6d78cea6 LW	67	/*
	68	* These channels from the ADC are simply hardware monitors.
	69	* That is why the ADC is referred to as "HKADC" - HouseKeeping
	70	* ADC.
	71	*/
	72	iio-hwmon {
	73	compatible = "iio-hwmon";
	74	io-channels = <&xoadc 0x00 0x01>, /* Battery */
	75	<&xoadc 0x00 0x02>, /* DC in (charger) */
	76	<&xoadc 0x00 0x04>, /* VPH the main system voltage */
	77	<&xoadc 0x00 0x0b>, /* Die temperature */
	78	<&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
	79	<&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
	80	<&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
	81	};
	82
66a6c317 KG	83	soc: soc {
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	ranges;
	87	compatible = "simple-bus";
cc60a1a4	88
66a6c317 KG	89	intc: interrupt-controller@2080000 {
	90	compatible = "qcom,msm-8660-qgic";
	91	interrupt-controller;
	92	#interrupt-cells = <3>;
	93	reg = < 0x02080000 0x1000 >,
	94	< 0x02081000 0x1000 >;
	95	};
cc60a1a4	96
66a6c317 KG	97	timer@2000000 {
	98	compatible = "qcom,scss-timer", "qcom,msm-timer";
	99	interrupts = <1 0 0x301>,
	100	<1 1 0x301>,
	101	<1 2 0x301>;
	102	reg = <0x02000000 0x100>;
	103	clock-frequency = <27000000>,
	104	<32768>;
	105	cpu-offset = <0x40000>;
	106	};
cc60a1a4	107
8e140c8e BA	108	tlmm: pinctrl@800000 {
	109	compatible = "qcom,msm8660-pinctrl";
	110	reg = <0x800000 0x4000>;
	111
66a6c317 KG	112	gpio-controller;
66a6c317 KG	113	#gpio-cells = <2>;
66a6c317 KG	114	interrupts = <0 16 0x4>;
	115	interrupt-controller;
	116	#interrupt-cells = <2>;
8e140c8e	117
66a6c317	118	};
cc60a1a4	119
66a6c317 KG	120	gcc: clock-controller@900000 {
	121	compatible = "qcom,gcc-msm8660";
	122	#clock-cells = <1>;
	123	#reset-cells = <1>;
	124	reg = <0x900000 0x4000>;
	125	};
	126
0adb9243 LW	127	gsbi6: gsbi@16500000 {
	128	compatible = "qcom,gsbi-v1.0.0";
	129	cell-index = <12>;
	130	reg = <0x16500000 0x100>;
	131	clocks = <&gcc GSBI6_H_CLK>;
	132	clock-names = "iface";
	133	#address-cells = <1>;
	134	#size-cells = <1>;
	135	ranges;
	136
	137	syscon-tcsr = <&tcsr>;
	138
	139	gsbi6_serial: serial@16540000 {
	140	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	141	reg = <0x16540000 0x1000>,
	142	<0x16500000 0x1000>;
	143	interrupts = <GIC_SPI 156 IRQ_TYPE_NONE>;
	144	clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
	145	clock-names = "core", "iface";
	146	status = "disabled";
	147	};
	148
	149	gsbi6_i2c: i2c@16580000 {
	150	compatible = "qcom,i2c-qup-v1.1.1";
	151	reg = <0x16580000 0x1000>;
	152	interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
	153	clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
	154	clock-names = "core", "iface";
	155	#address-cells = <1>;
	156	#size-cells = <0>;
	157	status = "disabled";
	158	};
	159	};
	160
	161	gsbi7: gsbi@16600000 {
	162	compatible = "qcom,gsbi-v1.0.0";
	163	cell-index = <12>;
	164	reg = <0x16600000 0x100>;
	165	clocks = <&gcc GSBI7_H_CLK>;
	166	clock-names = "iface";
	167	#address-cells = <1>;
	168	#size-cells = <1>;
	169	ranges;
	170
	171	syscon-tcsr = <&tcsr>;
	172
	173	gsbi7_serial: serial@16640000 {
	174	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	175	reg = <0x16640000 0x1000>,
	176	<0x16600000 0x1000>;
	177	interrupts = <GIC_SPI 158 IRQ_TYPE_NONE>;
	178	clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
	179	clock-names = "core", "iface";
	180	status = "disabled";
	181	};
	182
	183	gsbi7_i2c: i2c@16680000 {
	184	compatible = "qcom,i2c-qup-v1.1.1";
	185	reg = <0x16680000 0x1000>;
	186	interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
	187	clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
	188	clock-names = "core", "iface";
	189	#address-cells = <1>;
	190	#size-cells = <0>;
191	status = "disabled";
192	};
193	};
55942072 LW	194
	195	gsbi8: gsbi@19800000 {
	196	compatible = "qcom,gsbi-v1.0.0";
	197	cell-index = <12>;
	198	reg = <0x19800000 0x100>;
	199	clocks = <&gcc GSBI8_H_CLK>;
	200	clock-names = "iface";
	201	#address-cells = <1>;
	202	#size-cells = <1>;
	203	ranges;
	204
	205	syscon-tcsr = <&tcsr>;
	206
	207	gsbi8_i2c: i2c@19880000 {
	208	compatible = "qcom,i2c-qup-v1.1.1";
	209	reg = <0x19880000 0x1000>;
	210	interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>;
	211	clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
	212	clock-names = "core", "iface";
	213	#address-cells = <1>;
	214	#size-cells = <0>;
	215	status = "disabled";
	216	};
	217	};
	218
66a6c317 KG	219	gsbi12: gsbi@19c00000 {
66a6c317 KG	220	compatible = "qcom,gsbi-v1.0.0";
da047acd	221	cell-index = <12>;
66a6c317 KG	222	reg = <0x19c00000 0x100>;
	223	clocks = <&gcc GSBI12_H_CLK>;
	224	clock-names = "iface";
	225	#address-cells = <1>;
	226	#size-cells = <1>;
	227	ranges;
cc60a1a4	228
da047acd AG	229	syscon-tcsr = <&tcsr>;
da047acd AG	230
10bfcfea	231	gsbi12_serial: serial@19c40000 {
66a6c317 KG	232	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	233	reg = <0x19c40000 0x1000>,
	234	<0x19c00000 0x1000>;
c51cb1a1	235	interrupts = <0 195 IRQ_TYPE_NONE>;
66a6c317 KG	236	clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
	237	clock-names = "core", "iface";
	238	status = "disabled";
	239	};
c51cb1a1 LW	240
	241	gsbi12_i2c: i2c@19c80000 {
	242	compatible = "qcom,i2c-qup-v1.1.1";
	243	reg = <0x19c80000 0x1000>;
	244	interrupts = <0 196 IRQ_TYPE_NONE>;
	245	clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
	246	clock-names = "core", "iface";
	247	#address-cells = <1>;
	248	#size-cells = <0>;
	249	status = "disabled";
	250	};
66a6c317 KG	251	};
66a6c317 KG	252
e3770594 LW	253	external-bus@1a100000 {
	254	compatible = "qcom,msm8660-ebi2";
	255	#address-cells = <2>;
	256	#size-cells = <1>;
	257	ranges = <0 0x0 0x1a800000 0x00800000>,
	258	<1 0x0 0x1b000000 0x00800000>,
	259	<2 0x0 0x1b800000 0x00800000>,
	260	<3 0x0 0x1d000000 0x08000000>,
	261	<4 0x0 0x1c800000 0x00800000>,
	262	<5 0x0 0x1c000000 0x00800000>;
	263	reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
	264	reg-names = "ebi2", "xmem";
	265	clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
	266	clock-names = "ebi2x", "ebi2";
	267	status = "disabled";
	268	};
	269
66a6c317 KG	270	qcom,ssbi@500000 {
	271	compatible = "qcom,ssbi";
	272	reg = <0x500000 0x1000>;
	273	qcom,controller-type = "pmic-arbiter";
94ae991d	274
86e06f02	275	pm8058: pmic@0 {
94ae991d	276	compatible = "qcom,pm8058";
8e140c8e	277	interrupt-parent = <&tlmm>;
94ae991d SB	278	interrupts = <88 8>;
	279	#interrupt-cells = <2>;
	280	interrupt-controller;
	281	#address-cells = <1>;
	282	#size-cells = <0>;
	283
0840ea9e LW	284	pm8058_gpio: gpio@150 {
	285	compatible = "qcom,pm8058-gpio",
	286	"qcom,ssbi-gpio";
	287	reg = <0x150>;
86e06f02	288	interrupt-parent = <&pm8058>;
dcf5907e LW	289	interrupts = <192 IRQ_TYPE_NONE>,
	290	<193 IRQ_TYPE_NONE>,
	291	<194 IRQ_TYPE_NONE>,
	292	<195 IRQ_TYPE_NONE>,
	293	<196 IRQ_TYPE_NONE>,
	294	<197 IRQ_TYPE_NONE>,
	295	<198 IRQ_TYPE_NONE>,
	296	<199 IRQ_TYPE_NONE>,
	297	<200 IRQ_TYPE_NONE>,
	298	<201 IRQ_TYPE_NONE>,
	299	<202 IRQ_TYPE_NONE>,
	300	<203 IRQ_TYPE_NONE>,
	301	<204 IRQ_TYPE_NONE>,
	302	<205 IRQ_TYPE_NONE>,
	303	<206 IRQ_TYPE_NONE>,
	304	<207 IRQ_TYPE_NONE>,
	305	<208 IRQ_TYPE_NONE>,
	306	<209 IRQ_TYPE_NONE>,
	307	<210 IRQ_TYPE_NONE>,
	308	<211 IRQ_TYPE_NONE>,
	309	<212 IRQ_TYPE_NONE>,
	310	<213 IRQ_TYPE_NONE>,
	311	<214 IRQ_TYPE_NONE>,
	312	<215 IRQ_TYPE_NONE>,
	313	<216 IRQ_TYPE_NONE>,
	314	<217 IRQ_TYPE_NONE>,
	315	<218 IRQ_TYPE_NONE>,
	316	<219 IRQ_TYPE_NONE>,
	317	<220 IRQ_TYPE_NONE>,
	318	<221 IRQ_TYPE_NONE>,
	319	<222 IRQ_TYPE_NONE>,
	320	<223 IRQ_TYPE_NONE>,
	321	<224 IRQ_TYPE_NONE>,
	322	<225 IRQ_TYPE_NONE>,
	323	<226 IRQ_TYPE_NONE>,
	324	<227 IRQ_TYPE_NONE>,
	325	<228 IRQ_TYPE_NONE>,
	326	<229 IRQ_TYPE_NONE>,
	327	<230 IRQ_TYPE_NONE>,
	328	<231 IRQ_TYPE_NONE>,
	329	<232 IRQ_TYPE_NONE>,
	330	<233 IRQ_TYPE_NONE>,
	331	<234 IRQ_TYPE_NONE>,
	332	<235 IRQ_TYPE_NONE>;
0840ea9e LW	333	gpio-controller;
	334	#gpio-cells = <2>;
	335
	336	};
	337
	338	pm8058_mpps: mpps@50 {
	339	compatible = "qcom,pm8058-mpp",
	340	"qcom,ssbi-mpp";
	341	reg = <0x50>;
	342	gpio-controller;
	343	#gpio-cells = <2>;
86e06f02	344	interrupt-parent = <&pm8058>;
0840ea9e	345	interrupts =
dcf5907e LW	346	<128 IRQ_TYPE_NONE>,
	347	<129 IRQ_TYPE_NONE>,
	348	<130 IRQ_TYPE_NONE>,
	349	<131 IRQ_TYPE_NONE>,
	350	<132 IRQ_TYPE_NONE>,
	351	<133 IRQ_TYPE_NONE>,
	352	<134 IRQ_TYPE_NONE>,
	353	<135 IRQ_TYPE_NONE>,
	354	<136 IRQ_TYPE_NONE>,
	355	<137 IRQ_TYPE_NONE>,
	356	<138 IRQ_TYPE_NONE>,
	357	<139 IRQ_TYPE_NONE>;
0840ea9e LW	358	};
0840ea9e LW	359
94ae991d SB	360	pwrkey@1c {
	361	compatible = "qcom,pm8058-pwrkey";
	362	reg = <0x1c>;
86e06f02	363	interrupt-parent = <&pm8058>;
94ae991d SB	364	interrupts = <50 1>, <51 1>;
	365	debounce = <15625>;
	366	pull-up;
	367	};
	368
	369	keypad@148 {
	370	compatible = "qcom,pm8058-keypad";
	371	reg = <0x148>;
86e06f02	372	interrupt-parent = <&pm8058>;
94ae991d SB	373	interrupts = <74 1>, <75 1>;
	374	debounce = <15>;
	375	scan-delay = <32>;
	376	row-hold = <91500>;
	377	};
	378
6d78cea6 LW	379	xoadc: xoadc@197 {
	380	compatible = "qcom,pm8058-adc";
	381	reg = <0x197>;
	382	interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
	383	#address-cells = <2>;
	384	#size-cells = <0>;
	385	#io-channel-cells = <2>;
	386
8dccafaa	387	vcoin: adc-channel@0 {
6d78cea6 LW	388	reg = <0x00 0x00>;
6d78cea6 LW	389	};
8dccafaa	390	vbat: adc-channel@1 {
6d78cea6 LW	391	reg = <0x00 0x01>;
6d78cea6 LW	392	};
8dccafaa	393	dcin: adc-channel@2 {
6d78cea6 LW	394	reg = <0x00 0x02>;
6d78cea6 LW	395	};
8dccafaa	396	ichg: adc-channel@3 {
6d78cea6 LW	397	reg = <0x00 0x03>;
6d78cea6 LW	398	};
8dccafaa	399	vph_pwr: adc-channel@4 {
6d78cea6 LW	400	reg = <0x00 0x04>;
6d78cea6 LW	401	};
8dccafaa	402	usb_vbus: adc-channel@a {
6d78cea6 LW	403	reg = <0x00 0x0a>;
6d78cea6 LW	404	};
8dccafaa	405	die_temp: adc-channel@b {
6d78cea6 LW	406	reg = <0x00 0x0b>;
6d78cea6 LW	407	};
8dccafaa	408	ref_625mv: adc-channel@c {
6d78cea6 LW	409	reg = <0x00 0x0c>;
6d78cea6 LW	410	};
8dccafaa	411	ref_1250mv: adc-channel@d {
6d78cea6 LW	412	reg = <0x00 0x0d>;
6d78cea6 LW	413	};
8dccafaa	414	ref_325mv: adc-channel@e {
6d78cea6 LW	415	reg = <0x00 0x0e>;
6d78cea6 LW	416	};
8dccafaa	417	ref_muxoff: adc-channel@f {
6d78cea6 LW	418	reg = <0x00 0x0f>;
	419	};
	420	};
	421
e20fd336	422	rtc@1e8 {
94ae991d	423	compatible = "qcom,pm8058-rtc";
e20fd336	424	reg = <0x1e8>;
86e06f02	425	interrupt-parent = <&pm8058>;
94ae991d	426	interrupts = <39 1>;
94ae991d SB	427	allow-set-time;
	428	};
	429
	430	vibrator@4a {
	431	compatible = "qcom,pm8058-vib";
	432	reg = <0x4a>;
	433	};
	434	};
66a6c317	435	};
55602a09	436
30b4fb1c LW	437	l2cc: clock-controller@2082000 {
	438	compatible = "syscon";
	439	reg = <0x02082000 0x1000>;
	440	};
	441
	442	rpm: rpm@104000 {
	443	compatible = "qcom,rpm-msm8660";
	444	reg = <0x00104000 0x1000>;
	445	qcom,ipc = <&l2cc 0x8 2>;
	446
	447	interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
	448	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	449	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	450	interrupt-names = "ack", "err", "wakeup";
	451	clocks = <&gcc RPM_MSG_RAM_H_CLK>;
	452	clock-names = "ram";
	453
	454	rpmcc: clock-controller {
c715909b	455	compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
30b4fb1c LW	456	#clock-cells = <1>;
	457	};
	458
	459	pm8901-regulators {
	460	compatible = "qcom,rpm-pm8901-regulators";
	461
	462	pm8901_l0: l0 {};
	463	pm8901_l1: l1 {};
	464	pm8901_l2: l2 {};
	465	pm8901_l3: l3 {};
	466	pm8901_l4: l4 {};
	467	pm8901_l5: l5 {};
	468	pm8901_l6: l6 {};
	469
	470	/* S0 and S1 Handled as SAW regulators by SPM */
	471	pm8901_s2: s2 {};
	472	pm8901_s3: s3 {};
	473	pm8901_s4: s4 {};
	474
	475	pm8901_lvs0: lvs0 {};
	476	pm8901_lvs1: lvs1 {};
	477	pm8901_lvs2: lvs2 {};
	478	pm8901_lvs3: lvs3 {};
	479
	480	pm8901_mvs: mvs {};
	481	};
	482
	483	pm8058-regulators {
	484	compatible = "qcom,rpm-pm8058-regulators";
	485
	486	pm8058_l0: l0 {};
	487	pm8058_l1: l1 {};
	488	pm8058_l2: l2 {};
	489	pm8058_l3: l3 {};
	490	pm8058_l4: l4 {};
	491	pm8058_l5: l5 {};
	492	pm8058_l6: l6 {};
	493	pm8058_l7: l7 {};
	494	pm8058_l8: l8 {};
	495	pm8058_l9: l9 {};
	496	pm8058_l10: l10 {};
	497	pm8058_l11: l11 {};
	498	pm8058_l12: l12 {};
	499	pm8058_l13: l13 {};
	500	pm8058_l14: l14 {};
	501	pm8058_l15: l15 {};
	502	pm8058_l16: l16 {};
	503	pm8058_l17: l17 {};
	504	pm8058_l18: l18 {};
	505	pm8058_l19: l19 {};
	506	pm8058_l20: l20 {};
	507	pm8058_l21: l21 {};
	508	pm8058_l22: l22 {};
	509	pm8058_l23: l23 {};
	510	pm8058_l24: l24 {};
	511	pm8058_l25: l25 {};
	512
	513	pm8058_s0: s0 {};
	514	pm8058_s1: s1 {};
	515	pm8058_s2: s2 {};
	516	pm8058_s3: s3 {};
	517	pm8058_s4: s4 {};
	518
	519	pm8058_lvs0: lvs0 {};
520	pm8058_lvs1: lvs1 {};
521
522	pm8058_ncp: ncp {};
523	};
524	};
525
55602a09	526	amba {
2ef7d5f3	527	compatible = "simple-bus";
55602a09 SB	528	#address-cells = <1>;
	529	#size-cells = <1>;
	530	ranges;
	531	sdcc1: sdcc@12400000 {
	532	status = "disabled";
	533	compatible = "arm,pl18x", "arm,primecell";
	534	arm,primecell-periphid = <0x00051180>;
	535	reg = <0x12400000 0x8000>;
	536	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	537	interrupt-names = "cmd_irq";
	538	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	539	clock-names = "mclk", "apb_pclk";
	540	bus-width = <8>;
	541	max-frequency = <48000000>;
	542	non-removable;
	543	cap-sd-highspeed;
	544	cap-mmc-highspeed;
55602a09 SB	545	};
55602a09 SB	546
dfc14010 LW	547	sdcc2: sdcc@12140000 {
	548	status = "disabled";
	549	compatible = "arm,pl18x", "arm,primecell";
	550	arm,primecell-periphid = <0x00051180>;
	551	reg = <0x12140000 0x8000>;
	552	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	553	interrupt-names = "cmd_irq";
	554	clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
	555	clock-names = "mclk", "apb_pclk";
	556	bus-width = <8>;
	557	max-frequency = <48000000>;
	558	cap-sd-highspeed;
	559	cap-mmc-highspeed;
	560	};
	561
55602a09 SB	562	sdcc3: sdcc@12180000 {
	563	compatible = "arm,pl18x", "arm,primecell";
	564	arm,primecell-periphid = <0x00051180>;
	565	status = "disabled";
	566	reg = <0x12180000 0x8000>;
	567	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	568	interrupt-names = "cmd_irq";
	569	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	570	clock-names = "mclk", "apb_pclk";
	571	bus-width = <4>;
	572	cap-sd-highspeed;
	573	cap-mmc-highspeed;
	574	max-frequency = <48000000>;
	575	no-1-8-v;
55602a09	576	};
5f761007	577
dfc14010 LW	578	sdcc4: sdcc@121c0000 {
	579	compatible = "arm,pl18x", "arm,primecell";
	580	arm,primecell-periphid = <0x00051180>;
	581	status = "disabled";
	582	reg = <0x121c0000 0x8000>;
	583	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	584	interrupt-names = "cmd_irq";
	585	clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
	586	clock-names = "mclk", "apb_pclk";
	587	bus-width = <4>;
	588	max-frequency = <48000000>;
	589	cap-sd-highspeed;
	590	cap-mmc-highspeed;
	591	};
	592
5f761007 LW	593	sdcc5: sdcc@12200000 {
	594	compatible = "arm,pl18x", "arm,primecell";
	595	arm,primecell-periphid = <0x00051180>;
	596	status = "disabled";
	597	reg = <0x12200000 0x8000>;
	598	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	599	interrupt-names = "cmd_irq";
	600	clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
	601	clock-names = "mclk", "apb_pclk";
	602	bus-width = <4>;
	603	cap-sd-highspeed;
	604	cap-mmc-highspeed;
	605	max-frequency = <48000000>;
5f761007	606	};
55602a09	607	};
da047acd AG	608
	609	tcsr: syscon@1a400000 {
	610	compatible = "qcom,tcsr-msm8660", "syscon";
	611	reg = <0x1a400000 0x100>;
	612	};
cc60a1a4	613	};
55602a09	614
cc60a1a4	615	};