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Merge tag 'mvebu-fixes-4.17-2' of git://git.infradead.org/linux-mvebu into fixes
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / r8a73a4.dtsi
CommitLineData
eccf0607
MD		 1/*
2 * Device Tree Source for the r8a73a4 SoC
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
a76809a3 12#include <dt-bindings/clock/r8a73a4-clock.h>
5f75e73c
LP		 13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
eccf0607
MD		 16/ {
17 compatible = "renesas,r8a73a4";
18 interrupt-parent = <&gic>;
26a0d2d4
TY		 19 #address-cells = <2>;
20 #size-cells = <2>;
eccf0607
MD		 21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a15";
29 reg = <0>;
a7869a5b 30 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
eccf0607 31 clock-frequency = <1500000000>;
7b9ad9a0 32 power-domains = <&pd_a2sl>;
c86a4b62 33 next-level-cache = <&L2_CA15>;
eccf0607 34 };
b0da45c6 35
cdaf6417 36 L2_CA15: cache-controller-0 {
b0da45c6 37 compatible = "cache";
b0da45c6
GU		 38 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
39 power-domains = <&pd_a3sm>;
40 cache-unified;
41 cache-level = <2>;
42 };
43
cdaf6417 44 L2_CA7: cache-controller-1 {
b0da45c6 45 compatible = "cache";
b0da45c6
GU		 46 clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
47 power-domains = <&pd_a3km>;
48 cache-unified;
49 cache-level = <2>;
50 };
eccf0607
MD		 51 };
52
7b9ad9a0
GU		 53 ptm {
54 compatible = "arm,coresight-etm3x";
55 power-domains = <&pd_d4>;
56 };
57
eccf0607
MD		 58 timer {
59 compatible = "arm,armv7-timer";
45e75c42
GU		 60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
eccf0607 64 };
984ca295 65
35dd549c
GU		 66 dbsc1: memory-controller@e6790000 {
67 compatible = "renesas,dbsc-r8a73a4";
68 reg = <0 0xe6790000 0 0x10000>;
7b9ad9a0 69 power-domains = <&pd_a3bc>;
35dd549c
GU		 70 };
71
72 dbsc2: memory-controller@e67a0000 {
73 compatible = "renesas,dbsc-r8a73a4";
74 reg = <0 0xe67a0000 0 0x10000>;
7b9ad9a0 75 power-domains = <&pd_a3bc>;
35dd549c
GU		 76 };
77
7300505a
UH		 78 dmac: dma-multiplexer {
79 compatible = "renesas,shdma-mux";
80 #dma-cells = <1>;
81 dma-channels = <20>;
82 dma-requests = <256>;
83 #address-cells = <2>;
84 #size-cells = <2>;
85 ranges;
86
87 dma0: dma-controller@e6700020 {
88 compatible = "renesas,shdma-r8a73a4";
89 reg = <0 0xe6700020 0 0x89e0>;
4d5746a3
SH		 90 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
91 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
92 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
93 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
94 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
95 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
96 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
97 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
98 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
99 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
100 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
101 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
102 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
103 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
104 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
105 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
106 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
107 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
108 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
109 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
110 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
7300505a
UH		 111 interrupt-names = "error",
112 "ch0", "ch1", "ch2", "ch3",
113 "ch4", "ch5", "ch6", "ch7",
114 "ch8", "ch9", "ch10", "ch11",
115 "ch12", "ch13", "ch14", "ch15",
116 "ch16", "ch17", "ch18", "ch19";
662dd64f 117 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
7b9ad9a0 118 power-domains = <&pd_a3sp>;
7300505a
UH		 119 };
120 };
121
7300505a
UH		 122 i2c5: i2c@e60b0000 {
123 #address-cells = <1>;
124 #size-cells = <0>;
7e9ad4d0 125 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
7300505a 126 reg = <0 0xe60b0000 0 0x428>;
4d5746a3 127 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 128 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
7b9ad9a0 129 power-domains = <&pd_a3sp>;
f7b65230
SH		 130
131 status = "disabled";
132 };
133
134 cmt1: timer@e6130000 {
86656e9c 135 compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
f7b65230 136 reg = <0 0xe6130000 0 0x1004>;
4d5746a3 137 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
662dd64f
UH		 138 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
139 clock-names = "fck";
7b9ad9a0 140 power-domains = <&pd_c5>;
7300505a
UH		 141 status = "disabled";
142 };
143
984ca295 144 irqc0: interrupt-controller@e61c0000 {
34abee39 145 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
984ca295
MD		 146 #interrupt-cells = <2>;
147 interrupt-controller;
26a0d2d4 148 reg = <0 0xe61c0000 0 0x200>;
4d5746a3
SH		 149 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1c2a7eb7 181 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
7b9ad9a0 182 power-domains = <&pd_c4>;
984ca295
MD		 183 };
184
185 irqc1: interrupt-controller@e61c0200 {
34abee39 186 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
984ca295
MD		 187 #interrupt-cells = <2>;
188 interrupt-controller;
26a0d2d4 189 reg = <0 0xe61c0200 0 0x200>;
4d5746a3
SH		 190 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1c2a7eb7 216 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
7b9ad9a0 217 power-domains = <&pd_c4>;
984ca295
MD		 218 };
219
5b9906c9 220 pfc: pin-controller@e6050000 {
e4ba0a9b
GU		 221 compatible = "renesas,pfc-r8a73a4";
222 reg = <0 0xe6050000 0 0x9000>;
223 gpio-controller;
224 #gpio-cells = <2>;
17ccec50
GU		 225 gpio-ranges =
226 <&pfc 0 0 31>, <&pfc 32 32 9>,
227 <&pfc 64 64 22>, <&pfc 96 96 31>,
228 <&pfc 128 128 7>, <&pfc 160 160 19>,
229 <&pfc 192 192 31>, <&pfc 224 224 27>,
230 <&pfc 256 256 28>, <&pfc 288 288 21>,
231 <&pfc 320 320 10>;
e4ba0a9b
GU		 232 interrupts-extended =
233 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
234 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
235 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
236 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
237 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
238 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
239 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
240 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
241 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
242 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
243 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
244 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
245 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
246 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
247 <&irqc1 24 0>, <&irqc1 25 0>;
7b9ad9a0 248 power-domains = <&pd_c5>;
e4ba0a9b
GU		 249 };
250
c91cf2fa 251 thermal@e61f0000 {
a2cfaa74 252 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
26a0d2d4
TY		 253 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
254 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
4d5746a3 255 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 256 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
7b9ad9a0 257 power-domains = <&pd_c5>;
c91cf2fa 258 };
f98c1069
GL		 259
260 i2c0: i2c@e6500000 {
261 #address-cells = <1>;
262 #size-cells = <0>;
7e9ad4d0 263 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 264 reg = <0 0xe6500000 0 0x428>;
4d5746a3 265 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 266 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
7b9ad9a0 267 power-domains = <&pd_a3sp>;
eda3a4fa 268 status = "disabled";
f98c1069
GL		 269 };
270
271 i2c1: i2c@e6510000 {
272 #address-cells = <1>;
273 #size-cells = <0>;
7e9ad4d0 274 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 275 reg = <0 0xe6510000 0 0x428>;
4d5746a3 276 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 277 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
7b9ad9a0 278 power-domains = <&pd_a3sp>;
eda3a4fa 279 status = "disabled";
f98c1069
GL		 280 };
281
282 i2c2: i2c@e6520000 {
283 #address-cells = <1>;
284 #size-cells = <0>;
7e9ad4d0 285 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 286 reg = <0 0xe6520000 0 0x428>;
4d5746a3 287 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 288 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
7b9ad9a0 289 power-domains = <&pd_a3sp>;
eda3a4fa 290 status = "disabled";
f98c1069
GL		 291 };
292
293 i2c3: i2c@e6530000 {
294 #address-cells = <1>;
295 #size-cells = <0>;
7e9ad4d0 296 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 297 reg = <0 0xe6530000 0 0x428>;
4d5746a3 298 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 299 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
7b9ad9a0 300 power-domains = <&pd_a3sp>;
eda3a4fa 301 status = "disabled";
f98c1069
GL		 302 };
303
304 i2c4: i2c@e6540000 {
305 #address-cells = <1>;
306 #size-cells = <0>;
7e9ad4d0 307 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 308 reg = <0 0xe6540000 0 0x428>;
4d5746a3 309 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 310 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
7b9ad9a0 311 power-domains = <&pd_a3sp>;
eda3a4fa 312 status = "disabled";
f98c1069
GL		 313 };
314
f98c1069
GL		 315 i2c6: i2c@e6550000 {
316 #address-cells = <1>;
317 #size-cells = <0>;
7e9ad4d0 318 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 319 reg = <0 0xe6550000 0 0x428>;
4d5746a3 320 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 321 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
7b9ad9a0 322 power-domains = <&pd_a3sp>;
eda3a4fa 323 status = "disabled";
f98c1069
GL		 324 };
325
326 i2c7: i2c@e6560000 {
327 #address-cells = <1>;
328 #size-cells = <0>;
7e9ad4d0 329 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 330 reg = <0 0xe6560000 0 0x428>;
4d5746a3 331 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 332 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
7b9ad9a0 333 power-domains = <&pd_a3sp>;
eda3a4fa 334 status = "disabled";
f98c1069
GL		 335 };
336
337 i2c8: i2c@e6570000 {
338 #address-cells = <1>;
339 #size-cells = <0>;
7e9ad4d0 340 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 341 reg = <0 0xe6570000 0 0x428>;
4d5746a3 342 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 343 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
7b9ad9a0 344 power-domains = <&pd_a3sp>;
94f1a03d
SH		 345 status = "disabled";
346 };
347
0b3a0ef6 348 scifb0: serial@e6c20000 {
94f1a03d
SH		 349 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
350 reg = <0 0xe6c20000 0 0x100>;
4d5746a3 351 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 352 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
d4be2f1b 353 clock-names = "fck";
7b9ad9a0 354 power-domains = <&pd_a3sp>;
94f1a03d
SH		 355 status = "disabled";
356 };
357
0b3a0ef6 358 scifb1: serial@e6c30000 {
94f1a03d
SH		 359 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
360 reg = <0 0xe6c30000 0 0x100>;
4d5746a3 361 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 362 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
d4be2f1b 363 clock-names = "fck";
7b9ad9a0 364 power-domains = <&pd_a3sp>;
94f1a03d
SH		 365 status = "disabled";
366 };
367
7300505a
UH		 368 scifa0: serial@e6c40000 {
369 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
370 reg = <0 0xe6c40000 0 0x100>;
4d5746a3 371 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 372 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
d4be2f1b 373 clock-names = "fck";
7b9ad9a0 374 power-domains = <&pd_a3sp>;
7300505a
UH		 375 status = "disabled";
376 };
377
378 scifa1: serial@e6c50000 {
379 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
380 reg = <0 0xe6c50000 0 0x100>;
4d5746a3 381 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 382 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
d4be2f1b 383 clock-names = "fck";
7b9ad9a0 384 power-domains = <&pd_a3sp>;
7300505a
UH		 385 status = "disabled";
386 };
387
0b3a0ef6 388 scifb2: serial@e6ce0000 {
94f1a03d
SH		 389 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
390 reg = <0 0xe6ce0000 0 0x100>;
4d5746a3 391 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 392 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
d4be2f1b 393 clock-names = "fck";
7b9ad9a0 394 power-domains = <&pd_a3sp>;
94f1a03d
SH		 395 status = "disabled";
396 };
397
0b3a0ef6 398 scifb3: serial@e6cf0000 {
94f1a03d
SH		 399 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
400 reg = <0 0xe6cf0000 0 0x100>;
4d5746a3 401 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 402 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
d4be2f1b 403 clock-names = "fck";
7b9ad9a0 404 power-domains = <&pd_c4>;
eda3a4fa 405 status = "disabled";
f98c1069 406 };
369ee2db 407
43304a5f 408 sdhi0: sd@ee100000 {
df1d0584 409 compatible = "renesas,sdhi-r8a73a4";
369ee2db 410 reg = <0 0xee100000 0 0x100>;
4d5746a3 411 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 412 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
7b9ad9a0 413 power-domains = <&pd_a3sp>;
369ee2db
GL		 414 cap-sd-highspeed;
415 status = "disabled";
416 };
417
43304a5f 418 sdhi1: sd@ee120000 {
df1d0584 419 compatible = "renesas,sdhi-r8a73a4";
369ee2db 420 reg = <0 0xee120000 0 0x100>;
4d5746a3 421 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 422 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
7b9ad9a0 423 power-domains = <&pd_a3sp>;
369ee2db
GL		 424 cap-sd-highspeed;
425 status = "disabled";
426 };
427
43304a5f 428 sdhi2: sd@ee140000 {
df1d0584 429 compatible = "renesas,sdhi-r8a73a4";
369ee2db 430 reg = <0 0xee140000 0 0x100>;
4d5746a3 431 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 432 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
7b9ad9a0 433 power-domains = <&pd_a3sp>;
369ee2db
GL		 434 cap-sd-highspeed;
435 status = "disabled";
436 };
7300505a
UH		 437
438 mmcif0: mmc@ee200000 {
5b016174 439 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
7300505a 440 reg = <0 0xee200000 0 0x80>;
4d5746a3 441 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 442 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
7b9ad9a0 443 power-domains = <&pd_a3sp>;
7300505a
UH		 444 reg-io-width = <4>;
445 status = "disabled";
446 };
447
448 mmcif1: mmc@ee220000 {
5b016174 449 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
7300505a 450 reg = <0 0xee220000 0 0x80>;
4d5746a3 451 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 452 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
7b9ad9a0 453 power-domains = <&pd_a3sp>;
7300505a
UH		 454 reg-io-width = <4>;
455 status = "disabled";
456 };
457
458 gic: interrupt-controller@f1001000 {
eaec1d67 459 compatible = "arm,gic-400";
7300505a
UH		 460 #interrupt-cells = <3>;
461 #address-cells = <0>;
462 interrupt-controller;
463 reg = <0 0xf1001000 0 0x1000>,
387720c9 464 <0 0xf1002000 0 0x2000>,
7300505a
UH		 465 <0 0xf1004000 0 0x2000>,
466 <0 0xf1006000 0 0x2000>;
45e75c42 467 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
c11333cc
GU		 468 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
469 clock-names = "clk";
470 power-domains = <&pd_c4>;
7300505a 471 };
a76809a3 472
271b3ad2
GU		 473 bsc: bus@fec10000 {
474 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
475 "simple-pm-bus";
476 #address-cells = <1>;
477 #size-cells = <1>;
478 ranges = <0 0 0 0x20000000>;
479 reg = <0 0xfec10000 0 0x400>;
480 clocks = <&zb_clk>;
7b9ad9a0 481 power-domains = <&pd_c4>;
271b3ad2
GU		 482 };
483
a76809a3
UH		 484 clocks {
485 #address-cells = <2>;
486 #size-cells = <2>;
487 ranges;
488
489 /* External root clocks */
57c75d1e 490 extalr_clk: extalr {
a76809a3
UH		 491 compatible = "fixed-clock";
492 #clock-cells = <0>;
493 clock-frequency = <32768>;
a76809a3 494 };
57c75d1e 495 extal1_clk: extal1 {
a76809a3
UH		 496 compatible = "fixed-clock";
497 #clock-cells = <0>;
498 clock-frequency = <25000000>;
a76809a3 499 };
57c75d1e 500 extal2_clk: extal2 {
a76809a3
UH		 501 compatible = "fixed-clock";
502 #clock-cells = <0>;
503 clock-frequency = <48000000>;
a76809a3 504 };
57c75d1e 505 fsiack_clk: fsiack {
a76809a3
UH		 506 compatible = "fixed-clock";
507 #clock-cells = <0>;
508 /* This value must be overridden by the board. */
509 clock-frequency = <0>;
a76809a3 510 };
57c75d1e 511 fsibck_clk: fsibck {
a76809a3
UH		 512 compatible = "fixed-clock";
513 #clock-cells = <0>;
514 /* This value must be overridden by the board. */
515 clock-frequency = <0>;
a76809a3
UH		 516 };
517
518 /* Special CPG clocks */
519 cpg_clocks: cpg_clocks@e6150000 {
520 compatible = "renesas,r8a73a4-cpg-clocks";
521 reg = <0 0xe6150000 0 0x10000>;
522 clocks = <&extal1_clk>, <&extal2_clk>;
523 #clock-cells = <1>;
524 clock-output-names = "main", "pll0", "pll1", "pll2",
525 "pll2s", "pll2h", "z", "z2",
526 "i", "m3", "b", "m1", "m2",
527 "zx", "zs", "hp";
528 };
529
530 /* Variable factor clocks (DIV6) */
531 zb_clk: zb_clk@e6150010 {
532 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
533 reg = <0 0xe6150010 0 4>;
534 clocks = <&pll1_div2_clk>, <0>,
535 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
536 #clock-cells = <0>;
537 clock-output-names = "zb";
538 };
57c75d1e 539 sdhi0_clk: sdhi0ck@e6150074 {
a76809a3
UH		 540 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
541 reg = <0 0xe6150074 0 4>;
542 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
543 <0>, <&extal2_clk>;
544 #clock-cells = <0>;
a76809a3 545 };
57c75d1e 546 sdhi1_clk: sdhi1ck@e6150078 {
a76809a3
UH		 547 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
548 reg = <0 0xe6150078 0 4>;
549 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
550 <0>, <&extal2_clk>;
551 #clock-cells = <0>;
a76809a3 552 };
57c75d1e 553 sdhi2_clk: sdhi2ck@e615007c {
a76809a3
UH		 554 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
555 reg = <0 0xe615007c 0 4>;
556 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
557 <0>, <&extal2_clk>;
558 #clock-cells = <0>;
a76809a3 559 };
57c75d1e 560 mmc0_clk: mmc0@e6150240 {
a76809a3
UH		 561 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
562 reg = <0 0xe6150240 0 4>;
563 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
564 <0>, <&extal2_clk>;
565 #clock-cells = <0>;
a76809a3 566 };
57c75d1e 567 mmc1_clk: mmc1@e6150244 {
a76809a3
UH		 568 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
569 reg = <0 0xe6150244 0 4>;
570 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
571 <0>, <&extal2_clk>;
572 #clock-cells = <0>;
a76809a3 573 };
57c75d1e 574 vclk1_clk: vclk1@e6150008 {
a76809a3
UH		 575 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
576 reg = <0 0xe6150008 0 4>;
577 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
578 <0>, <&extal2_clk>, <&main_div2_clk>,
579 <&extalr_clk>, <0>, <0>;
580 #clock-cells = <0>;
a76809a3 581 };
57c75d1e 582 vclk2_clk: vclk2@e615000c {
a76809a3
UH		 583 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
584 reg = <0 0xe615000c 0 4>;
585 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
586 <0>, <&extal2_clk>, <&main_div2_clk>,
587 <&extalr_clk>, <0>, <0>;
588 #clock-cells = <0>;
a76809a3 589 };
57c75d1e 590 vclk3_clk: vclk3@e615001c {
a76809a3
UH		 591 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
592 reg = <0 0xe615001c 0 4>;
593 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
594 <0>, <&extal2_clk>, <&main_div2_clk>,
595 <&extalr_clk>, <0>, <0>;
596 #clock-cells = <0>;
a76809a3 597 };
57c75d1e 598 vclk4_clk: vclk4@e6150014 {
a76809a3
UH		 599 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
600 reg = <0 0xe6150014 0 4>;
601 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
602 <0>, <&extal2_clk>, <&main_div2_clk>,
603 <&extalr_clk>, <0>, <0>;
604 #clock-cells = <0>;
a76809a3 605 };
57c75d1e 606 vclk5_clk: vclk5@e6150034 {
a76809a3
UH		 607 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
608 reg = <0 0xe6150034 0 4>;
609 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
610 <0>, <&extal2_clk>, <&main_div2_clk>,
611 <&extalr_clk>, <0>, <0>;
612 #clock-cells = <0>;
a76809a3 613 };
57c75d1e 614 fsia_clk: fsia@e6150018 {
a76809a3
UH		 615 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
616 reg = <0 0xe6150018 0 4>;
617 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
618 <&fsiack_clk>, <0>;
619 #clock-cells = <0>;
a76809a3 620 };
57c75d1e 621 fsib_clk: fsib@e6150090 {
a76809a3
UH		 622 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
623 reg = <0 0xe6150090 0 4>;
624 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
625 <&fsibck_clk>, <0>;
626 #clock-cells = <0>;
a76809a3 627 };
57c75d1e 628 mp_clk: mp@e6150080 {
a76809a3
UH		 629 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
630 reg = <0 0xe6150080 0 4>;
631 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
632 <&extal2_clk>, <&extal2_clk>;
633 #clock-cells = <0>;
a76809a3 634 };
57c75d1e 635 m4_clk: m4@e6150098 {
a76809a3
UH		 636 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
637 reg = <0 0xe6150098 0 4>;
638 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
639 #clock-cells = <0>;
a76809a3 640 };
57c75d1e 641 hsi_clk: hsi@e615026c {
a76809a3
UH		 642 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
643 reg = <0 0xe615026c 0 4>;
644 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
645 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
646 #clock-cells = <0>;
a76809a3 647 };
57c75d1e 648 spuv_clk: spuv@e6150094 {
a76809a3
UH		 649 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
650 reg = <0 0xe6150094 0 4>;
651 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
652 <&extal2_clk>, <&extal2_clk>;
653 #clock-cells = <0>;
a76809a3
UH		 654 };
655
656 /* Fixed factor clocks */
57c75d1e 657 main_div2_clk: main_div2 {
a76809a3
UH		 658 compatible = "fixed-factor-clock";
659 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
660 #clock-cells = <0>;
661 clock-div = <2>;
662 clock-mult = <1>;
a76809a3 663 };
57c75d1e 664 pll0_div2_clk: pll0_div2 {
a76809a3
UH		 665 compatible = "fixed-factor-clock";
666 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
667 #clock-cells = <0>;
668 clock-div = <2>;
669 clock-mult = <1>;
a76809a3 670 };
57c75d1e 671 pll1_div2_clk: pll1_div2 {
a76809a3
UH		 672 compatible = "fixed-factor-clock";
673 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
674 #clock-cells = <0>;
675 clock-div = <2>;
676 clock-mult = <1>;
a76809a3 677 };
57c75d1e 678 extal1_div2_clk: extal1_div2 {
a76809a3
UH		 679 compatible = "fixed-factor-clock";
680 clocks = <&extal1_clk>;
681 #clock-cells = <0>;
682 clock-div = <2>;
683 clock-mult = <1>;
a76809a3
UH		 684 };
685
686 /* Gate clocks */
687 mstp2_clks: mstp2_clks@e6150138 {
688 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
689 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
690 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
691 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
692 #clock-cells = <1>;
693 clock-indices = <
694 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
695 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
696 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
697 R8A73A4_CLK_DMAC
698 >;
699 clock-output-names =
700 "scifa0", "scifa1", "scifb0", "scifb1",
701 "scifb2", "scifb3", "dmac";
702 };
703 mstp3_clks: mstp3_clks@e615013c {
704 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
705 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
706 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
707 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
708 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
709 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
710 R8A73A4_CLK_HP>, <&cpg_clocks
711 R8A73A4_CLK_HP>, <&extalr_clk>;
712 #clock-cells = <1>;
713 clock-indices = <
714 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
715 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
716 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
717 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
718 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
719 R8A73A4_CLK_CMT1
720 >;
721 clock-output-names =
722 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
723 "mmcif0", "iic6", "iic7", "iic0", "iic1",
724 "cmt1";
725 };
726 mstp4_clks: mstp4_clks@e6150140 {
727 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
728 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
c11333cc
GU		 729 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
730 <&main_div2_clk>,
1c2a7eb7 731 <&cpg_clocks R8A73A4_CLK_HP>,
a76809a3
UH		 732 <&cpg_clocks R8A73A4_CLK_HP>;
733 #clock-cells = <1>;
734 clock-indices = <
c11333cc
GU		 735 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
736 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
737 R8A73A4_CLK_IIC3
a76809a3
UH		 738 >;
739 clock-output-names =
c11333cc 740 "irqc", "intc-sys", "iic5", "iic4", "iic3";
a76809a3
UH		 741 };
742 mstp5_clks: mstp5_clks@e6150144 {
743 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
744 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
745 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
746 #clock-cells = <1>;
747 clock-indices = <
748 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
749 >;
750 clock-output-names =
751 "thermal", "iic8";
752 };
753 };
7b9ad9a0 754
f0270332
GU		 755 prr: chipid@ff000044 {
756 compatible = "renesas,prr";
757 reg = <0 0xff000044 0 4>;
758 };
759
7b9ad9a0
GU		 760 sysc: system-controller@e6180000 {
761 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
762 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
763
764 pm-domains {
765 pd_c5: c5 {
766 #address-cells = <1>;
767 #size-cells = <0>;
768 #power-domain-cells = <0>;
769
770 pd_c4: c4@0 {
771 reg = <0>;
772 #address-cells = <1>;
773 #size-cells = <0>;
774 #power-domain-cells = <0>;
775
776 pd_a3sg: a3sg@16 {
777 reg = <16>;
778 #power-domain-cells = <0>;
779 };
780
781 pd_a3ex: a3ex@17 {
782 reg = <17>;
783 #power-domain-cells = <0>;
784 };
785
786 pd_a3sp: a3sp@18 {
787 reg = <18>;
788 #address-cells = <1>;
789 #size-cells = <0>;
790 #power-domain-cells = <0>;
791
792 pd_a2us: a2us@19 {
793 reg = <19>;
794 #power-domain-cells = <0>;
795 };
796 };
797
798 pd_a3sm: a3sm@20 {
799 reg = <20>;
800 #address-cells = <1>;
801 #size-cells = <0>;
802 #power-domain-cells = <0>;
803
804 pd_a2sl: a2sl@21 {
805 reg = <21>;
806 #power-domain-cells = <0>;
807 };
808 };
809
810 pd_a3km: a3km@22 {
811 reg = <22>;
812 #address-cells = <1>;
813 #size-cells = <0>;
814 #power-domain-cells = <0>;
815
816 pd_a2kl: a2kl@23 {
817 reg = <23>;
818 #power-domain-cells = <0>;
819 };
820 };
821 };
822
823 pd_c4ma: c4ma@1 {
824 reg = <1>;
825 #power-domain-cells = <0>;
826 };
827
828 pd_c4cl: c4cl@2 {
829 reg = <2>;
830 #power-domain-cells = <0>;
831 };
832
833 pd_d4: d4@3 {
834 reg = <3>;
835 #power-domain-cells = <0>;
836 };
837
838 pd_a4bc: a4bc@4 {
839 reg = <4>;
840 #address-cells = <1>;
841 #size-cells = <0>;
842 #power-domain-cells = <0>;
843
844 pd_a3bc: a3bc@5 {
845 reg = <5>;
846 #power-domain-cells = <0>;
847 };
848 };
849
850 pd_a4l: a4l@6 {
851 reg = <6>;
852 #power-domain-cells = <0>;
853 };
854
855 pd_a4lc: a4lc@7 {
856 reg = <7>;
857 #power-domain-cells = <0>;
858 };
859
860 pd_a4mp: a4mp@8 {
861 reg = <8>;
862 #address-cells = <1>;
863 #size-cells = <0>;
864 #power-domain-cells = <0>;
865
866 pd_a3mp: a3mp@9 {
867 reg = <9>;
868 #power-domain-cells = <0>;
869 };
870
871 pd_a3vc: a3vc@10 {
872 reg = <10>;
873 #power-domain-cells = <0>;
874 };
875 };
876
877 pd_a4sf: a4sf@11 {
878 reg = <11>;
879 #power-domain-cells = <0>;
880 };
881
882 pd_a3r: a3r@12 {
883 reg = <12>;
884 #address-cells = <1>;
885 #size-cells = <0>;
886 #power-domain-cells = <0>;
887
888 pd_a2rv: a2rv@13 {
889 reg = <13>;
890 #power-domain-cells = <0>;
891 };
892
893 pd_a2is: a2is@14 {
894 reg = <14>;
895 #power-domain-cells = <0>;
896 };
897 };
898 };
899 };
900 };
eccf0607 901};
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