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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / r8a73a4.dtsi
CommitLineData
eccf0607
MD		 1/*
2 * Device Tree Source for the r8a73a4 SoC
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
a76809a3 12#include <dt-bindings/clock/r8a73a4-clock.h>
5f75e73c
LP		 13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
eccf0607
MD		 16/ {
17 compatible = "renesas,r8a73a4";
18 interrupt-parent = <&gic>;
26a0d2d4
TY		 19 #address-cells = <2>;
20 #size-cells = <2>;
eccf0607
MD		 21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a15";
29 reg = <0>;
a7869a5b 30 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
eccf0607 31 clock-frequency = <1500000000>;
7b9ad9a0 32 power-domains = <&pd_a2sl>;
c86a4b62 33 next-level-cache = <&L2_CA15>;
eccf0607 34 };
b0da45c6 35
cdaf6417 36 L2_CA15: cache-controller-0 {
b0da45c6 37 compatible = "cache";
b0da45c6
GU		 38 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
39 power-domains = <&pd_a3sm>;
40 cache-unified;
41 cache-level = <2>;
42 };
43
cdaf6417 44 L2_CA7: cache-controller-1 {
b0da45c6 45 compatible = "cache";
b0da45c6
GU		 46 clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
47 power-domains = <&pd_a3km>;
48 cache-unified;
49 cache-level = <2>;
50 };
eccf0607
MD		 51 };
52
7b9ad9a0
GU		 53 ptm {
54 compatible = "arm,coresight-etm3x";
55 power-domains = <&pd_d4>;
56 };
57
eccf0607
MD		 58 timer {
59 compatible = "arm,armv7-timer";
4d5746a3
SH		 60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
eccf0607 64 };
984ca295 65
35dd549c
GU		 66 dbsc1: memory-controller@e6790000 {
67 compatible = "renesas,dbsc-r8a73a4";
68 reg = <0 0xe6790000 0 0x10000>;
7b9ad9a0 69 power-domains = <&pd_a3bc>;
35dd549c
GU		 70 };
71
72 dbsc2: memory-controller@e67a0000 {
73 compatible = "renesas,dbsc-r8a73a4";
74 reg = <0 0xe67a0000 0 0x10000>;
7b9ad9a0 75 power-domains = <&pd_a3bc>;
35dd549c
GU		 76 };
77
7300505a
UH		 78 dmac: dma-multiplexer {
79 compatible = "renesas,shdma-mux";
80 #dma-cells = <1>;
81 dma-channels = <20>;
82 dma-requests = <256>;
83 #address-cells = <2>;
84 #size-cells = <2>;
85 ranges;
86
87 dma0: dma-controller@e6700020 {
88 compatible = "renesas,shdma-r8a73a4";
89 reg = <0 0xe6700020 0 0x89e0>;
4d5746a3
SH		 90 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
91 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
92 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
93 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
94 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
95 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
96 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
97 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
98 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
99 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
100 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
101 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
102 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
103 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
104 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
105 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
106 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
107 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
108 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
109 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
110 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
7300505a
UH		 111 interrupt-names = "error",
112 "ch0", "ch1", "ch2", "ch3",
113 "ch4", "ch5", "ch6", "ch7",
114 "ch8", "ch9", "ch10", "ch11",
115 "ch12", "ch13", "ch14", "ch15",
116 "ch16", "ch17", "ch18", "ch19";
662dd64f 117 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
7b9ad9a0 118 power-domains = <&pd_a3sp>;
7300505a
UH		 119 };
120 };
121
7300505a
UH		 122 i2c5: i2c@e60b0000 {
123 #address-cells = <1>;
124 #size-cells = <0>;
7e9ad4d0 125 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
7300505a 126 reg = <0 0xe60b0000 0 0x428>;
4d5746a3 127 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 128 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
7b9ad9a0 129 power-domains = <&pd_a3sp>;
f7b65230
SH		 130
131 status = "disabled";
132 };
133
134 cmt1: timer@e6130000 {
2cd823fc 135 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
f7b65230 136 reg = <0 0xe6130000 0 0x1004>;
4d5746a3 137 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
662dd64f
UH		 138 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
139 clock-names = "fck";
7b9ad9a0 140 power-domains = <&pd_c5>;
f7b65230
SH		 141
142 renesas,channels-mask = <0xff>;
143
7300505a
UH		 144 status = "disabled";
145 };
146
984ca295 147 irqc0: interrupt-controller@e61c0000 {
34abee39 148 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
984ca295
MD		 149 #interrupt-cells = <2>;
150 interrupt-controller;
26a0d2d4 151 reg = <0 0xe61c0000 0 0x200>;
4d5746a3
SH		 152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1c2a7eb7 184 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
7b9ad9a0 185 power-domains = <&pd_c4>;
984ca295
MD		 186 };
187
188 irqc1: interrupt-controller@e61c0200 {
34abee39 189 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
984ca295
MD		 190 #interrupt-cells = <2>;
191 interrupt-controller;
26a0d2d4 192 reg = <0 0xe61c0200 0 0x200>;
4d5746a3
SH		 193 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1c2a7eb7 219 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
7b9ad9a0 220 power-domains = <&pd_c4>;
984ca295
MD		 221 };
222
5b9906c9 223 pfc: pin-controller@e6050000 {
e4ba0a9b
GU		 224 compatible = "renesas,pfc-r8a73a4";
225 reg = <0 0xe6050000 0 0x9000>;
226 gpio-controller;
227 #gpio-cells = <2>;
17ccec50
GU		 228 gpio-ranges =
229 <&pfc 0 0 31>, <&pfc 32 32 9>,
230 <&pfc 64 64 22>, <&pfc 96 96 31>,
231 <&pfc 128 128 7>, <&pfc 160 160 19>,
232 <&pfc 192 192 31>, <&pfc 224 224 27>,
233 <&pfc 256 256 28>, <&pfc 288 288 21>,
234 <&pfc 320 320 10>;
e4ba0a9b
GU		 235 interrupts-extended =
236 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
237 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
238 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
239 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
240 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
241 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
242 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
243 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
244 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
245 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
246 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
247 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
248 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
249 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
250 <&irqc1 24 0>, <&irqc1 25 0>;
7b9ad9a0 251 power-domains = <&pd_c5>;
e4ba0a9b
GU		 252 };
253
c91cf2fa 254 thermal@e61f0000 {
a2cfaa74 255 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
26a0d2d4
TY		 256 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
257 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
4d5746a3 258 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 259 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
7b9ad9a0 260 power-domains = <&pd_c5>;
c91cf2fa 261 };
f98c1069
GL		 262
263 i2c0: i2c@e6500000 {
264 #address-cells = <1>;
265 #size-cells = <0>;
7e9ad4d0 266 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 267 reg = <0 0xe6500000 0 0x428>;
4d5746a3 268 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 269 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
7b9ad9a0 270 power-domains = <&pd_a3sp>;
eda3a4fa 271 status = "disabled";
f98c1069
GL		 272 };
273
274 i2c1: i2c@e6510000 {
275 #address-cells = <1>;
276 #size-cells = <0>;
7e9ad4d0 277 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 278 reg = <0 0xe6510000 0 0x428>;
4d5746a3 279 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 280 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
7b9ad9a0 281 power-domains = <&pd_a3sp>;
eda3a4fa 282 status = "disabled";
f98c1069
GL		 283 };
284
285 i2c2: i2c@e6520000 {
286 #address-cells = <1>;
287 #size-cells = <0>;
7e9ad4d0 288 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 289 reg = <0 0xe6520000 0 0x428>;
4d5746a3 290 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 291 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
7b9ad9a0 292 power-domains = <&pd_a3sp>;
eda3a4fa 293 status = "disabled";
f98c1069
GL		 294 };
295
296 i2c3: i2c@e6530000 {
297 #address-cells = <1>;
298 #size-cells = <0>;
7e9ad4d0 299 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 300 reg = <0 0xe6530000 0 0x428>;
4d5746a3 301 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 302 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
7b9ad9a0 303 power-domains = <&pd_a3sp>;
eda3a4fa 304 status = "disabled";
f98c1069
GL		 305 };
306
307 i2c4: i2c@e6540000 {
308 #address-cells = <1>;
309 #size-cells = <0>;
7e9ad4d0 310 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 311 reg = <0 0xe6540000 0 0x428>;
4d5746a3 312 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 313 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
7b9ad9a0 314 power-domains = <&pd_a3sp>;
eda3a4fa 315 status = "disabled";
f98c1069
GL		 316 };
317
f98c1069
GL		 318 i2c6: i2c@e6550000 {
319 #address-cells = <1>;
320 #size-cells = <0>;
7e9ad4d0 321 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 322 reg = <0 0xe6550000 0 0x428>;
4d5746a3 323 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 324 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
7b9ad9a0 325 power-domains = <&pd_a3sp>;
eda3a4fa 326 status = "disabled";
f98c1069
GL		 327 };
328
329 i2c7: i2c@e6560000 {
330 #address-cells = <1>;
331 #size-cells = <0>;
7e9ad4d0 332 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 333 reg = <0 0xe6560000 0 0x428>;
4d5746a3 334 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 335 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
7b9ad9a0 336 power-domains = <&pd_a3sp>;
eda3a4fa 337 status = "disabled";
f98c1069
GL		 338 };
339
340 i2c8: i2c@e6570000 {
341 #address-cells = <1>;
342 #size-cells = <0>;
7e9ad4d0 343 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 344 reg = <0 0xe6570000 0 0x428>;
4d5746a3 345 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 346 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
7b9ad9a0 347 power-domains = <&pd_a3sp>;
94f1a03d
SH		 348 status = "disabled";
349 };
350
0b3a0ef6 351 scifb0: serial@e6c20000 {
94f1a03d
SH		 352 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
353 reg = <0 0xe6c20000 0 0x100>;
4d5746a3 354 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 355 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
d4be2f1b 356 clock-names = "fck";
7b9ad9a0 357 power-domains = <&pd_a3sp>;
94f1a03d
SH		 358 status = "disabled";
359 };
360
0b3a0ef6 361 scifb1: serial@e6c30000 {
94f1a03d
SH		 362 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
363 reg = <0 0xe6c30000 0 0x100>;
4d5746a3 364 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 365 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
d4be2f1b 366 clock-names = "fck";
7b9ad9a0 367 power-domains = <&pd_a3sp>;
94f1a03d
SH		 368 status = "disabled";
369 };
370
7300505a
UH		 371 scifa0: serial@e6c40000 {
372 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
373 reg = <0 0xe6c40000 0 0x100>;
4d5746a3 374 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 375 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
d4be2f1b 376 clock-names = "fck";
7b9ad9a0 377 power-domains = <&pd_a3sp>;
7300505a
UH		 378 status = "disabled";
379 };
380
381 scifa1: serial@e6c50000 {
382 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
383 reg = <0 0xe6c50000 0 0x100>;
4d5746a3 384 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 385 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
d4be2f1b 386 clock-names = "fck";
7b9ad9a0 387 power-domains = <&pd_a3sp>;
7300505a
UH		 388 status = "disabled";
389 };
390
0b3a0ef6 391 scifb2: serial@e6ce0000 {
94f1a03d
SH		 392 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
393 reg = <0 0xe6ce0000 0 0x100>;
4d5746a3 394 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 395 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
d4be2f1b 396 clock-names = "fck";
7b9ad9a0 397 power-domains = <&pd_a3sp>;
94f1a03d
SH		 398 status = "disabled";
399 };
400
0b3a0ef6 401 scifb3: serial@e6cf0000 {
94f1a03d
SH		 402 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
403 reg = <0 0xe6cf0000 0 0x100>;
4d5746a3 404 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 405 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
d4be2f1b 406 clock-names = "fck";
7b9ad9a0 407 power-domains = <&pd_c4>;
eda3a4fa 408 status = "disabled";
f98c1069 409 };
369ee2db 410
43304a5f 411 sdhi0: sd@ee100000 {
df1d0584 412 compatible = "renesas,sdhi-r8a73a4";
369ee2db 413 reg = <0 0xee100000 0 0x100>;
4d5746a3 414 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 415 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
7b9ad9a0 416 power-domains = <&pd_a3sp>;
369ee2db
GL		 417 cap-sd-highspeed;
418 status = "disabled";
419 };
420
43304a5f 421 sdhi1: sd@ee120000 {
df1d0584 422 compatible = "renesas,sdhi-r8a73a4";
369ee2db 423 reg = <0 0xee120000 0 0x100>;
4d5746a3 424 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 425 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
7b9ad9a0 426 power-domains = <&pd_a3sp>;
369ee2db
GL		 427 cap-sd-highspeed;
428 status = "disabled";
429 };
430
43304a5f 431 sdhi2: sd@ee140000 {
df1d0584 432 compatible = "renesas,sdhi-r8a73a4";
369ee2db 433 reg = <0 0xee140000 0 0x100>;
4d5746a3 434 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 435 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
7b9ad9a0 436 power-domains = <&pd_a3sp>;
369ee2db
GL		 437 cap-sd-highspeed;
438 status = "disabled";
439 };
7300505a
UH		 440
441 mmcif0: mmc@ee200000 {
5b016174 442 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
7300505a 443 reg = <0 0xee200000 0 0x80>;
4d5746a3 444 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 445 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
7b9ad9a0 446 power-domains = <&pd_a3sp>;
7300505a
UH		 447 reg-io-width = <4>;
448 status = "disabled";
449 };
450
451 mmcif1: mmc@ee220000 {
5b016174 452 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
7300505a 453 reg = <0 0xee220000 0 0x80>;
4d5746a3 454 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 455 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
7b9ad9a0 456 power-domains = <&pd_a3sp>;
7300505a
UH		 457 reg-io-width = <4>;
458 status = "disabled";
459 };
460
461 gic: interrupt-controller@f1001000 {
eaec1d67 462 compatible = "arm,gic-400";
7300505a
UH		 463 #interrupt-cells = <3>;
464 #address-cells = <0>;
465 interrupt-controller;
466 reg = <0 0xf1001000 0 0x1000>,
387720c9 467 <0 0xf1002000 0 0x2000>,
7300505a
UH		 468 <0 0xf1004000 0 0x2000>,
469 <0 0xf1006000 0 0x2000>;
4d5746a3 470 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
c11333cc
GU		 471 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
472 clock-names = "clk";
473 power-domains = <&pd_c4>;
7300505a 474 };
a76809a3 475
271b3ad2
GU		 476 bsc: bus@fec10000 {
477 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
478 "simple-pm-bus";
479 #address-cells = <1>;
480 #size-cells = <1>;
481 ranges = <0 0 0 0x20000000>;
482 reg = <0 0xfec10000 0 0x400>;
483 clocks = <&zb_clk>;
7b9ad9a0 484 power-domains = <&pd_c4>;
271b3ad2
GU		 485 };
486
a76809a3
UH		 487 clocks {
488 #address-cells = <2>;
489 #size-cells = <2>;
490 ranges;
491
492 /* External root clocks */
57c75d1e 493 extalr_clk: extalr {
a76809a3
UH		 494 compatible = "fixed-clock";
495 #clock-cells = <0>;
496 clock-frequency = <32768>;
a76809a3 497 };
57c75d1e 498 extal1_clk: extal1 {
a76809a3
UH		 499 compatible = "fixed-clock";
500 #clock-cells = <0>;
501 clock-frequency = <25000000>;
a76809a3 502 };
57c75d1e 503 extal2_clk: extal2 {
a76809a3
UH		 504 compatible = "fixed-clock";
505 #clock-cells = <0>;
506 clock-frequency = <48000000>;
a76809a3 507 };
57c75d1e 508 fsiack_clk: fsiack {
a76809a3
UH		 509 compatible = "fixed-clock";
510 #clock-cells = <0>;
511 /* This value must be overridden by the board. */
512 clock-frequency = <0>;
a76809a3 513 };
57c75d1e 514 fsibck_clk: fsibck {
a76809a3
UH		 515 compatible = "fixed-clock";
516 #clock-cells = <0>;
517 /* This value must be overridden by the board. */
518 clock-frequency = <0>;
a76809a3
UH		 519 };
520
521 /* Special CPG clocks */
522 cpg_clocks: cpg_clocks@e6150000 {
523 compatible = "renesas,r8a73a4-cpg-clocks";
524 reg = <0 0xe6150000 0 0x10000>;
525 clocks = <&extal1_clk>, <&extal2_clk>;
526 #clock-cells = <1>;
527 clock-output-names = "main", "pll0", "pll1", "pll2",
528 "pll2s", "pll2h", "z", "z2",
529 "i", "m3", "b", "m1", "m2",
530 "zx", "zs", "hp";
531 };
532
533 /* Variable factor clocks (DIV6) */
534 zb_clk: zb_clk@e6150010 {
535 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
536 reg = <0 0xe6150010 0 4>;
537 clocks = <&pll1_div2_clk>, <0>,
538 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
539 #clock-cells = <0>;
540 clock-output-names = "zb";
541 };
57c75d1e 542 sdhi0_clk: sdhi0ck@e6150074 {
a76809a3
UH		 543 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
544 reg = <0 0xe6150074 0 4>;
545 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
546 <0>, <&extal2_clk>;
547 #clock-cells = <0>;
a76809a3 548 };
57c75d1e 549 sdhi1_clk: sdhi1ck@e6150078 {
a76809a3
UH		 550 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
551 reg = <0 0xe6150078 0 4>;
552 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
553 <0>, <&extal2_clk>;
554 #clock-cells = <0>;
a76809a3 555 };
57c75d1e 556 sdhi2_clk: sdhi2ck@e615007c {
a76809a3
UH		 557 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
558 reg = <0 0xe615007c 0 4>;
559 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
560 <0>, <&extal2_clk>;
561 #clock-cells = <0>;
a76809a3 562 };
57c75d1e 563 mmc0_clk: mmc0@e6150240 {
a76809a3
UH		 564 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
565 reg = <0 0xe6150240 0 4>;
566 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
567 <0>, <&extal2_clk>;
568 #clock-cells = <0>;
a76809a3 569 };
57c75d1e 570 mmc1_clk: mmc1@e6150244 {
a76809a3
UH		 571 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
572 reg = <0 0xe6150244 0 4>;
573 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
574 <0>, <&extal2_clk>;
575 #clock-cells = <0>;
a76809a3 576 };
57c75d1e 577 vclk1_clk: vclk1@e6150008 {
a76809a3
UH		 578 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
579 reg = <0 0xe6150008 0 4>;
580 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
581 <0>, <&extal2_clk>, <&main_div2_clk>,
582 <&extalr_clk>, <0>, <0>;
583 #clock-cells = <0>;
a76809a3 584 };
57c75d1e 585 vclk2_clk: vclk2@e615000c {
a76809a3
UH		 586 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
587 reg = <0 0xe615000c 0 4>;
588 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
589 <0>, <&extal2_clk>, <&main_div2_clk>,
590 <&extalr_clk>, <0>, <0>;
591 #clock-cells = <0>;
a76809a3 592 };
57c75d1e 593 vclk3_clk: vclk3@e615001c {
a76809a3
UH		 594 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
595 reg = <0 0xe615001c 0 4>;
596 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
597 <0>, <&extal2_clk>, <&main_div2_clk>,
598 <&extalr_clk>, <0>, <0>;
599 #clock-cells = <0>;
a76809a3 600 };
57c75d1e 601 vclk4_clk: vclk4@e6150014 {
a76809a3
UH		 602 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
603 reg = <0 0xe6150014 0 4>;
604 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
605 <0>, <&extal2_clk>, <&main_div2_clk>,
606 <&extalr_clk>, <0>, <0>;
607 #clock-cells = <0>;
a76809a3 608 };
57c75d1e 609 vclk5_clk: vclk5@e6150034 {
a76809a3
UH		 610 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
611 reg = <0 0xe6150034 0 4>;
612 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
613 <0>, <&extal2_clk>, <&main_div2_clk>,
614 <&extalr_clk>, <0>, <0>;
615 #clock-cells = <0>;
a76809a3 616 };
57c75d1e 617 fsia_clk: fsia@e6150018 {
a76809a3
UH		 618 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
619 reg = <0 0xe6150018 0 4>;
620 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
621 <&fsiack_clk>, <0>;
622 #clock-cells = <0>;
a76809a3 623 };
57c75d1e 624 fsib_clk: fsib@e6150090 {
a76809a3
UH		 625 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
626 reg = <0 0xe6150090 0 4>;
627 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
628 <&fsibck_clk>, <0>;
629 #clock-cells = <0>;
a76809a3 630 };
57c75d1e 631 mp_clk: mp@e6150080 {
a76809a3
UH		 632 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
633 reg = <0 0xe6150080 0 4>;
634 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
635 <&extal2_clk>, <&extal2_clk>;
636 #clock-cells = <0>;
a76809a3 637 };
57c75d1e 638 m4_clk: m4@e6150098 {
a76809a3
UH		 639 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
640 reg = <0 0xe6150098 0 4>;
641 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
642 #clock-cells = <0>;
a76809a3 643 };
57c75d1e 644 hsi_clk: hsi@e615026c {
a76809a3
UH		 645 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
646 reg = <0 0xe615026c 0 4>;
647 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
648 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
649 #clock-cells = <0>;
a76809a3 650 };
57c75d1e 651 spuv_clk: spuv@e6150094 {
a76809a3
UH		 652 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
653 reg = <0 0xe6150094 0 4>;
654 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
655 <&extal2_clk>, <&extal2_clk>;
656 #clock-cells = <0>;
a76809a3
UH		 657 };
658
659 /* Fixed factor clocks */
57c75d1e 660 main_div2_clk: main_div2 {
a76809a3
UH		 661 compatible = "fixed-factor-clock";
662 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
663 #clock-cells = <0>;
664 clock-div = <2>;
665 clock-mult = <1>;
a76809a3 666 };
57c75d1e 667 pll0_div2_clk: pll0_div2 {
a76809a3
UH		 668 compatible = "fixed-factor-clock";
669 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
670 #clock-cells = <0>;
671 clock-div = <2>;
672 clock-mult = <1>;
a76809a3 673 };
57c75d1e 674 pll1_div2_clk: pll1_div2 {
a76809a3
UH		 675 compatible = "fixed-factor-clock";
676 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
677 #clock-cells = <0>;
678 clock-div = <2>;
679 clock-mult = <1>;
a76809a3 680 };
57c75d1e 681 extal1_div2_clk: extal1_div2 {
a76809a3
UH		 682 compatible = "fixed-factor-clock";
683 clocks = <&extal1_clk>;
684 #clock-cells = <0>;
685 clock-div = <2>;
686 clock-mult = <1>;
a76809a3
UH		 687 };
688
689 /* Gate clocks */
690 mstp2_clks: mstp2_clks@e6150138 {
691 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
692 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
693 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
694 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
695 #clock-cells = <1>;
696 clock-indices = <
697 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
698 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
699 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
700 R8A73A4_CLK_DMAC
701 >;
702 clock-output-names =
703 "scifa0", "scifa1", "scifb0", "scifb1",
704 "scifb2", "scifb3", "dmac";
705 };
706 mstp3_clks: mstp3_clks@e615013c {
707 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
708 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
709 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
710 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
711 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
712 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
713 R8A73A4_CLK_HP>, <&cpg_clocks
714 R8A73A4_CLK_HP>, <&extalr_clk>;
715 #clock-cells = <1>;
716 clock-indices = <
717 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
718 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
719 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
720 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
721 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
722 R8A73A4_CLK_CMT1
723 >;
724 clock-output-names =
725 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
726 "mmcif0", "iic6", "iic7", "iic0", "iic1",
727 "cmt1";
728 };
729 mstp4_clks: mstp4_clks@e6150140 {
730 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
731 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
c11333cc
GU		 732 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
733 <&main_div2_clk>,
1c2a7eb7 734 <&cpg_clocks R8A73A4_CLK_HP>,
a76809a3
UH		 735 <&cpg_clocks R8A73A4_CLK_HP>;
736 #clock-cells = <1>;
737 clock-indices = <
c11333cc
GU		 738 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
739 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
740 R8A73A4_CLK_IIC3
a76809a3
UH		 741 >;
742 clock-output-names =
c11333cc 743 "irqc", "intc-sys", "iic5", "iic4", "iic3";
a76809a3
UH		 744 };
745 mstp5_clks: mstp5_clks@e6150144 {
746 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
747 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
748 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
749 #clock-cells = <1>;
750 clock-indices = <
751 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
752 >;
753 clock-output-names =
754 "thermal", "iic8";
755 };
756 };
7b9ad9a0 757
f0270332
GU		 758 prr: chipid@ff000044 {
759 compatible = "renesas,prr";
760 reg = <0 0xff000044 0 4>;
761 };
762
7b9ad9a0
GU		 763 sysc: system-controller@e6180000 {
764 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
765 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
766
767 pm-domains {
768 pd_c5: c5 {
769 #address-cells = <1>;
770 #size-cells = <0>;
771 #power-domain-cells = <0>;
772
773 pd_c4: c4@0 {
774 reg = <0>;
775 #address-cells = <1>;
776 #size-cells = <0>;
777 #power-domain-cells = <0>;
778
779 pd_a3sg: a3sg@16 {
780 reg = <16>;
781 #power-domain-cells = <0>;
782 };
783
784 pd_a3ex: a3ex@17 {
785 reg = <17>;
786 #power-domain-cells = <0>;
787 };
788
789 pd_a3sp: a3sp@18 {
790 reg = <18>;
791 #address-cells = <1>;
792 #size-cells = <0>;
793 #power-domain-cells = <0>;
794
795 pd_a2us: a2us@19 {
796 reg = <19>;
797 #power-domain-cells = <0>;
798 };
799 };
800
801 pd_a3sm: a3sm@20 {
802 reg = <20>;
803 #address-cells = <1>;
804 #size-cells = <0>;
805 #power-domain-cells = <0>;
806
807 pd_a2sl: a2sl@21 {
808 reg = <21>;
809 #power-domain-cells = <0>;
810 };
811 };
812
813 pd_a3km: a3km@22 {
814 reg = <22>;
815 #address-cells = <1>;
816 #size-cells = <0>;
817 #power-domain-cells = <0>;
818
819 pd_a2kl: a2kl@23 {
820 reg = <23>;
821 #power-domain-cells = <0>;
822 };
823 };
824 };
825
826 pd_c4ma: c4ma@1 {
827 reg = <1>;
828 #power-domain-cells = <0>;
829 };
830
831 pd_c4cl: c4cl@2 {
832 reg = <2>;
833 #power-domain-cells = <0>;
834 };
835
836 pd_d4: d4@3 {
837 reg = <3>;
838 #power-domain-cells = <0>;
839 };
840
841 pd_a4bc: a4bc@4 {
842 reg = <4>;
843 #address-cells = <1>;
844 #size-cells = <0>;
845 #power-domain-cells = <0>;
846
847 pd_a3bc: a3bc@5 {
848 reg = <5>;
849 #power-domain-cells = <0>;
850 };
851 };
852
853 pd_a4l: a4l@6 {
854 reg = <6>;
855 #power-domain-cells = <0>;
856 };
857
858 pd_a4lc: a4lc@7 {
859 reg = <7>;
860 #power-domain-cells = <0>;
861 };
862
863 pd_a4mp: a4mp@8 {
864 reg = <8>;
865 #address-cells = <1>;
866 #size-cells = <0>;
867 #power-domain-cells = <0>;
868
869 pd_a3mp: a3mp@9 {
870 reg = <9>;
871 #power-domain-cells = <0>;
872 };
873
874 pd_a3vc: a3vc@10 {
875 reg = <10>;
876 #power-domain-cells = <0>;
877 };
878 };
879
880 pd_a4sf: a4sf@11 {
881 reg = <11>;
882 #power-domain-cells = <0>;
883 };
884
885 pd_a3r: a3r@12 {
886 reg = <12>;
887 #address-cells = <1>;
888 #size-cells = <0>;
889 #power-domain-cells = <0>;
890
891 pd_a2rv: a2rv@13 {
892 reg = <13>;
893 #power-domain-cells = <0>;
894 };
895
896 pd_a2is: a2is@14 {
897 reg = <14>;
898 #power-domain-cells = <0>;
899 };
900 };
901 };
902 };
903 };
eccf0607 904};
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