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Commit | Line | Data |
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755d57b2 MD |
1 | /* |
2 | * Device Tree Source for the r8a7740 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | /include/ "skeleton.dtsi" | |
12 | ||
d9ffd583 | 13 | #include <dt-bindings/clock/r8a7740-clock.h> |
5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/irq.h> |
15 | ||
755d57b2 MD |
16 | / { |
17 | compatible = "renesas,r8a7740"; | |
9ff254ad | 18 | interrupt-parent = <&gic>; |
755d57b2 MD |
19 | |
20 | cpus { | |
b4032013 LP |
21 | #address-cells = <1>; |
22 | #size-cells = <0>; | |
755d57b2 MD |
23 | cpu@0 { |
24 | compatible = "arm,cortex-a9"; | |
b4032013 LP |
25 | device_type = "cpu"; |
26 | reg = <0x0>; | |
63575d8c | 27 | clock-frequency = <800000000>; |
755d57b2 MD |
28 | }; |
29 | }; | |
744fdc8d BH |
30 | |
31 | gic: interrupt-controller@c2800000 { | |
32 | compatible = "arm,cortex-a9-gic"; | |
33 | #interrupt-cells = <3>; | |
744fdc8d BH |
34 | interrupt-controller; |
35 | reg = <0xc2800000 0x1000>, | |
36 | <0xc2000000 0x1000>; | |
37 | }; | |
38 | ||
b21ed4eb MD |
39 | pmu { |
40 | compatible = "arm,cortex-a9-pmu"; | |
5f75e73c | 41 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
b21ed4eb MD |
42 | }; |
43 | ||
c10df265 | 44 | cmt1: timer@e6138000 { |
a2ffcf87 | 45 | compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; |
c10df265 SH |
46 | reg = <0xe6138000 0x170>; |
47 | interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; | |
48 | clocks = <&mstp3_clks R8A7740_CLK_CMT1>; | |
49 | clock-names = "fck"; | |
50 | ||
51 | renesas,channels-mask = <0x3f>; | |
52 | ||
53 | status = "disabled"; | |
54 | }; | |
55 | ||
744fdc8d BH |
56 | /* irqpin0: IRQ0 - IRQ7 */ |
57 | irqpin0: irqpin@e6900000 { | |
96327999 | 58 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
744fdc8d BH |
59 | #interrupt-cells = <2>; |
60 | interrupt-controller; | |
61 | reg = <0xe6900000 4>, | |
62 | <0xe6900010 4>, | |
63 | <0xe6900020 1>, | |
64 | <0xe6900040 1>, | |
65 | <0xe6900060 1>; | |
5f75e73c LP |
66 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
67 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
68 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
69 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
70 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
71 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
72 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
73 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
744fdc8d BH |
74 | }; |
75 | ||
76 | /* irqpin1: IRQ8 - IRQ15 */ | |
77 | irqpin1: irqpin@e6900004 { | |
96327999 | 78 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
744fdc8d BH |
79 | #interrupt-cells = <2>; |
80 | interrupt-controller; | |
81 | reg = <0xe6900004 4>, | |
82 | <0xe6900014 4>, | |
83 | <0xe6900024 1>, | |
84 | <0xe6900044 1>, | |
85 | <0xe6900064 1>; | |
5f75e73c LP |
86 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
87 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
88 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
89 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
90 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
91 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
92 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
93 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
744fdc8d BH |
94 | }; |
95 | ||
96 | /* irqpin2: IRQ16 - IRQ23 */ | |
97 | irqpin2: irqpin@e6900008 { | |
96327999 | 98 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
744fdc8d BH |
99 | #interrupt-cells = <2>; |
100 | interrupt-controller; | |
101 | reg = <0xe6900008 4>, | |
102 | <0xe6900018 4>, | |
103 | <0xe6900028 1>, | |
104 | <0xe6900048 1>, | |
105 | <0xe6900068 1>; | |
5f75e73c LP |
106 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
107 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
108 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
109 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
110 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
111 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
112 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
113 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
744fdc8d BH |
114 | }; |
115 | ||
116 | /* irqpin3: IRQ24 - IRQ31 */ | |
117 | irqpin3: irqpin@e690000c { | |
96327999 | 118 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
744fdc8d BH |
119 | #interrupt-cells = <2>; |
120 | interrupt-controller; | |
121 | reg = <0xe690000c 4>, | |
122 | <0xe690001c 4>, | |
123 | <0xe690002c 1>, | |
124 | <0xe690004c 1>, | |
125 | <0xe690006c 1>; | |
5f75e73c LP |
126 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
127 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
128 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
129 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
130 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
131 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
132 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
133 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
744fdc8d BH |
134 | }; |
135 | ||
08ec67b5 GU |
136 | ether: ethernet@e9a00000 { |
137 | compatible = "renesas,gether-r8a7740"; | |
138 | reg = <0xe9a00000 0x800>, | |
139 | <0xe9a01800 0x800>; | |
08ec67b5 | 140 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
4a7ae2e2 | 141 | clocks = <&mstp3_clks R8A7740_CLK_GETHER>; |
08ec67b5 GU |
142 | phy-mode = "mii"; |
143 | #address-cells = <1>; | |
144 | #size-cells = <0>; | |
145 | status = "disabled"; | |
146 | }; | |
147 | ||
744fdc8d BH |
148 | i2c0: i2c@fff20000 { |
149 | #address-cells = <1>; | |
150 | #size-cells = <0>; | |
5c53f50c | 151 | compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; |
744fdc8d | 152 | reg = <0xfff20000 0x425>; |
5f75e73c LP |
153 | interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH |
154 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
155 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
156 | 0 204 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 157 | clocks = <&mstp1_clks R8A7740_CLK_IIC0>; |
eda3a4fa | 158 | status = "disabled"; |
744fdc8d BH |
159 | }; |
160 | ||
161 | i2c1: i2c@e6c20000 { | |
162 | #address-cells = <1>; | |
163 | #size-cells = <0>; | |
5c53f50c | 164 | compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; |
744fdc8d | 165 | reg = <0xe6c20000 0x425>; |
5f75e73c LP |
166 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH |
167 | 0 71 IRQ_TYPE_LEVEL_HIGH | |
168 | 0 72 IRQ_TYPE_LEVEL_HIGH | |
169 | 0 73 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 170 | clocks = <&mstp3_clks R8A7740_CLK_IIC1>; |
eda3a4fa | 171 | status = "disabled"; |
744fdc8d | 172 | }; |
f36218d2 | 173 | |
fa12355b SH |
174 | scifa0: serial@e6c40000 { |
175 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
176 | reg = <0xe6c40000 0x100>; | |
177 | interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
178 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; |
179 | clock-names = "sci_ick"; | |
fa12355b SH |
180 | status = "disabled"; |
181 | }; | |
182 | ||
183 | scifa1: serial@e6c50000 { | |
184 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
185 | reg = <0xe6c50000 0x100>; | |
186 | interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
187 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; |
188 | clock-names = "sci_ick"; | |
fa12355b SH |
189 | status = "disabled"; |
190 | }; | |
191 | ||
192 | scifa2: serial@e6c60000 { | |
193 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
194 | reg = <0xe6c60000 0x100>; | |
195 | interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
196 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; |
197 | clock-names = "sci_ick"; | |
fa12355b SH |
198 | status = "disabled"; |
199 | }; | |
200 | ||
201 | scifa3: serial@e6c70000 { | |
202 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
203 | reg = <0xe6c70000 0x100>; | |
204 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
205 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; |
206 | clock-names = "sci_ick"; | |
fa12355b SH |
207 | status = "disabled"; |
208 | }; | |
209 | ||
210 | scifa4: serial@e6c80000 { | |
211 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
212 | reg = <0xe6c80000 0x100>; | |
213 | interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
214 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; |
215 | clock-names = "sci_ick"; | |
fa12355b SH |
216 | status = "disabled"; |
217 | }; | |
218 | ||
219 | scifa5: serial@e6cb0000 { | |
220 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
221 | reg = <0xe6cb0000 0x100>; | |
222 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
223 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; |
224 | clock-names = "sci_ick"; | |
fa12355b SH |
225 | status = "disabled"; |
226 | }; | |
227 | ||
228 | scifa6: serial@e6cc0000 { | |
229 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
230 | reg = <0xe6cc0000 0x100>; | |
231 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
232 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; |
233 | clock-names = "sci_ick"; | |
fa12355b SH |
234 | status = "disabled"; |
235 | }; | |
236 | ||
237 | scifa7: serial@e6cd0000 { | |
238 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
239 | reg = <0xe6cd0000 0x100>; | |
240 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
241 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; |
242 | clock-names = "sci_ick"; | |
fa12355b SH |
243 | status = "disabled"; |
244 | }; | |
245 | ||
246 | scifb8: serial@e6c30000 { | |
247 | compatible = "renesas,scifb-r8a7740", "renesas,scifb"; | |
248 | reg = <0xe6c30000 0x100>; | |
249 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
250 | clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; |
251 | clock-names = "sci_ick"; | |
fa12355b SH |
252 | status = "disabled"; |
253 | }; | |
254 | ||
f36218d2 LP |
255 | pfc: pfc@e6050000 { |
256 | compatible = "renesas,pfc-r8a7740"; | |
257 | reg = <0xe6050000 0x8000>, | |
258 | <0xe605800c 0x20>; | |
259 | gpio-controller; | |
260 | #gpio-cells = <2>; | |
778de006 LP |
261 | interrupts-extended = |
262 | <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, | |
263 | <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, | |
264 | <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, | |
265 | <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, | |
266 | <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, | |
267 | <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, | |
268 | <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, | |
269 | <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; | |
f36218d2 | 270 | }; |
fa91515c | 271 | |
8b3e32c1 LP |
272 | tpu: pwm@e6600000 { |
273 | compatible = "renesas,tpu-r8a7740", "renesas,tpu"; | |
274 | reg = <0xe6600000 0x100>; | |
4a7ae2e2 | 275 | clocks = <&mstp3_clks R8A7740_CLK_TPU0>; |
8b3e32c1 LP |
276 | status = "disabled"; |
277 | #pwm-cells = <3>; | |
278 | }; | |
e99d7963 | 279 | |
7d907894 | 280 | mmcif0: mmc@e6bd0000 { |
5c53f50c | 281 | compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; |
e99d7963 | 282 | reg = <0xe6bd0000 0x100>; |
5f75e73c LP |
283 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH |
284 | 0 57 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 285 | clocks = <&mstp3_clks R8A7740_CLK_MMC>; |
e99d7963 GL |
286 | status = "disabled"; |
287 | }; | |
288 | ||
7d907894 | 289 | sdhi0: sd@e6850000 { |
e99d7963 GL |
290 | compatible = "renesas,sdhi-r8a7740"; |
291 | reg = <0xe6850000 0x100>; | |
5f75e73c LP |
292 | interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH |
293 | 0 118 IRQ_TYPE_LEVEL_HIGH | |
294 | 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 295 | clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; |
e99d7963 GL |
296 | cap-sd-highspeed; |
297 | cap-sdio-irq; | |
298 | status = "disabled"; | |
299 | }; | |
300 | ||
7d907894 | 301 | sdhi1: sd@e6860000 { |
e99d7963 GL |
302 | compatible = "renesas,sdhi-r8a7740"; |
303 | reg = <0xe6860000 0x100>; | |
5f75e73c LP |
304 | interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH |
305 | 0 122 IRQ_TYPE_LEVEL_HIGH | |
306 | 0 123 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 307 | clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; |
e99d7963 GL |
308 | cap-sd-highspeed; |
309 | cap-sdio-irq; | |
310 | status = "disabled"; | |
311 | }; | |
7d907894 KM |
312 | |
313 | sdhi2: sd@e6870000 { | |
314 | compatible = "renesas,sdhi-r8a7740"; | |
315 | reg = <0xe6870000 0x100>; | |
5f75e73c LP |
316 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH |
317 | 0 126 IRQ_TYPE_LEVEL_HIGH | |
318 | 0 127 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 319 | clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; |
7d907894 KM |
320 | cap-sd-highspeed; |
321 | cap-sdio-irq; | |
322 | status = "disabled"; | |
323 | }; | |
efcd869b KM |
324 | |
325 | sh_fsi2: sound@fe1f0000 { | |
326 | #sound-dai-cells = <1>; | |
5c53f50c | 327 | compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; |
efcd869b | 328 | reg = <0xfe1f0000 0x400>; |
efcd869b | 329 | interrupts = <0 9 0x4>; |
4a7ae2e2 | 330 | clocks = <&mstp3_clks R8A7740_CLK_FSI>; |
efcd869b KM |
331 | status = "disabled"; |
332 | }; | |
d9ffd583 UH |
333 | |
334 | clocks { | |
335 | #address-cells = <1>; | |
336 | #size-cells = <1>; | |
337 | ranges; | |
338 | ||
339 | /* External root clock */ | |
340 | extalr_clk: extalr_clk { | |
341 | compatible = "fixed-clock"; | |
342 | #clock-cells = <0>; | |
343 | clock-frequency = <32768>; | |
344 | clock-output-names = "extalr"; | |
345 | }; | |
346 | extal1_clk: extal1_clk { | |
347 | compatible = "fixed-clock"; | |
348 | #clock-cells = <0>; | |
349 | clock-frequency = <0>; | |
350 | clock-output-names = "extal1"; | |
351 | }; | |
352 | extal2_clk: extal2_clk { | |
353 | compatible = "fixed-clock"; | |
354 | #clock-cells = <0>; | |
355 | clock-frequency = <0>; | |
356 | clock-output-names = "extal2"; | |
357 | }; | |
358 | dv_clk: dv_clk { | |
359 | compatible = "fixed-clock"; | |
360 | #clock-cells = <0>; | |
361 | clock-frequency = <27000000>; | |
362 | clock-output-names = "dv"; | |
363 | }; | |
364 | fsiack_clk: fsiack_clk { | |
365 | compatible = "fixed-clock"; | |
366 | #clock-cells = <0>; | |
367 | clock-frequency = <0>; | |
368 | clock-output-names = "fsiack"; | |
369 | }; | |
370 | fsibck_clk: fsibck_clk { | |
371 | compatible = "fixed-clock"; | |
372 | #clock-cells = <0>; | |
373 | clock-frequency = <0>; | |
374 | clock-output-names = "fsibck"; | |
375 | }; | |
376 | ||
377 | /* Special CPG clocks */ | |
378 | cpg_clocks: cpg_clocks@e6150000 { | |
379 | compatible = "renesas,r8a7740-cpg-clocks"; | |
380 | reg = <0xe6150000 0x10000>; | |
381 | clocks = <&extal1_clk>, <&extalr_clk>; | |
382 | #clock-cells = <1>; | |
383 | clock-output-names = "system", "pllc0", "pllc1", | |
384 | "pllc2", "r", | |
385 | "usb24s", | |
386 | "i", "zg", "b", "m1", "hp", | |
387 | "hpp", "usbp", "s", "zb", "m3", | |
388 | "cp"; | |
389 | }; | |
390 | ||
391 | /* Variable factor clocks (DIV6) */ | |
392 | sub_clk: sub_clk@e6150080 { | |
393 | compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; | |
394 | reg = <0xe6150080 4>; | |
395 | clocks = <&pllc1_div2_clk>; | |
396 | #clock-cells = <0>; | |
397 | clock-output-names = "sub"; | |
398 | }; | |
399 | ||
400 | /* Fixed factor clocks */ | |
401 | pllc1_div2_clk: pllc1_div2_clk { | |
402 | compatible = "fixed-factor-clock"; | |
403 | clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; | |
404 | #clock-cells = <0>; | |
405 | clock-div = <2>; | |
406 | clock-mult = <1>; | |
407 | clock-output-names = "pllc1_div2"; | |
408 | }; | |
409 | extal1_div2_clk: extal1_div2_clk { | |
410 | compatible = "fixed-factor-clock"; | |
411 | clocks = <&extal1_clk>; | |
412 | #clock-cells = <0>; | |
413 | clock-div = <2>; | |
414 | clock-mult = <1>; | |
415 | clock-output-names = "extal1_div2"; | |
416 | }; | |
417 | ||
418 | /* Gate clocks */ | |
419 | subck_clks: subck_clks@e6150080 { | |
420 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
421 | reg = <0xe6150080 4>; | |
422 | clocks = <&sub_clk>, <&sub_clk>; | |
423 | #clock-cells = <1>; | |
424 | renesas,clock-indices = < | |
425 | R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 | |
426 | >; | |
427 | clock-output-names = | |
428 | "subck", "subck2"; | |
429 | }; | |
430 | mstp1_clks: mstp1_clks@e6150134 { | |
431 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
432 | reg = <0xe6150134 4>, <0xe6150038 4>; | |
433 | clocks = <&cpg_clocks R8A7740_CLK_S>, | |
434 | <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, | |
435 | <&cpg_clocks R8A7740_CLK_B>, | |
436 | <&sub_clk>, <&sub_clk>, | |
437 | <&cpg_clocks R8A7740_CLK_B>; | |
438 | #clock-cells = <1>; | |
439 | renesas,clock-indices = < | |
440 | R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 | |
441 | R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 | |
442 | R8A7740_CLK_LCDC0 | |
443 | >; | |
444 | clock-output-names = | |
445 | "ceu21", "ceu20", "tmu0", "lcdc1", "iic0", | |
446 | "tmu1", "lcdc0"; | |
447 | }; | |
448 | mstp2_clks: mstp2_clks@e6150138 { | |
449 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
450 | reg = <0xe6150138 4>, <0xe6150040 4>; | |
451 | clocks = <&sub_clk>, <&sub_clk>, | |
452 | <&cpg_clocks R8A7740_CLK_HP>, | |
453 | <&cpg_clocks R8A7740_CLK_HP>, | |
454 | <&cpg_clocks R8A7740_CLK_HP>, | |
455 | <&cpg_clocks R8A7740_CLK_HP>, | |
456 | <&sub_clk>, <&sub_clk>, <&sub_clk>, | |
457 | <&sub_clk>, <&sub_clk>, <&sub_clk>, | |
458 | <&sub_clk>; | |
459 | #clock-cells = <1>; | |
460 | renesas,clock-indices = < | |
461 | R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7 | |
462 | R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 | |
463 | R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC | |
464 | R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB | |
465 | R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1 | |
466 | R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3 | |
467 | R8A7740_CLK_SCIFA4 | |
468 | >; | |
469 | clock-output-names = | |
470 | "scifa6", "scifa7", "dmac1", "dmac2", "dmac3", | |
471 | "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", | |
472 | "scifa2", "scifa3", "scifa4"; | |
473 | }; | |
474 | mstp3_clks: mstp3_clks@e615013c { | |
475 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
476 | reg = <0xe615013c 4>, <0xe6150048 4>; | |
477 | clocks = <&cpg_clocks R8A7740_CLK_R>, | |
478 | <&cpg_clocks R8A7740_CLK_HP>, | |
479 | <&sub_clk>, | |
480 | <&cpg_clocks R8A7740_CLK_HP>, | |
481 | <&cpg_clocks R8A7740_CLK_HP>, | |
482 | <&cpg_clocks R8A7740_CLK_HP>, | |
483 | <&cpg_clocks R8A7740_CLK_HP>, | |
484 | <&cpg_clocks R8A7740_CLK_HP>, | |
485 | <&cpg_clocks R8A7740_CLK_HP>; | |
486 | #clock-cells = <1>; | |
487 | renesas,clock-indices = < | |
488 | R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 | |
489 | R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 | |
490 | R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 | |
491 | >; | |
492 | clock-output-names = | |
493 | "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1", | |
494 | "mmc", "gether", "tpu0"; | |
495 | }; | |
496 | mstp4_clks: mstp4_clks@e6150140 { | |
497 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
498 | reg = <0xe6150140 4>, <0xe615004c 4>; | |
499 | clocks = <&cpg_clocks R8A7740_CLK_HP>, | |
500 | <&cpg_clocks R8A7740_CLK_HP>, | |
501 | <&cpg_clocks R8A7740_CLK_HP>, | |
502 | <&cpg_clocks R8A7740_CLK_HP>; | |
503 | #clock-cells = <1>; | |
504 | renesas,clock-indices = < | |
505 | R8A7740_CLK_USBH R8A7740_CLK_SDHI2 | |
506 | R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY | |
507 | >; | |
508 | clock-output-names = | |
509 | "usbhost", "sdhi2", "usbfunc", "usphy"; | |
510 | }; | |
511 | }; | |
755d57b2 | 512 | }; |