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Commit | Line | Data |
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755d57b2 MD |
1 | /* |
2 | * Device Tree Source for the r8a7740 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | /include/ "skeleton.dtsi" | |
12 | ||
d9ffd583 | 13 | #include <dt-bindings/clock/r8a7740-clock.h> |
5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/irq.h> |
15 | ||
755d57b2 MD |
16 | / { |
17 | compatible = "renesas,r8a7740"; | |
9ff254ad | 18 | interrupt-parent = <&gic>; |
755d57b2 MD |
19 | |
20 | cpus { | |
b4032013 LP |
21 | #address-cells = <1>; |
22 | #size-cells = <0>; | |
755d57b2 MD |
23 | cpu@0 { |
24 | compatible = "arm,cortex-a9"; | |
b4032013 LP |
25 | device_type = "cpu"; |
26 | reg = <0x0>; | |
63575d8c | 27 | clock-frequency = <800000000>; |
755d57b2 MD |
28 | }; |
29 | }; | |
744fdc8d BH |
30 | |
31 | gic: interrupt-controller@c2800000 { | |
32 | compatible = "arm,cortex-a9-gic"; | |
33 | #interrupt-cells = <3>; | |
744fdc8d BH |
34 | interrupt-controller; |
35 | reg = <0xc2800000 0x1000>, | |
36 | <0xc2000000 0x1000>; | |
37 | }; | |
38 | ||
b21ed4eb MD |
39 | pmu { |
40 | compatible = "arm,cortex-a9-pmu"; | |
5f75e73c | 41 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
b21ed4eb MD |
42 | }; |
43 | ||
c10df265 | 44 | cmt1: timer@e6138000 { |
a2ffcf87 | 45 | compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; |
c10df265 SH |
46 | reg = <0xe6138000 0x170>; |
47 | interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; | |
48 | clocks = <&mstp3_clks R8A7740_CLK_CMT1>; | |
49 | clock-names = "fck"; | |
50 | ||
51 | renesas,channels-mask = <0x3f>; | |
52 | ||
53 | status = "disabled"; | |
54 | }; | |
55 | ||
744fdc8d BH |
56 | /* irqpin0: IRQ0 - IRQ7 */ |
57 | irqpin0: irqpin@e6900000 { | |
96327999 | 58 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
744fdc8d BH |
59 | #interrupt-cells = <2>; |
60 | interrupt-controller; | |
61 | reg = <0xe6900000 4>, | |
62 | <0xe6900010 4>, | |
63 | <0xe6900020 1>, | |
64 | <0xe6900040 1>, | |
65 | <0xe6900060 1>; | |
5f75e73c LP |
66 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
67 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
68 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
69 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
70 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
71 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
72 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
73 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
3ab84ee9 | 74 | clocks = <&mstp2_clks R8A7740_CLK_INTCA>; |
744fdc8d BH |
75 | }; |
76 | ||
77 | /* irqpin1: IRQ8 - IRQ15 */ | |
78 | irqpin1: irqpin@e6900004 { | |
96327999 | 79 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
744fdc8d BH |
80 | #interrupt-cells = <2>; |
81 | interrupt-controller; | |
82 | reg = <0xe6900004 4>, | |
83 | <0xe6900014 4>, | |
84 | <0xe6900024 1>, | |
85 | <0xe6900044 1>, | |
86 | <0xe6900064 1>; | |
5f75e73c LP |
87 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
88 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
89 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
90 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
91 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
92 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
93 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
94 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
3ab84ee9 | 95 | clocks = <&mstp2_clks R8A7740_CLK_INTCA>; |
744fdc8d BH |
96 | }; |
97 | ||
98 | /* irqpin2: IRQ16 - IRQ23 */ | |
99 | irqpin2: irqpin@e6900008 { | |
96327999 | 100 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
744fdc8d BH |
101 | #interrupt-cells = <2>; |
102 | interrupt-controller; | |
103 | reg = <0xe6900008 4>, | |
104 | <0xe6900018 4>, | |
105 | <0xe6900028 1>, | |
106 | <0xe6900048 1>, | |
107 | <0xe6900068 1>; | |
5f75e73c LP |
108 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
109 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
110 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
111 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
112 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
113 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
114 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
115 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
3ab84ee9 | 116 | clocks = <&mstp2_clks R8A7740_CLK_INTCA>; |
744fdc8d BH |
117 | }; |
118 | ||
119 | /* irqpin3: IRQ24 - IRQ31 */ | |
120 | irqpin3: irqpin@e690000c { | |
96327999 | 121 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
744fdc8d BH |
122 | #interrupt-cells = <2>; |
123 | interrupt-controller; | |
124 | reg = <0xe690000c 4>, | |
125 | <0xe690001c 4>, | |
126 | <0xe690002c 1>, | |
127 | <0xe690004c 1>, | |
128 | <0xe690006c 1>; | |
5f75e73c LP |
129 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
130 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
131 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
132 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
133 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
134 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
135 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
136 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
3ab84ee9 | 137 | clocks = <&mstp2_clks R8A7740_CLK_INTCA>; |
744fdc8d BH |
138 | }; |
139 | ||
08ec67b5 GU |
140 | ether: ethernet@e9a00000 { |
141 | compatible = "renesas,gether-r8a7740"; | |
142 | reg = <0xe9a00000 0x800>, | |
143 | <0xe9a01800 0x800>; | |
08ec67b5 | 144 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
4a7ae2e2 | 145 | clocks = <&mstp3_clks R8A7740_CLK_GETHER>; |
08ec67b5 GU |
146 | phy-mode = "mii"; |
147 | #address-cells = <1>; | |
148 | #size-cells = <0>; | |
149 | status = "disabled"; | |
150 | }; | |
151 | ||
744fdc8d BH |
152 | i2c0: i2c@fff20000 { |
153 | #address-cells = <1>; | |
154 | #size-cells = <0>; | |
5c53f50c | 155 | compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; |
744fdc8d | 156 | reg = <0xfff20000 0x425>; |
5f75e73c LP |
157 | interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH |
158 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
159 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
160 | 0 204 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 161 | clocks = <&mstp1_clks R8A7740_CLK_IIC0>; |
eda3a4fa | 162 | status = "disabled"; |
744fdc8d BH |
163 | }; |
164 | ||
165 | i2c1: i2c@e6c20000 { | |
166 | #address-cells = <1>; | |
167 | #size-cells = <0>; | |
5c53f50c | 168 | compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; |
744fdc8d | 169 | reg = <0xe6c20000 0x425>; |
5f75e73c LP |
170 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH |
171 | 0 71 IRQ_TYPE_LEVEL_HIGH | |
172 | 0 72 IRQ_TYPE_LEVEL_HIGH | |
173 | 0 73 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 174 | clocks = <&mstp3_clks R8A7740_CLK_IIC1>; |
eda3a4fa | 175 | status = "disabled"; |
744fdc8d | 176 | }; |
f36218d2 | 177 | |
fa12355b SH |
178 | scifa0: serial@e6c40000 { |
179 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
180 | reg = <0xe6c40000 0x100>; | |
181 | interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
182 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; |
183 | clock-names = "sci_ick"; | |
fa12355b SH |
184 | status = "disabled"; |
185 | }; | |
186 | ||
187 | scifa1: serial@e6c50000 { | |
188 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
189 | reg = <0xe6c50000 0x100>; | |
190 | interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
191 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; |
192 | clock-names = "sci_ick"; | |
fa12355b SH |
193 | status = "disabled"; |
194 | }; | |
195 | ||
196 | scifa2: serial@e6c60000 { | |
197 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
198 | reg = <0xe6c60000 0x100>; | |
199 | interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; | |
b345aee4 | 200 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; |
4a7ae2e2 | 201 | clock-names = "sci_ick"; |
fa12355b SH |
202 | status = "disabled"; |
203 | }; | |
204 | ||
205 | scifa3: serial@e6c70000 { | |
206 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
207 | reg = <0xe6c70000 0x100>; | |
208 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
209 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; |
210 | clock-names = "sci_ick"; | |
fa12355b SH |
211 | status = "disabled"; |
212 | }; | |
213 | ||
214 | scifa4: serial@e6c80000 { | |
215 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
216 | reg = <0xe6c80000 0x100>; | |
217 | interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
218 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; |
219 | clock-names = "sci_ick"; | |
fa12355b SH |
220 | status = "disabled"; |
221 | }; | |
222 | ||
223 | scifa5: serial@e6cb0000 { | |
224 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
225 | reg = <0xe6cb0000 0x100>; | |
226 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
227 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; |
228 | clock-names = "sci_ick"; | |
fa12355b SH |
229 | status = "disabled"; |
230 | }; | |
231 | ||
232 | scifa6: serial@e6cc0000 { | |
233 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
234 | reg = <0xe6cc0000 0x100>; | |
235 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
236 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; |
237 | clock-names = "sci_ick"; | |
fa12355b SH |
238 | status = "disabled"; |
239 | }; | |
240 | ||
241 | scifa7: serial@e6cd0000 { | |
242 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
243 | reg = <0xe6cd0000 0x100>; | |
244 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
245 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; |
246 | clock-names = "sci_ick"; | |
fa12355b SH |
247 | status = "disabled"; |
248 | }; | |
249 | ||
250 | scifb8: serial@e6c30000 { | |
251 | compatible = "renesas,scifb-r8a7740", "renesas,scifb"; | |
252 | reg = <0xe6c30000 0x100>; | |
253 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 UH |
254 | clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; |
255 | clock-names = "sci_ick"; | |
fa12355b SH |
256 | status = "disabled"; |
257 | }; | |
258 | ||
f36218d2 LP |
259 | pfc: pfc@e6050000 { |
260 | compatible = "renesas,pfc-r8a7740"; | |
261 | reg = <0xe6050000 0x8000>, | |
262 | <0xe605800c 0x20>; | |
263 | gpio-controller; | |
264 | #gpio-cells = <2>; | |
778de006 LP |
265 | interrupts-extended = |
266 | <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, | |
267 | <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, | |
268 | <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, | |
269 | <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, | |
270 | <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, | |
271 | <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, | |
272 | <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, | |
273 | <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; | |
f36218d2 | 274 | }; |
fa91515c | 275 | |
8b3e32c1 LP |
276 | tpu: pwm@e6600000 { |
277 | compatible = "renesas,tpu-r8a7740", "renesas,tpu"; | |
278 | reg = <0xe6600000 0x100>; | |
4a7ae2e2 | 279 | clocks = <&mstp3_clks R8A7740_CLK_TPU0>; |
8b3e32c1 LP |
280 | status = "disabled"; |
281 | #pwm-cells = <3>; | |
282 | }; | |
e99d7963 | 283 | |
7d907894 | 284 | mmcif0: mmc@e6bd0000 { |
5c53f50c | 285 | compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; |
e99d7963 | 286 | reg = <0xe6bd0000 0x100>; |
5f75e73c LP |
287 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH |
288 | 0 57 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 289 | clocks = <&mstp3_clks R8A7740_CLK_MMC>; |
e99d7963 GL |
290 | status = "disabled"; |
291 | }; | |
292 | ||
7d907894 | 293 | sdhi0: sd@e6850000 { |
e99d7963 GL |
294 | compatible = "renesas,sdhi-r8a7740"; |
295 | reg = <0xe6850000 0x100>; | |
5f75e73c LP |
296 | interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH |
297 | 0 118 IRQ_TYPE_LEVEL_HIGH | |
298 | 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 299 | clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; |
e99d7963 GL |
300 | cap-sd-highspeed; |
301 | cap-sdio-irq; | |
302 | status = "disabled"; | |
303 | }; | |
304 | ||
7d907894 | 305 | sdhi1: sd@e6860000 { |
e99d7963 GL |
306 | compatible = "renesas,sdhi-r8a7740"; |
307 | reg = <0xe6860000 0x100>; | |
5f75e73c LP |
308 | interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH |
309 | 0 122 IRQ_TYPE_LEVEL_HIGH | |
310 | 0 123 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 311 | clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; |
e99d7963 GL |
312 | cap-sd-highspeed; |
313 | cap-sdio-irq; | |
314 | status = "disabled"; | |
315 | }; | |
7d907894 KM |
316 | |
317 | sdhi2: sd@e6870000 { | |
318 | compatible = "renesas,sdhi-r8a7740"; | |
319 | reg = <0xe6870000 0x100>; | |
5f75e73c LP |
320 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH |
321 | 0 126 IRQ_TYPE_LEVEL_HIGH | |
322 | 0 127 IRQ_TYPE_LEVEL_HIGH>; | |
4a7ae2e2 | 323 | clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; |
7d907894 KM |
324 | cap-sd-highspeed; |
325 | cap-sdio-irq; | |
326 | status = "disabled"; | |
327 | }; | |
efcd869b KM |
328 | |
329 | sh_fsi2: sound@fe1f0000 { | |
330 | #sound-dai-cells = <1>; | |
5c53f50c | 331 | compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; |
efcd869b | 332 | reg = <0xfe1f0000 0x400>; |
efcd869b | 333 | interrupts = <0 9 0x4>; |
4a7ae2e2 | 334 | clocks = <&mstp3_clks R8A7740_CLK_FSI>; |
efcd869b KM |
335 | status = "disabled"; |
336 | }; | |
d9ffd583 UH |
337 | |
338 | clocks { | |
339 | #address-cells = <1>; | |
340 | #size-cells = <1>; | |
341 | ranges; | |
342 | ||
343 | /* External root clock */ | |
344 | extalr_clk: extalr_clk { | |
345 | compatible = "fixed-clock"; | |
346 | #clock-cells = <0>; | |
347 | clock-frequency = <32768>; | |
348 | clock-output-names = "extalr"; | |
349 | }; | |
350 | extal1_clk: extal1_clk { | |
351 | compatible = "fixed-clock"; | |
352 | #clock-cells = <0>; | |
353 | clock-frequency = <0>; | |
354 | clock-output-names = "extal1"; | |
355 | }; | |
356 | extal2_clk: extal2_clk { | |
357 | compatible = "fixed-clock"; | |
358 | #clock-cells = <0>; | |
359 | clock-frequency = <0>; | |
360 | clock-output-names = "extal2"; | |
361 | }; | |
362 | dv_clk: dv_clk { | |
363 | compatible = "fixed-clock"; | |
364 | #clock-cells = <0>; | |
365 | clock-frequency = <27000000>; | |
366 | clock-output-names = "dv"; | |
367 | }; | |
368 | fsiack_clk: fsiack_clk { | |
369 | compatible = "fixed-clock"; | |
370 | #clock-cells = <0>; | |
371 | clock-frequency = <0>; | |
372 | clock-output-names = "fsiack"; | |
373 | }; | |
374 | fsibck_clk: fsibck_clk { | |
375 | compatible = "fixed-clock"; | |
376 | #clock-cells = <0>; | |
377 | clock-frequency = <0>; | |
378 | clock-output-names = "fsibck"; | |
379 | }; | |
380 | ||
381 | /* Special CPG clocks */ | |
382 | cpg_clocks: cpg_clocks@e6150000 { | |
383 | compatible = "renesas,r8a7740-cpg-clocks"; | |
384 | reg = <0xe6150000 0x10000>; | |
385 | clocks = <&extal1_clk>, <&extalr_clk>; | |
386 | #clock-cells = <1>; | |
387 | clock-output-names = "system", "pllc0", "pllc1", | |
388 | "pllc2", "r", | |
389 | "usb24s", | |
390 | "i", "zg", "b", "m1", "hp", | |
391 | "hpp", "usbp", "s", "zb", "m3", | |
392 | "cp"; | |
393 | }; | |
394 | ||
395 | /* Variable factor clocks (DIV6) */ | |
396 | sub_clk: sub_clk@e6150080 { | |
397 | compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; | |
398 | reg = <0xe6150080 4>; | |
399 | clocks = <&pllc1_div2_clk>; | |
400 | #clock-cells = <0>; | |
401 | clock-output-names = "sub"; | |
402 | }; | |
403 | ||
404 | /* Fixed factor clocks */ | |
405 | pllc1_div2_clk: pllc1_div2_clk { | |
406 | compatible = "fixed-factor-clock"; | |
407 | clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; | |
408 | #clock-cells = <0>; | |
409 | clock-div = <2>; | |
410 | clock-mult = <1>; | |
411 | clock-output-names = "pllc1_div2"; | |
412 | }; | |
413 | extal1_div2_clk: extal1_div2_clk { | |
414 | compatible = "fixed-factor-clock"; | |
415 | clocks = <&extal1_clk>; | |
416 | #clock-cells = <0>; | |
417 | clock-div = <2>; | |
418 | clock-mult = <1>; | |
419 | clock-output-names = "extal1_div2"; | |
420 | }; | |
421 | ||
422 | /* Gate clocks */ | |
423 | subck_clks: subck_clks@e6150080 { | |
424 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
425 | reg = <0xe6150080 4>; | |
426 | clocks = <&sub_clk>, <&sub_clk>; | |
427 | #clock-cells = <1>; | |
428 | renesas,clock-indices = < | |
429 | R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 | |
430 | >; | |
431 | clock-output-names = | |
432 | "subck", "subck2"; | |
433 | }; | |
434 | mstp1_clks: mstp1_clks@e6150134 { | |
435 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
436 | reg = <0xe6150134 4>, <0xe6150038 4>; | |
437 | clocks = <&cpg_clocks R8A7740_CLK_S>, | |
438 | <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, | |
439 | <&cpg_clocks R8A7740_CLK_B>, | |
440 | <&sub_clk>, <&sub_clk>, | |
441 | <&cpg_clocks R8A7740_CLK_B>; | |
442 | #clock-cells = <1>; | |
443 | renesas,clock-indices = < | |
444 | R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 | |
445 | R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 | |
446 | R8A7740_CLK_LCDC0 | |
447 | >; | |
448 | clock-output-names = | |
449 | "ceu21", "ceu20", "tmu0", "lcdc1", "iic0", | |
450 | "tmu1", "lcdc0"; | |
451 | }; | |
452 | mstp2_clks: mstp2_clks@e6150138 { | |
453 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
454 | reg = <0xe6150138 4>, <0xe6150040 4>; | |
3ab84ee9 GU |
455 | clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, |
456 | <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, | |
d9ffd583 UH |
457 | <&cpg_clocks R8A7740_CLK_HP>, |
458 | <&cpg_clocks R8A7740_CLK_HP>, | |
459 | <&cpg_clocks R8A7740_CLK_HP>, | |
460 | <&sub_clk>, <&sub_clk>, <&sub_clk>, | |
461 | <&sub_clk>, <&sub_clk>, <&sub_clk>, | |
462 | <&sub_clk>; | |
463 | #clock-cells = <1>; | |
464 | renesas,clock-indices = < | |
3ab84ee9 GU |
465 | R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA |
466 | R8A7740_CLK_SCIFA7 | |
d9ffd583 UH |
467 | R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 |
468 | R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC | |
469 | R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB | |
470 | R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1 | |
471 | R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3 | |
472 | R8A7740_CLK_SCIFA4 | |
473 | >; | |
474 | clock-output-names = | |
3ab84ee9 GU |
475 | "scifa6", "intca", |
476 | "scifa7", "dmac1", "dmac2", "dmac3", | |
d9ffd583 UH |
477 | "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", |
478 | "scifa2", "scifa3", "scifa4"; | |
479 | }; | |
480 | mstp3_clks: mstp3_clks@e615013c { | |
481 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
482 | reg = <0xe615013c 4>, <0xe6150048 4>; | |
483 | clocks = <&cpg_clocks R8A7740_CLK_R>, | |
484 | <&cpg_clocks R8A7740_CLK_HP>, | |
485 | <&sub_clk>, | |
486 | <&cpg_clocks R8A7740_CLK_HP>, | |
487 | <&cpg_clocks R8A7740_CLK_HP>, | |
488 | <&cpg_clocks R8A7740_CLK_HP>, | |
489 | <&cpg_clocks R8A7740_CLK_HP>, | |
490 | <&cpg_clocks R8A7740_CLK_HP>, | |
491 | <&cpg_clocks R8A7740_CLK_HP>; | |
492 | #clock-cells = <1>; | |
493 | renesas,clock-indices = < | |
494 | R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 | |
495 | R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 | |
496 | R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 | |
497 | >; | |
498 | clock-output-names = | |
499 | "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1", | |
500 | "mmc", "gether", "tpu0"; | |
501 | }; | |
502 | mstp4_clks: mstp4_clks@e6150140 { | |
503 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
504 | reg = <0xe6150140 4>, <0xe615004c 4>; | |
505 | clocks = <&cpg_clocks R8A7740_CLK_HP>, | |
506 | <&cpg_clocks R8A7740_CLK_HP>, | |
507 | <&cpg_clocks R8A7740_CLK_HP>, | |
508 | <&cpg_clocks R8A7740_CLK_HP>; | |
509 | #clock-cells = <1>; | |
510 | renesas,clock-indices = < | |
511 | R8A7740_CLK_USBH R8A7740_CLK_SDHI2 | |
512 | R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY | |
513 | >; | |
514 | clock-output-names = | |
515 | "usbhost", "sdhi2", "usbfunc", "usphy"; | |
516 | }; | |
517 | }; | |
755d57b2 | 518 | }; |