[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / r8a7778.dtsi

/*
 * Device Tree Source for Renesas r8a7778
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * based on r8a7779
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Simon Horman
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/clock/r8a7778-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7778";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <800000000>;
		};
	};

	aliases {
		spi0 = &hspi0;
		spi1 = &hspi1;
		spi2 = &hspi2;
	};

	bsc: bus@1c000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x1c000000>;
	};

	ether: ethernet@fde00000 {
		compatible = "renesas,ether-r8a7778";
		reg = <0xfde00000 0x400>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
		power-domains = <&cpg_clocks>;
		phy-mode = "rmii";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	gic: interrupt-controller@fe438000 {
		compatible = "arm,pl390";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xfe438000 0x1000>,
		      <0xfe430000 0x100>;
	};

	/* irqpin: IRQ0 - IRQ3 */
	irqpin: interrupt-controller@fe78001c {
		compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		status = "disabled"; /* default off */
		reg =	<0xfe78001c 4>,
			<0xfe780010 4>,
			<0xfe780024 4>,
			<0xfe780044 4>,
			<0xfe780064 4>;
		interrupts =   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
				GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
				GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
				GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		sense-bitfield-width = <2>;
	};

	gpio0: gpio@ffc40000 {
		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
		reg = <0xffc40000 0x2c>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio1: gpio@ffc41000 {
		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
		reg = <0xffc41000 0x2c>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio2: gpio@ffc42000 {
		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
		reg = <0xffc42000 0x2c>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio3: gpio@ffc43000 {
		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
		reg = <0xffc43000 0x2c>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio4: gpio@ffc44000 {
		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
		reg = <0xffc44000 0x2c>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 27>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pfc: pfc@fffc0000 {
		compatible = "renesas,pfc-r8a7778";
		reg = <0xfffc0000 0x118>;
	};

	i2c0: i2c@ffc70000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
		reg = <0xffc70000 0x1000>;
		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c1: i2c@ffc71000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
		reg = <0xffc71000 0x1000>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c2: i2c@ffc72000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
		reg = <0xffc72000 0x1000>;
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c3: i2c@ffc73000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
		reg = <0xffc73000 0x1000>;
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	tmu0: timer@ffd80000 {
		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
		reg = <0xffd80000 0x30>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu1: timer@ffd81000 {
		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
		reg = <0xffd81000 0x30>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu2: timer@ffd82000 {
		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
		reg = <0xffd82000 0x30>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	rcar_sound: sound@ffd90000 {
		/*
		 * #sound-dai-cells is required
		 *
		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
		 */
		compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
		reg =	<0xffd90000 0x1000>,	/* SRU */
			<0xffd91000 0x240>,	/* SSI */
			<0xfffe0000 0x24>;	/* ADG */
		clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
			<&mstp3_clks R8A7778_CLK_SSI7>,
			<&mstp3_clks R8A7778_CLK_SSI6>,
			<&mstp3_clks R8A7778_CLK_SSI5>,
			<&mstp3_clks R8A7778_CLK_SSI4>,
			<&mstp0_clks R8A7778_CLK_SSI3>,
			<&mstp0_clks R8A7778_CLK_SSI2>,
			<&mstp0_clks R8A7778_CLK_SSI1>,
			<&mstp0_clks R8A7778_CLK_SSI0>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC8>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC7>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC6>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC5>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC4>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC3>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC2>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC1>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC0>,
			<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
			<&cpg_clocks R8A7778_CLK_S1>;
		clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
			"ssi.3", "ssi.2", "ssi.1", "ssi.0",
			"src.8", "src.7", "src.6", "src.5", "src.4",
			"src.3", "src.2", "src.1", "src.0",
			"clk_a", "clk_b", "clk_c", "clk_i";

		status = "disabled";

		rcar_sound,src {
			src3: src-3 { };
			src4: src-4 { };
			src5: src-5 { };
			src6: src-6 { };
			src7: src-7 { };
			src8: src-8 { };
			src9: src-9 { };
		};

		rcar_sound,ssi {
			ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
			ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
			ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
			ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
			ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
			ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
			ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
		};
	};

	scif0: serial@ffe40000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe40000 0x100>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif1: serial@ffe41000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe41000 0x100>;
		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif2: serial@ffe42000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe42000 0x100>;
		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif3: serial@ffe43000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe43000 0x100>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif4: serial@ffe44000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe44000 0x100>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif5: serial@ffe45000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe45000 0x100>;
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	mmcif: mmc@ffe4e000 {
		compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
		reg = <0xffe4e000 0x100>;
		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7778_CLK_MMC>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	sdhi0: sd@ffe4c000 {
		compatible = "renesas,sdhi-r8a7778";
		reg = <0xffe4c000 0x100>;
		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	sdhi1: sd@ffe4d000 {
		compatible = "renesas,sdhi-r8a7778";
		reg = <0xffe4d000 0x100>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	sdhi2: sd@ffe4f000 {
		compatible = "renesas,sdhi-r8a7778";
		reg = <0xffe4f000 0x100>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	hspi0: spi@fffc7000 {
		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
		reg = <0xfffc7000 0x18>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
		power-domains = <&cpg_clocks>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	hspi1: spi@fffc8000 {
		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
		reg = <0xfffc8000 0x18>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
		power-domains = <&cpg_clocks>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	hspi2: spi@fffc6000 {
		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
		reg = <0xfffc6000 0x18>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
		power-domains = <&cpg_clocks>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* External input clock */
		extal_clk: extal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		/* External SCIF clock */
		scif_clk: scif {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overridden by the board. */
			clock-frequency = <0>;
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@ffc80000 {
			compatible = "renesas,r8a7778-cpg-clocks";
			reg = <0xffc80000 0x80>;
			#clock-cells = <1>;
			clocks = <&extal_clk>;
			clock-output-names = "plla", "pllb", "b",
					     "out", "p", "s", "s1";
			#power-domain-cells = <0>;
		};

		/* Audio clocks; frequencies are set by boards if applicable. */
		audio_clk_a: audio_clk_a {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};
		audio_clk_b: audio_clk_b {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};
		audio_clk_c: audio_clk_c {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};

		/* Fixed ratio clocks */
		g_clk: g {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <12>;
			clock-mult = <1>;
		};
		i_clk: i {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <1>;
		};
		s3_clk: s3 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
		};
		s4_clk: s4 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
		};
		z_clk: z {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <1>;
		};

		/* Gate clocks */
		mstp0_clks: mstp0_clks@ffc80030 {
			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xffc80030 4>;
			clocks = <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_S>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
				R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
				R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
				R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
				R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
				R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
				R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
				R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
				R8A7778_CLK_SSI3 R8A7778_CLK_SRU
				R8A7778_CLK_HSPI
			>;
			clock-output-names =
				"i2c0", "i2c1", "i2c2", "i2c3", "scif0",
				"scif1", "scif2", "scif3", "scif4", "scif5",
				"tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
				"ssi2", "ssi3", "sru", "hspi";
		};
		mstp1_clks: mstp1_clks@ffc80034 {
			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xffc80034 4>, <0xffc80044 4>;
			clocks = <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_S>,
				 <&cpg_clocks R8A7778_CLK_S>,
				 <&cpg_clocks R8A7778_CLK_P>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7778_CLK_ETHER R8A7778_CLK_VIN0
				R8A7778_CLK_VIN1 R8A7778_CLK_USB
			>;
			clock-output-names =
				"ether", "vin0", "vin1", "usb";
		};
		mstp3_clks: mstp3_clks@ffc8003c {
			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xffc8003c 4>;
			clocks = <&s4_clk>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7778_CLK_MMC R8A7778_CLK_SDHI0
				R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
				R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
				R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
				R8A7778_CLK_SSI8
			>;
			clock-output-names =
				"mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
				"ssi5", "ssi6", "ssi7", "ssi8";
		};
		mstp5_clks: mstp5_clks@ffc80054 {
			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xffc80054 4>;
			clocks = <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
				R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
				R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
				R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
				R8A7778_CLK_SRU_SRC8
			>;
			clock-output-names =
				"sru-src0", "sru-src1", "sru-src2",
				"sru-src3", "sru-src4", "sru-src5",
				"sru-src6", "sru-src7", "sru-src8";
		};
	};

	rst: reset-controller@ffcc0000 {
		compatible = "renesas,r8a7778-reset-wdt";
		reg = <0xffcc0000 0x40>;
	};
};
Commit	Line	Data
ccb7cc74 KM	1	/*
	2	* Device Tree Source for Renesas r8a7778
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
	6	*
	7	* based on r8a7779
	8	*
	9	* Copyright (C) 2013 Renesas Solutions Corp.
	10	* Copyright (C) 2013 Simon Horman
	11	*
	12	* This file is licensed under the terms of the GNU General Public License
	13	* version 2. This program is licensed "as is" without any warranty of any
	14	* kind, whether express or implied.
	15	*/
	16
93aa970d	17	#include <dt-bindings/clock/r8a7778-clock.h>
0c34bd1e	18	#include <dt-bindings/interrupt-controller/arm-gic.h>
5f75e73c LP	19	#include <dt-bindings/interrupt-controller/irq.h>
5f75e73c LP	20
ccb7cc74 KM	21	/ {
ccb7cc74 KM	22	compatible = "renesas,r8a7778";
9ff254ad	23	interrupt-parent = <&gic>;
3bc31302 GU	24	#address-cells = <1>;
3bc31302 GU	25	#size-cells = <1>;
ccb7cc74 KM	26
ccb7cc74 KM	27	cpus {
869f92ae MD	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
ccb7cc74	31	cpu@0 {
869f92ae	32	device_type = "cpu";
ccb7cc74	33	compatible = "arm,cortex-a9";
869f92ae MD	34	reg = <0>;
869f92ae MD	35	clock-frequency = <800000000>;
ccb7cc74 KM	36	};
	37	};
	38
a50da085 KM	39	aliases {
	40	spi0 = &hspi0;
	41	spi1 = &hspi1;
	42	spi2 = &hspi2;
	43	};
	44
d4578204 UH	45	bsc: bus@1c000000 {
	46	compatible = "simple-bus";
	47	#address-cells = <1>;
	48	#size-cells = <1>;
	49	ranges = <0 0 0x1c000000>;
	50	};
	51
05cabb83 UH	52	ether: ethernet@fde00000 {
	53	compatible = "renesas,ether-r8a7778";
	54	reg = <0xfde00000 0x400>;
0c34bd1e	55	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
05cabb83	56	clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
a670f366	57	power-domains = <&cpg_clocks>;
05cabb83 UH	58	phy-mode = "rmii";
	59	#address-cells = <1>;
	60	#size-cells = <0>;
	61	status = "disabled";
	62	};
	63
ccb7cc74	64	gic: interrupt-controller@fe438000 {
26828d9e	65	compatible = "arm,pl390";
ccb7cc74 KM	66	#interrupt-cells = <3>;
	67	interrupt-controller;
	68	reg = <0xfe438000 0x1000>,
	69	<0xfe430000 0x100>;
	70	};
0697ccc0	71
87f1ba80	72	/* irqpin: IRQ0 - IRQ3 */
b38150fa	73	irqpin: interrupt-controller@fe78001c {
d79af224	74	compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
87f1ba80 KM	75	#interrupt-cells = <2>;
	76	interrupt-controller;
	77	status = "disabled"; /* default off */
	78	reg = <0xfe78001c 4>,
	79	<0xfe780010 4>,
	80	<0xfe780024 4>,
	81	<0xfe780044 4>,
	82	<0xfe780064 4>;
0c34bd1e SH	83	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
	84	GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
	85	GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
	86	GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
87f1ba80 KM	87	sense-bitfield-width = <2>;
	88	};
	89
aaf7eda8 LP	90	gpio0: gpio@ffc40000 {
	91	compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
	92	reg = <0xffc40000 0x2c>;
0c34bd1e	93	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
aaf7eda8 LP	94	#gpio-cells = <2>;
	95	gpio-controller;
	96	gpio-ranges = <&pfc 0 0 32>;
	97	#interrupt-cells = <2>;
	98	interrupt-controller;
	99	};
	100
	101	gpio1: gpio@ffc41000 {
	102	compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
	103	reg = <0xffc41000 0x2c>;
0c34bd1e	104	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
aaf7eda8 LP	105	#gpio-cells = <2>;
	106	gpio-controller;
	107	gpio-ranges = <&pfc 0 32 32>;
	108	#interrupt-cells = <2>;
	109	interrupt-controller;
	110	};
	111
	112	gpio2: gpio@ffc42000 {
	113	compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
	114	reg = <0xffc42000 0x2c>;
0c34bd1e	115	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
aaf7eda8 LP	116	#gpio-cells = <2>;
	117	gpio-controller;
	118	gpio-ranges = <&pfc 0 64 32>;
	119	#interrupt-cells = <2>;
	120	interrupt-controller;
	121	};
	122
	123	gpio3: gpio@ffc43000 {
	124	compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
	125	reg = <0xffc43000 0x2c>;
0c34bd1e	126	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
aaf7eda8 LP	127	#gpio-cells = <2>;
	128	gpio-controller;
	129	gpio-ranges = <&pfc 0 96 32>;
	130	#interrupt-cells = <2>;
	131	interrupt-controller;
	132	};
	133
	134	gpio4: gpio@ffc44000 {
	135	compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
	136	reg = <0xffc44000 0x2c>;
0c34bd1e	137	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
aaf7eda8 LP	138	#gpio-cells = <2>;
	139	gpio-controller;
	140	gpio-ranges = <&pfc 0 128 27>;
	141	#interrupt-cells = <2>;
	142	interrupt-controller;
	143	};
	144
0697ccc0 LP	145	pfc: pfc@fffc0000 {
0697ccc0 LP	146	compatible = "renesas,pfc-r8a7778";
80d01fee	147	reg = <0xfffc0000 0x118>;
0697ccc0	148	};
3acb51b9 KM	149
	150	i2c0: i2c@ffc70000 {
	151	#address-cells = <1>;
	152	#size-cells = <0>;
eb6f2adf	153	compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
3acb51b9	154	reg = <0xffc70000 0x1000>;
0c34bd1e	155	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
66462be7	156	clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
a670f366	157	power-domains = <&cpg_clocks>;
3acb51b9 KM	158	status = "disabled";
	159	};
	160
	161	i2c1: i2c@ffc71000 {
	162	#address-cells = <1>;
	163	#size-cells = <0>;
eb6f2adf	164	compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
3acb51b9	165	reg = <0xffc71000 0x1000>;
0c34bd1e	166	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
66462be7	167	clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
a670f366	168	power-domains = <&cpg_clocks>;
3acb51b9 KM	169	status = "disabled";
	170	};
	171
	172	i2c2: i2c@ffc72000 {
	173	#address-cells = <1>;
	174	#size-cells = <0>;
eb6f2adf	175	compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
3acb51b9	176	reg = <0xffc72000 0x1000>;
0c34bd1e	177	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
66462be7	178	clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
a670f366	179	power-domains = <&cpg_clocks>;
3acb51b9 KM	180	status = "disabled";
	181	};
	182
	183	i2c3: i2c@ffc73000 {
	184	#address-cells = <1>;
	185	#size-cells = <0>;
eb6f2adf	186	compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
3acb51b9	187	reg = <0xffc73000 0x1000>;
0c34bd1e	188	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
66462be7	189	clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
a670f366	190	power-domains = <&cpg_clocks>;
3acb51b9 KM	191	status = "disabled";
3acb51b9 KM	192	};
f7b90175	193
2109b5a2	194	tmu0: timer@ffd80000 {
45b439c1	195	compatible = "renesas,tmu-r8a7778", "renesas,tmu";
2109b5a2	196	reg = <0xffd80000 0x30>;
0c34bd1e SH	197	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	199	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
66462be7 UH	200	clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
66462be7 UH	201	clock-names = "fck";
a670f366	202	power-domains = <&cpg_clocks>;
2109b5a2 SH	203
	204	#renesas,channels = <3>;
	205
	206	status = "disabled";
	207	};
	208
	209	tmu1: timer@ffd81000 {
45b439c1	210	compatible = "renesas,tmu-r8a7778", "renesas,tmu";
2109b5a2	211	reg = <0xffd81000 0x30>;
0c34bd1e SH	212	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	213	<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
	214	<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
66462be7 UH	215	clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
66462be7 UH	216	clock-names = "fck";
a670f366	217	power-domains = <&cpg_clocks>;
2109b5a2 SH	218
	219	#renesas,channels = <3>;
	220
	221	status = "disabled";
	222	};
	223
	224	tmu2: timer@ffd82000 {
45b439c1	225	compatible = "renesas,tmu-r8a7778", "renesas,tmu";
2109b5a2	226	reg = <0xffd82000 0x30>;
0c34bd1e SH	227	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	228	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	229	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
66462be7 UH	230	clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
66462be7 UH	231	clock-names = "fck";
a670f366	232	power-domains = <&cpg_clocks>;
2109b5a2 SH	233
	234	#renesas,channels = <3>;
	235
	236	status = "disabled";
	237	};
	238
39a96792	239	rcar_sound: sound@ffd90000 {
2020dddd KM	240	/*
	241	* #sound-dai-cells is required
	242	*
	243	* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
	244	* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
	245	*/
39a96792 UH	246	compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
39a96792 UH	247	reg = <0xffd90000 0x1000>, /* SRU */
23640ff2	248	<0xffd91000 0x240>, /* SSI */
39a96792 UH	249	<0xfffe0000 0x24>; /* ADG */
	250	clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
	251	<&mstp3_clks R8A7778_CLK_SSI7>,
	252	<&mstp3_clks R8A7778_CLK_SSI6>,
	253	<&mstp3_clks R8A7778_CLK_SSI5>,
	254	<&mstp3_clks R8A7778_CLK_SSI4>,
	255	<&mstp0_clks R8A7778_CLK_SSI3>,
	256	<&mstp0_clks R8A7778_CLK_SSI2>,
	257	<&mstp0_clks R8A7778_CLK_SSI1>,
	258	<&mstp0_clks R8A7778_CLK_SSI0>,
	259	<&mstp5_clks R8A7778_CLK_SRU_SRC8>,
	260	<&mstp5_clks R8A7778_CLK_SRU_SRC7>,
	261	<&mstp5_clks R8A7778_CLK_SRU_SRC6>,
	262	<&mstp5_clks R8A7778_CLK_SRU_SRC5>,
	263	<&mstp5_clks R8A7778_CLK_SRU_SRC4>,
	264	<&mstp5_clks R8A7778_CLK_SRU_SRC3>,
	265	<&mstp5_clks R8A7778_CLK_SRU_SRC2>,
	266	<&mstp5_clks R8A7778_CLK_SRU_SRC1>,
	267	<&mstp5_clks R8A7778_CLK_SRU_SRC0>,
	268	<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
	269	<&cpg_clocks R8A7778_CLK_S1>;
	270	clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
	271	"ssi.3", "ssi.2", "ssi.1", "ssi.0",
	272	"src.8", "src.7", "src.6", "src.5", "src.4",
	273	"src.3", "src.2", "src.1", "src.0",
	274	"clk_a", "clk_b", "clk_c", "clk_i";
	275
	276	status = "disabled";
	277
	278	rcar_sound,src {
51f20c93 GU	279	src3: src-3 { };
	280	src4: src-4 { };
	281	src5: src-5 { };
	282	src6: src-6 { };
	283	src7: src-7 { };
	284	src8: src-8 { };
	285	src9: src-9 { };
39a96792 UH	286	};
	287
	288	rcar_sound,ssi {
51f20c93 GU	289	ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
	290	ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
	291	ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
	292	ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
	293	ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
	294	ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
	295	ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
39a96792 UH	296	};
	297	};
	298
9930dc8e	299	scif0: serial@ffe40000 {
720e9096 GU	300	compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
720e9096 GU	301	"renesas,scif";
9930dc8e	302	reg = <0xffe40000 0x100>;
0c34bd1e	303	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
5fb544da GU	304	clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
	305	<&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
	306	clock-names = "fck", "brg_int", "scif_clk";
a670f366	307	power-domains = <&cpg_clocks>;
9930dc8e SH	308	status = "disabled";
	309	};
	310
	311	scif1: serial@ffe41000 {
720e9096 GU	312	compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
720e9096 GU	313	"renesas,scif";
9930dc8e	314	reg = <0xffe41000 0x100>;
0c34bd1e	315	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
5fb544da GU	316	clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
	317	<&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
	318	clock-names = "fck", "brg_int", "scif_clk";
a670f366	319	power-domains = <&cpg_clocks>;
9930dc8e SH	320	status = "disabled";
	321	};
	322
	323	scif2: serial@ffe42000 {
720e9096 GU	324	compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
720e9096 GU	325	"renesas,scif";
9930dc8e	326	reg = <0xffe42000 0x100>;
0c34bd1e	327	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
5fb544da GU	328	clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
	329	<&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
	330	clock-names = "fck", "brg_int", "scif_clk";
a670f366	331	power-domains = <&cpg_clocks>;
9930dc8e SH	332	status = "disabled";
	333	};
	334
	335	scif3: serial@ffe43000 {
720e9096 GU	336	compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
720e9096 GU	337	"renesas,scif";
9930dc8e	338	reg = <0xffe43000 0x100>;
0c34bd1e	339	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
5fb544da GU	340	clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
	341	<&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
	342	clock-names = "fck", "brg_int", "scif_clk";
a670f366	343	power-domains = <&cpg_clocks>;
9930dc8e SH	344	status = "disabled";
	345	};
	346
	347	scif4: serial@ffe44000 {
720e9096 GU	348	compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
720e9096 GU	349	"renesas,scif";
9930dc8e	350	reg = <0xffe44000 0x100>;
0c34bd1e	351	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
5fb544da GU	352	clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
	353	<&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
	354	clock-names = "fck", "brg_int", "scif_clk";
a670f366	355	power-domains = <&cpg_clocks>;
9930dc8e SH	356	status = "disabled";
	357	};
	358
	359	scif5: serial@ffe45000 {
720e9096 GU	360	compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
720e9096 GU	361	"renesas,scif";
9930dc8e	362	reg = <0xffe45000 0x100>;
0c34bd1e	363	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
5fb544da GU	364	clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
	365	<&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
	366	clock-names = "fck", "brg_int", "scif_clk";
a670f366	367	power-domains = <&cpg_clocks>;
9930dc8e SH	368	status = "disabled";
	369	};
	370
14e1d914	371	mmcif: mmc@ffe4e000 {
f9be04fe	372	compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
f7b90175	373	reg = <0xffe4e000 0x100>;
0c34bd1e	374	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
66462be7	375	clocks = <&mstp3_clks R8A7778_CLK_MMC>;
a670f366	376	power-domains = <&cpg_clocks>;
f7b90175 KM	377	status = "disabled";
f7b90175 KM	378	};
04cbd889	379
14e1d914	380	sdhi0: sd@ffe4c000 {
04cbd889 KM	381	compatible = "renesas,sdhi-r8a7778";
04cbd889 KM	382	reg = <0xffe4c000 0x100>;
0c34bd1e	383	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
66462be7	384	clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
a670f366	385	power-domains = <&cpg_clocks>;
04cbd889 KM	386	status = "disabled";
	387	};
	388
14e1d914	389	sdhi1: sd@ffe4d000 {
04cbd889 KM	390	compatible = "renesas,sdhi-r8a7778";
04cbd889 KM	391	reg = <0xffe4d000 0x100>;
0c34bd1e	392	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
66462be7	393	clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
a670f366	394	power-domains = <&cpg_clocks>;
04cbd889 KM	395	status = "disabled";
	396	};
	397
14e1d914	398	sdhi2: sd@ffe4f000 {
04cbd889 KM	399	compatible = "renesas,sdhi-r8a7778";
04cbd889 KM	400	reg = <0xffe4f000 0x100>;
0c34bd1e	401	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
66462be7	402	clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
a670f366	403	power-domains = <&cpg_clocks>;
04cbd889 KM	404	status = "disabled";
04cbd889 KM	405	};
ae4273ec	406
a50da085	407	hspi0: spi@fffc7000 {
a34c50d5	408	compatible = "renesas,hspi-r8a7778", "renesas,hspi";
a50da085	409	reg = <0xfffc7000 0x18>;
0c34bd1e	410	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
66462be7	411	clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
a670f366	412	power-domains = <&cpg_clocks>;
a34c50d5 GU	413	#address-cells = <1>;
a34c50d5 GU	414	#size-cells = <0>;
a50da085 KM	415	status = "disabled";
	416	};
	417
	418	hspi1: spi@fffc8000 {
a34c50d5	419	compatible = "renesas,hspi-r8a7778", "renesas,hspi";
a50da085	420	reg = <0xfffc8000 0x18>;
0c34bd1e	421	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
66462be7	422	clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
a670f366	423	power-domains = <&cpg_clocks>;
a34c50d5 GU	424	#address-cells = <1>;
a34c50d5 GU	425	#size-cells = <0>;
a50da085 KM	426	status = "disabled";
	427	};
	428
	429	hspi2: spi@fffc6000 {
a34c50d5	430	compatible = "renesas,hspi-r8a7778", "renesas,hspi";
a50da085	431	reg = <0xfffc6000 0x18>;
0c34bd1e	432	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
66462be7	433	clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
a670f366	434	power-domains = <&cpg_clocks>;
a34c50d5 GU	435	#address-cells = <1>;
a34c50d5 GU	436	#size-cells = <0>;
a50da085 KM	437	status = "disabled";
a50da085 KM	438	};
93aa970d UH	439
	440	clocks {
	441	#address-cells = <1>;
	442	#size-cells = <1>;
	443	ranges;
	444
	445	/* External input clock */
452fc899	446	extal_clk: extal {
93aa970d UH	447	compatible = "fixed-clock";
	448	#clock-cells = <0>;
	449	clock-frequency = <0>;
93aa970d UH	450	};
93aa970d UH	451
5fb544da GU	452	/* External SCIF clock */
	453	scif_clk: scif {
	454	compatible = "fixed-clock";
	455	#clock-cells = <0>;
	456	/* This value must be overridden by the board. */
	457	clock-frequency = <0>;
5fb544da GU	458	};
5fb544da GU	459
93aa970d UH	460	/* Special CPG clocks */
	461	cpg_clocks: cpg_clocks@ffc80000 {
	462	compatible = "renesas,r8a7778-cpg-clocks";
	463	reg = <0xffc80000 0x80>;
	464	#clock-cells = <1>;
	465	clocks = <&extal_clk>;
	466	clock-output-names = "plla", "pllb", "b",
	467	"out", "p", "s", "s1";
a670f366	468	#power-domain-cells = <0>;
93aa970d UH	469	};
	470
	471	/* Audio clocks; frequencies are set by boards if applicable. */
	472	audio_clk_a: audio_clk_a {
	473	compatible = "fixed-clock";
	474	#clock-cells = <0>;
93aa970d UH	475	};
	476	audio_clk_b: audio_clk_b {
	477	compatible = "fixed-clock";
	478	#clock-cells = <0>;
93aa970d UH	479	};
	480	audio_clk_c: audio_clk_c {
	481	compatible = "fixed-clock";
	482	#clock-cells = <0>;
93aa970d UH	483	};
	484
	485	/* Fixed ratio clocks */
452fc899	486	g_clk: g {
93aa970d UH	487	compatible = "fixed-factor-clock";
	488	clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
	489	#clock-cells = <0>;
	490	clock-div = <12>;
	491	clock-mult = <1>;
93aa970d	492	};
452fc899	493	i_clk: i {
93aa970d UH	494	compatible = "fixed-factor-clock";
	495	clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
	496	#clock-cells = <0>;
	497	clock-div = <1>;
	498	clock-mult = <1>;
93aa970d	499	};
452fc899	500	s3_clk: s3 {
93aa970d UH	501	compatible = "fixed-factor-clock";
	502	clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
	503	#clock-cells = <0>;
	504	clock-div = <4>;
	505	clock-mult = <1>;
93aa970d	506	};
452fc899	507	s4_clk: s4 {
93aa970d UH	508	compatible = "fixed-factor-clock";
	509	clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
	510	#clock-cells = <0>;
	511	clock-div = <8>;
	512	clock-mult = <1>;
93aa970d	513	};
452fc899	514	z_clk: z {
93aa970d UH	515	compatible = "fixed-factor-clock";
	516	clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
	517	#clock-cells = <0>;
	518	clock-div = <1>;
	519	clock-mult = <1>;
93aa970d UH	520	};
	521
	522	/* Gate clocks */
	523	mstp0_clks: mstp0_clks@ffc80030 {
	524	compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
	525	reg = <0xffc80030 4>;
	526	clocks = <&cpg_clocks R8A7778_CLK_P>,
	527	<&cpg_clocks R8A7778_CLK_P>,
	528	<&cpg_clocks R8A7778_CLK_P>,
	529	<&cpg_clocks R8A7778_CLK_P>,
	530	<&cpg_clocks R8A7778_CLK_P>,
	531	<&cpg_clocks R8A7778_CLK_P>,
	532	<&cpg_clocks R8A7778_CLK_P>,
	533	<&cpg_clocks R8A7778_CLK_P>,
	534	<&cpg_clocks R8A7778_CLK_P>,
	535	<&cpg_clocks R8A7778_CLK_P>,
	536	<&cpg_clocks R8A7778_CLK_P>,
	537	<&cpg_clocks R8A7778_CLK_P>,
	538	<&cpg_clocks R8A7778_CLK_P>,
	539	<&cpg_clocks R8A7778_CLK_P>,
	540	<&cpg_clocks R8A7778_CLK_P>,
	541	<&cpg_clocks R8A7778_CLK_P>,
	542	<&cpg_clocks R8A7778_CLK_P>,
	543	<&cpg_clocks R8A7778_CLK_P>,
	544	<&cpg_clocks R8A7778_CLK_S>;
	545	#clock-cells = <1>;
	546	clock-indices = <
	547	R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
	548	R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
	549	R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
	550	R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
	551	R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
	552	R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
	553	R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
	554	R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
	555	R8A7778_CLK_SSI3 R8A7778_CLK_SRU
	556	R8A7778_CLK_HSPI
	557	>;
	558	clock-output-names =
	559	"i2c0", "i2c1", "i2c2", "i2c3", "scif0",
	560	"scif1", "scif2", "scif3", "scif4", "scif5",
	561	"tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
	562	"ssi2", "ssi3", "sru", "hspi";
	563	};
	564	mstp1_clks: mstp1_clks@ffc80034 {
	565	compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
	566	reg = <0xffc80034 4>, <0xffc80044 4>;
	567	clocks = <&cpg_clocks R8A7778_CLK_P>,
	568	<&cpg_clocks R8A7778_CLK_S>,
	569	<&cpg_clocks R8A7778_CLK_S>,
	570	<&cpg_clocks R8A7778_CLK_P>;
	571	#clock-cells = <1>;
	572	clock-indices = <
	573	R8A7778_CLK_ETHER R8A7778_CLK_VIN0
	574	R8A7778_CLK_VIN1 R8A7778_CLK_USB
	575	>;
	576	clock-output-names =
	577	"ether", "vin0", "vin1", "usb";
	578	};
	579	mstp3_clks: mstp3_clks@ffc8003c {
	580	compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
	581	reg = <0xffc8003c 4>;
	582	clocks = <&s4_clk>,
	583	<&cpg_clocks R8A7778_CLK_P>,
584	<&cpg_clocks R8A7778_CLK_P>,
585	<&cpg_clocks R8A7778_CLK_P>,
586	<&cpg_clocks R8A7778_CLK_P>,
587	<&cpg_clocks R8A7778_CLK_P>,
588	<&cpg_clocks R8A7778_CLK_P>,
589	<&cpg_clocks R8A7778_CLK_P>,
590	<&cpg_clocks R8A7778_CLK_P>;
591	#clock-cells = <1>;
592	clock-indices = <
593	R8A7778_CLK_MMC R8A7778_CLK_SDHI0
594	R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
595	R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
596	R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
597	R8A7778_CLK_SSI8
598	>;
599	clock-output-names =
600	"mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
601	"ssi5", "ssi6", "ssi7", "ssi8";
602	};
603	mstp5_clks: mstp5_clks@ffc80054 {
604	compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
605	reg = <0xffc80054 4>;
606	clocks = <&cpg_clocks R8A7778_CLK_P>,
607	<&cpg_clocks R8A7778_CLK_P>,
608	<&cpg_clocks R8A7778_CLK_P>,
609	<&cpg_clocks R8A7778_CLK_P>,
610	<&cpg_clocks R8A7778_CLK_P>,
611	<&cpg_clocks R8A7778_CLK_P>,
612	<&cpg_clocks R8A7778_CLK_P>,
613	<&cpg_clocks R8A7778_CLK_P>,
614	<&cpg_clocks R8A7778_CLK_P>;
615	#clock-cells = <1>;
616	clock-indices = <
617	R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
618	R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
619	R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
620	R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
621	R8A7778_CLK_SRU_SRC8
622	>;
623	clock-output-names =
624	"sru-src0", "sru-src1", "sru-src2",
625	"sru-src3", "sru-src4", "sru-src5",
626	"sru-src6", "sru-src7", "sru-src8";
627	};
628	};
e2eb35e0 GU	629
	630	rst: reset-controller@ffcc0000 {
	631	compatible = "renesas,r8a7778-reset-wdt";
	632	reg = <0xffcc0000 0x40>;
	633	};
ccb7cc74	634	};