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Commit | Line | Data |
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ccb7cc74 KM |
1 | /* |
2 | * Device Tree Source for Renesas r8a7778 | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
6 | * | |
7 | * based on r8a7779 | |
8 | * | |
9 | * Copyright (C) 2013 Renesas Solutions Corp. | |
10 | * Copyright (C) 2013 Simon Horman | |
11 | * | |
12 | * This file is licensed under the terms of the GNU General Public License | |
13 | * version 2. This program is licensed "as is" without any warranty of any | |
14 | * kind, whether express or implied. | |
15 | */ | |
16 | ||
17 | /include/ "skeleton.dtsi" | |
18 | ||
93aa970d | 19 | #include <dt-bindings/clock/r8a7778-clock.h> |
5f75e73c LP |
20 | #include <dt-bindings/interrupt-controller/irq.h> |
21 | ||
ccb7cc74 KM |
22 | / { |
23 | compatible = "renesas,r8a7778"; | |
9ff254ad | 24 | interrupt-parent = <&gic>; |
ccb7cc74 KM |
25 | |
26 | cpus { | |
869f92ae MD |
27 | #address-cells = <1>; |
28 | #size-cells = <0>; | |
29 | ||
ccb7cc74 | 30 | cpu@0 { |
869f92ae | 31 | device_type = "cpu"; |
ccb7cc74 | 32 | compatible = "arm,cortex-a9"; |
869f92ae MD |
33 | reg = <0>; |
34 | clock-frequency = <800000000>; | |
ccb7cc74 KM |
35 | }; |
36 | }; | |
37 | ||
a50da085 KM |
38 | aliases { |
39 | spi0 = &hspi0; | |
40 | spi1 = &hspi1; | |
41 | spi2 = &hspi2; | |
42 | }; | |
43 | ||
d4578204 UH |
44 | bsc: bus@1c000000 { |
45 | compatible = "simple-bus"; | |
46 | #address-cells = <1>; | |
47 | #size-cells = <1>; | |
48 | ranges = <0 0 0x1c000000>; | |
49 | }; | |
50 | ||
05cabb83 UH |
51 | ether: ethernet@fde00000 { |
52 | compatible = "renesas,ether-r8a7778"; | |
53 | reg = <0xfde00000 0x400>; | |
54 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; | |
55 | clocks = <&mstp1_clks R8A7778_CLK_ETHER>; | |
56 | phy-mode = "rmii"; | |
57 | #address-cells = <1>; | |
58 | #size-cells = <0>; | |
59 | status = "disabled"; | |
60 | }; | |
61 | ||
ccb7cc74 KM |
62 | gic: interrupt-controller@fe438000 { |
63 | compatible = "arm,cortex-a9-gic"; | |
64 | #interrupt-cells = <3>; | |
65 | interrupt-controller; | |
66 | reg = <0xfe438000 0x1000>, | |
67 | <0xfe430000 0x100>; | |
68 | }; | |
0697ccc0 | 69 | |
87f1ba80 KM |
70 | /* irqpin: IRQ0 - IRQ3 */ |
71 | irqpin: irqpin@fe78001c { | |
d79af224 | 72 | compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin"; |
87f1ba80 KM |
73 | #interrupt-cells = <2>; |
74 | interrupt-controller; | |
75 | status = "disabled"; /* default off */ | |
76 | reg = <0xfe78001c 4>, | |
77 | <0xfe780010 4>, | |
78 | <0xfe780024 4>, | |
79 | <0xfe780044 4>, | |
80 | <0xfe780064 4>; | |
5f75e73c LP |
81 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH |
82 | 0 28 IRQ_TYPE_LEVEL_HIGH | |
83 | 0 29 IRQ_TYPE_LEVEL_HIGH | |
84 | 0 30 IRQ_TYPE_LEVEL_HIGH>; | |
87f1ba80 KM |
85 | sense-bitfield-width = <2>; |
86 | }; | |
87 | ||
aaf7eda8 LP |
88 | gpio0: gpio@ffc40000 { |
89 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; | |
90 | reg = <0xffc40000 0x2c>; | |
5f75e73c | 91 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; |
aaf7eda8 LP |
92 | #gpio-cells = <2>; |
93 | gpio-controller; | |
94 | gpio-ranges = <&pfc 0 0 32>; | |
95 | #interrupt-cells = <2>; | |
96 | interrupt-controller; | |
97 | }; | |
98 | ||
99 | gpio1: gpio@ffc41000 { | |
100 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; | |
101 | reg = <0xffc41000 0x2c>; | |
5f75e73c | 102 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; |
aaf7eda8 LP |
103 | #gpio-cells = <2>; |
104 | gpio-controller; | |
105 | gpio-ranges = <&pfc 0 32 32>; | |
106 | #interrupt-cells = <2>; | |
107 | interrupt-controller; | |
108 | }; | |
109 | ||
110 | gpio2: gpio@ffc42000 { | |
111 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; | |
112 | reg = <0xffc42000 0x2c>; | |
5f75e73c | 113 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; |
aaf7eda8 LP |
114 | #gpio-cells = <2>; |
115 | gpio-controller; | |
116 | gpio-ranges = <&pfc 0 64 32>; | |
117 | #interrupt-cells = <2>; | |
118 | interrupt-controller; | |
119 | }; | |
120 | ||
121 | gpio3: gpio@ffc43000 { | |
122 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; | |
123 | reg = <0xffc43000 0x2c>; | |
5f75e73c | 124 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; |
aaf7eda8 LP |
125 | #gpio-cells = <2>; |
126 | gpio-controller; | |
127 | gpio-ranges = <&pfc 0 96 32>; | |
128 | #interrupt-cells = <2>; | |
129 | interrupt-controller; | |
130 | }; | |
131 | ||
132 | gpio4: gpio@ffc44000 { | |
133 | compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; | |
134 | reg = <0xffc44000 0x2c>; | |
5f75e73c | 135 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; |
aaf7eda8 LP |
136 | #gpio-cells = <2>; |
137 | gpio-controller; | |
138 | gpio-ranges = <&pfc 0 128 27>; | |
139 | #interrupt-cells = <2>; | |
140 | interrupt-controller; | |
141 | }; | |
142 | ||
0697ccc0 LP |
143 | pfc: pfc@fffc0000 { |
144 | compatible = "renesas,pfc-r8a7778"; | |
80d01fee | 145 | reg = <0xfffc0000 0x118>; |
0697ccc0 | 146 | }; |
3acb51b9 KM |
147 | |
148 | i2c0: i2c@ffc70000 { | |
149 | #address-cells = <1>; | |
150 | #size-cells = <0>; | |
151 | compatible = "renesas,i2c-r8a7778"; | |
152 | reg = <0xffc70000 0x1000>; | |
5f75e73c | 153 | interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; |
66462be7 | 154 | clocks = <&mstp0_clks R8A7778_CLK_I2C0>; |
3acb51b9 KM |
155 | status = "disabled"; |
156 | }; | |
157 | ||
158 | i2c1: i2c@ffc71000 { | |
159 | #address-cells = <1>; | |
160 | #size-cells = <0>; | |
161 | compatible = "renesas,i2c-r8a7778"; | |
162 | reg = <0xffc71000 0x1000>; | |
5f75e73c | 163 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; |
66462be7 | 164 | clocks = <&mstp0_clks R8A7778_CLK_I2C1>; |
3acb51b9 KM |
165 | status = "disabled"; |
166 | }; | |
167 | ||
168 | i2c2: i2c@ffc72000 { | |
169 | #address-cells = <1>; | |
170 | #size-cells = <0>; | |
171 | compatible = "renesas,i2c-r8a7778"; | |
172 | reg = <0xffc72000 0x1000>; | |
5f75e73c | 173 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; |
66462be7 | 174 | clocks = <&mstp0_clks R8A7778_CLK_I2C2>; |
3acb51b9 KM |
175 | status = "disabled"; |
176 | }; | |
177 | ||
178 | i2c3: i2c@ffc73000 { | |
179 | #address-cells = <1>; | |
180 | #size-cells = <0>; | |
181 | compatible = "renesas,i2c-r8a7778"; | |
182 | reg = <0xffc73000 0x1000>; | |
5f75e73c | 183 | interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; |
66462be7 | 184 | clocks = <&mstp0_clks R8A7778_CLK_I2C3>; |
3acb51b9 KM |
185 | status = "disabled"; |
186 | }; | |
f7b90175 | 187 | |
2109b5a2 | 188 | tmu0: timer@ffd80000 { |
45b439c1 | 189 | compatible = "renesas,tmu-r8a7778", "renesas,tmu"; |
2109b5a2 SH |
190 | reg = <0xffd80000 0x30>; |
191 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, | |
192 | <0 33 IRQ_TYPE_LEVEL_HIGH>, | |
193 | <0 34 IRQ_TYPE_LEVEL_HIGH>; | |
66462be7 UH |
194 | clocks = <&mstp0_clks R8A7778_CLK_TMU0>; |
195 | clock-names = "fck"; | |
2109b5a2 SH |
196 | |
197 | #renesas,channels = <3>; | |
198 | ||
199 | status = "disabled"; | |
200 | }; | |
201 | ||
202 | tmu1: timer@ffd81000 { | |
45b439c1 | 203 | compatible = "renesas,tmu-r8a7778", "renesas,tmu"; |
2109b5a2 SH |
204 | reg = <0xffd81000 0x30>; |
205 | interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, | |
206 | <0 37 IRQ_TYPE_LEVEL_HIGH>, | |
207 | <0 38 IRQ_TYPE_LEVEL_HIGH>; | |
66462be7 UH |
208 | clocks = <&mstp0_clks R8A7778_CLK_TMU1>; |
209 | clock-names = "fck"; | |
2109b5a2 SH |
210 | |
211 | #renesas,channels = <3>; | |
212 | ||
213 | status = "disabled"; | |
214 | }; | |
215 | ||
216 | tmu2: timer@ffd82000 { | |
45b439c1 | 217 | compatible = "renesas,tmu-r8a7778", "renesas,tmu"; |
2109b5a2 SH |
218 | reg = <0xffd82000 0x30>; |
219 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, | |
220 | <0 41 IRQ_TYPE_LEVEL_HIGH>, | |
221 | <0 42 IRQ_TYPE_LEVEL_HIGH>; | |
66462be7 UH |
222 | clocks = <&mstp0_clks R8A7778_CLK_TMU2>; |
223 | clock-names = "fck"; | |
2109b5a2 SH |
224 | |
225 | #renesas,channels = <3>; | |
226 | ||
227 | status = "disabled"; | |
228 | }; | |
229 | ||
39a96792 UH |
230 | rcar_sound: sound@ffd90000 { |
231 | #sound-dai-cells = <1>; | |
232 | compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1"; | |
233 | reg = <0xffd90000 0x1000>, /* SRU */ | |
234 | <0xffd91000 0x1240>, /* SSI */ | |
235 | <0xfffe0000 0x24>; /* ADG */ | |
236 | clocks = <&mstp3_clks R8A7778_CLK_SSI8>, | |
237 | <&mstp3_clks R8A7778_CLK_SSI7>, | |
238 | <&mstp3_clks R8A7778_CLK_SSI6>, | |
239 | <&mstp3_clks R8A7778_CLK_SSI5>, | |
240 | <&mstp3_clks R8A7778_CLK_SSI4>, | |
241 | <&mstp0_clks R8A7778_CLK_SSI3>, | |
242 | <&mstp0_clks R8A7778_CLK_SSI2>, | |
243 | <&mstp0_clks R8A7778_CLK_SSI1>, | |
244 | <&mstp0_clks R8A7778_CLK_SSI0>, | |
245 | <&mstp5_clks R8A7778_CLK_SRU_SRC8>, | |
246 | <&mstp5_clks R8A7778_CLK_SRU_SRC7>, | |
247 | <&mstp5_clks R8A7778_CLK_SRU_SRC6>, | |
248 | <&mstp5_clks R8A7778_CLK_SRU_SRC5>, | |
249 | <&mstp5_clks R8A7778_CLK_SRU_SRC4>, | |
250 | <&mstp5_clks R8A7778_CLK_SRU_SRC3>, | |
251 | <&mstp5_clks R8A7778_CLK_SRU_SRC2>, | |
252 | <&mstp5_clks R8A7778_CLK_SRU_SRC1>, | |
253 | <&mstp5_clks R8A7778_CLK_SRU_SRC0>, | |
254 | <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, | |
255 | <&cpg_clocks R8A7778_CLK_S1>; | |
256 | clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", | |
257 | "ssi.3", "ssi.2", "ssi.1", "ssi.0", | |
258 | "src.8", "src.7", "src.6", "src.5", "src.4", | |
259 | "src.3", "src.2", "src.1", "src.0", | |
260 | "clk_a", "clk_b", "clk_c", "clk_i"; | |
261 | ||
262 | status = "disabled"; | |
263 | ||
264 | rcar_sound,src { | |
265 | src3: src@3 { }; | |
266 | src4: src@4 { }; | |
267 | src5: src@5 { }; | |
268 | src6: src@6 { }; | |
269 | src7: src@7 { }; | |
270 | src8: src@8 { }; | |
271 | src9: src@9 { }; | |
272 | }; | |
273 | ||
274 | rcar_sound,ssi { | |
275 | ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; }; | |
276 | ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; }; | |
277 | ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; | |
278 | ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; | |
279 | ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; | |
280 | ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; | |
281 | ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; | |
282 | }; | |
283 | }; | |
284 | ||
9930dc8e SH |
285 | scif0: serial@ffe40000 { |
286 | compatible = "renesas,scif-r8a7778", "renesas,scif"; | |
287 | reg = <0xffe40000 0x100>; | |
288 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; | |
66462be7 UH |
289 | clocks = <&mstp0_clks R8A7778_CLK_SCIF0>; |
290 | clock-names = "sci_ick"; | |
9930dc8e SH |
291 | status = "disabled"; |
292 | }; | |
293 | ||
294 | scif1: serial@ffe41000 { | |
295 | compatible = "renesas,scif-r8a7778", "renesas,scif"; | |
296 | reg = <0xffe41000 0x100>; | |
297 | interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; | |
66462be7 UH |
298 | clocks = <&mstp0_clks R8A7778_CLK_SCIF1>; |
299 | clock-names = "sci_ick"; | |
9930dc8e SH |
300 | status = "disabled"; |
301 | }; | |
302 | ||
303 | scif2: serial@ffe42000 { | |
304 | compatible = "renesas,scif-r8a7778", "renesas,scif"; | |
305 | reg = <0xffe42000 0x100>; | |
306 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; | |
66462be7 UH |
307 | clocks = <&mstp0_clks R8A7778_CLK_SCIF2>; |
308 | clock-names = "sci_ick"; | |
9930dc8e SH |
309 | status = "disabled"; |
310 | }; | |
311 | ||
312 | scif3: serial@ffe43000 { | |
313 | compatible = "renesas,scif-r8a7778", "renesas,scif"; | |
314 | reg = <0xffe43000 0x100>; | |
315 | interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; | |
66462be7 UH |
316 | clocks = <&mstp0_clks R8A7778_CLK_SCIF3>; |
317 | clock-names = "sci_ick"; | |
9930dc8e SH |
318 | status = "disabled"; |
319 | }; | |
320 | ||
321 | scif4: serial@ffe44000 { | |
322 | compatible = "renesas,scif-r8a7778", "renesas,scif"; | |
323 | reg = <0xffe44000 0x100>; | |
324 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; | |
66462be7 UH |
325 | clocks = <&mstp0_clks R8A7778_CLK_SCIF4>; |
326 | clock-names = "sci_ick"; | |
9930dc8e SH |
327 | status = "disabled"; |
328 | }; | |
329 | ||
330 | scif5: serial@ffe45000 { | |
331 | compatible = "renesas,scif-r8a7778", "renesas,scif"; | |
332 | reg = <0xffe45000 0x100>; | |
333 | interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; | |
66462be7 UH |
334 | clocks = <&mstp0_clks R8A7778_CLK_SCIF5>; |
335 | clock-names = "sci_ick"; | |
9930dc8e SH |
336 | status = "disabled"; |
337 | }; | |
338 | ||
14e1d914 | 339 | mmcif: mmc@ffe4e000 { |
f7b90175 KM |
340 | compatible = "renesas,sh-mmcif"; |
341 | reg = <0xffe4e000 0x100>; | |
5f75e73c | 342 | interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; |
66462be7 | 343 | clocks = <&mstp3_clks R8A7778_CLK_MMC>; |
f7b90175 KM |
344 | status = "disabled"; |
345 | }; | |
04cbd889 | 346 | |
14e1d914 | 347 | sdhi0: sd@ffe4c000 { |
04cbd889 KM |
348 | compatible = "renesas,sdhi-r8a7778"; |
349 | reg = <0xffe4c000 0x100>; | |
5f75e73c | 350 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; |
66462be7 | 351 | clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; |
04cbd889 KM |
352 | status = "disabled"; |
353 | }; | |
354 | ||
14e1d914 | 355 | sdhi1: sd@ffe4d000 { |
04cbd889 KM |
356 | compatible = "renesas,sdhi-r8a7778"; |
357 | reg = <0xffe4d000 0x100>; | |
5f75e73c | 358 | interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; |
66462be7 | 359 | clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; |
04cbd889 KM |
360 | status = "disabled"; |
361 | }; | |
362 | ||
14e1d914 | 363 | sdhi2: sd@ffe4f000 { |
04cbd889 KM |
364 | compatible = "renesas,sdhi-r8a7778"; |
365 | reg = <0xffe4f000 0x100>; | |
5f75e73c | 366 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
66462be7 | 367 | clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; |
04cbd889 KM |
368 | status = "disabled"; |
369 | }; | |
ae4273ec | 370 | |
a50da085 | 371 | hspi0: spi@fffc7000 { |
a34c50d5 | 372 | compatible = "renesas,hspi-r8a7778", "renesas,hspi"; |
a50da085 | 373 | reg = <0xfffc7000 0x18>; |
d6dd1313 | 374 | interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; |
66462be7 | 375 | clocks = <&mstp0_clks R8A7778_CLK_HSPI>; |
a34c50d5 GU |
376 | #address-cells = <1>; |
377 | #size-cells = <0>; | |
a50da085 KM |
378 | status = "disabled"; |
379 | }; | |
380 | ||
381 | hspi1: spi@fffc8000 { | |
a34c50d5 | 382 | compatible = "renesas,hspi-r8a7778", "renesas,hspi"; |
a50da085 | 383 | reg = <0xfffc8000 0x18>; |
d6dd1313 | 384 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
66462be7 | 385 | clocks = <&mstp0_clks R8A7778_CLK_HSPI>; |
a34c50d5 GU |
386 | #address-cells = <1>; |
387 | #size-cells = <0>; | |
a50da085 KM |
388 | status = "disabled"; |
389 | }; | |
390 | ||
391 | hspi2: spi@fffc6000 { | |
a34c50d5 | 392 | compatible = "renesas,hspi-r8a7778", "renesas,hspi"; |
a50da085 | 393 | reg = <0xfffc6000 0x18>; |
d6dd1313 | 394 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
66462be7 | 395 | clocks = <&mstp0_clks R8A7778_CLK_HSPI>; |
a34c50d5 GU |
396 | #address-cells = <1>; |
397 | #size-cells = <0>; | |
a50da085 KM |
398 | status = "disabled"; |
399 | }; | |
93aa970d UH |
400 | |
401 | clocks { | |
402 | #address-cells = <1>; | |
403 | #size-cells = <1>; | |
404 | ranges; | |
405 | ||
406 | /* External input clock */ | |
407 | extal_clk: extal_clk { | |
408 | compatible = "fixed-clock"; | |
409 | #clock-cells = <0>; | |
410 | clock-frequency = <0>; | |
411 | clock-output-names = "extal"; | |
412 | }; | |
413 | ||
414 | /* Special CPG clocks */ | |
415 | cpg_clocks: cpg_clocks@ffc80000 { | |
416 | compatible = "renesas,r8a7778-cpg-clocks"; | |
417 | reg = <0xffc80000 0x80>; | |
418 | #clock-cells = <1>; | |
419 | clocks = <&extal_clk>; | |
420 | clock-output-names = "plla", "pllb", "b", | |
421 | "out", "p", "s", "s1"; | |
422 | }; | |
423 | ||
424 | /* Audio clocks; frequencies are set by boards if applicable. */ | |
425 | audio_clk_a: audio_clk_a { | |
426 | compatible = "fixed-clock"; | |
427 | #clock-cells = <0>; | |
428 | clock-output-names = "audio_clk_a"; | |
429 | }; | |
430 | audio_clk_b: audio_clk_b { | |
431 | compatible = "fixed-clock"; | |
432 | #clock-cells = <0>; | |
433 | clock-output-names = "audio_clk_b"; | |
434 | }; | |
435 | audio_clk_c: audio_clk_c { | |
436 | compatible = "fixed-clock"; | |
437 | #clock-cells = <0>; | |
438 | clock-output-names = "audio_clk_c"; | |
439 | }; | |
440 | ||
441 | /* Fixed ratio clocks */ | |
442 | g_clk: g_clk { | |
443 | compatible = "fixed-factor-clock"; | |
444 | clocks = <&cpg_clocks R8A7778_CLK_PLLA>; | |
445 | #clock-cells = <0>; | |
446 | clock-div = <12>; | |
447 | clock-mult = <1>; | |
448 | clock-output-names = "g"; | |
449 | }; | |
450 | i_clk: i_clk { | |
451 | compatible = "fixed-factor-clock"; | |
452 | clocks = <&cpg_clocks R8A7778_CLK_PLLA>; | |
453 | #clock-cells = <0>; | |
454 | clock-div = <1>; | |
455 | clock-mult = <1>; | |
456 | clock-output-names = "i"; | |
457 | }; | |
458 | s3_clk: s3_clk { | |
459 | compatible = "fixed-factor-clock"; | |
460 | clocks = <&cpg_clocks R8A7778_CLK_PLLA>; | |
461 | #clock-cells = <0>; | |
462 | clock-div = <4>; | |
463 | clock-mult = <1>; | |
464 | clock-output-names = "s3"; | |
465 | }; | |
466 | s4_clk: s4_clk { | |
467 | compatible = "fixed-factor-clock"; | |
468 | clocks = <&cpg_clocks R8A7778_CLK_PLLA>; | |
469 | #clock-cells = <0>; | |
470 | clock-div = <8>; | |
471 | clock-mult = <1>; | |
472 | clock-output-names = "s4"; | |
473 | }; | |
474 | z_clk: z_clk { | |
475 | compatible = "fixed-factor-clock"; | |
476 | clocks = <&cpg_clocks R8A7778_CLK_PLLB>; | |
477 | #clock-cells = <0>; | |
478 | clock-div = <1>; | |
479 | clock-mult = <1>; | |
480 | clock-output-names = "z"; | |
481 | }; | |
482 | ||
483 | /* Gate clocks */ | |
484 | mstp0_clks: mstp0_clks@ffc80030 { | |
485 | compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
486 | reg = <0xffc80030 4>; | |
487 | clocks = <&cpg_clocks R8A7778_CLK_P>, | |
488 | <&cpg_clocks R8A7778_CLK_P>, | |
489 | <&cpg_clocks R8A7778_CLK_P>, | |
490 | <&cpg_clocks R8A7778_CLK_P>, | |
491 | <&cpg_clocks R8A7778_CLK_P>, | |
492 | <&cpg_clocks R8A7778_CLK_P>, | |
493 | <&cpg_clocks R8A7778_CLK_P>, | |
494 | <&cpg_clocks R8A7778_CLK_P>, | |
495 | <&cpg_clocks R8A7778_CLK_P>, | |
496 | <&cpg_clocks R8A7778_CLK_P>, | |
497 | <&cpg_clocks R8A7778_CLK_P>, | |
498 | <&cpg_clocks R8A7778_CLK_P>, | |
499 | <&cpg_clocks R8A7778_CLK_P>, | |
500 | <&cpg_clocks R8A7778_CLK_P>, | |
501 | <&cpg_clocks R8A7778_CLK_P>, | |
502 | <&cpg_clocks R8A7778_CLK_P>, | |
503 | <&cpg_clocks R8A7778_CLK_P>, | |
504 | <&cpg_clocks R8A7778_CLK_P>, | |
505 | <&cpg_clocks R8A7778_CLK_S>; | |
506 | #clock-cells = <1>; | |
507 | clock-indices = < | |
508 | R8A7778_CLK_I2C0 R8A7778_CLK_I2C1 | |
509 | R8A7778_CLK_I2C2 R8A7778_CLK_I2C3 | |
510 | R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 | |
511 | R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 | |
512 | R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 | |
513 | R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 | |
514 | R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 | |
515 | R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 | |
516 | R8A7778_CLK_SSI3 R8A7778_CLK_SRU | |
517 | R8A7778_CLK_HSPI | |
518 | >; | |
519 | clock-output-names = | |
520 | "i2c0", "i2c1", "i2c2", "i2c3", "scif0", | |
521 | "scif1", "scif2", "scif3", "scif4", "scif5", | |
522 | "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", | |
523 | "ssi2", "ssi3", "sru", "hspi"; | |
524 | }; | |
525 | mstp1_clks: mstp1_clks@ffc80034 { | |
526 | compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
527 | reg = <0xffc80034 4>, <0xffc80044 4>; | |
528 | clocks = <&cpg_clocks R8A7778_CLK_P>, | |
529 | <&cpg_clocks R8A7778_CLK_S>, | |
530 | <&cpg_clocks R8A7778_CLK_S>, | |
531 | <&cpg_clocks R8A7778_CLK_P>; | |
532 | #clock-cells = <1>; | |
533 | clock-indices = < | |
534 | R8A7778_CLK_ETHER R8A7778_CLK_VIN0 | |
535 | R8A7778_CLK_VIN1 R8A7778_CLK_USB | |
536 | >; | |
537 | clock-output-names = | |
538 | "ether", "vin0", "vin1", "usb"; | |
539 | }; | |
540 | mstp3_clks: mstp3_clks@ffc8003c { | |
541 | compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
542 | reg = <0xffc8003c 4>; | |
543 | clocks = <&s4_clk>, | |
544 | <&cpg_clocks R8A7778_CLK_P>, | |
545 | <&cpg_clocks R8A7778_CLK_P>, | |
546 | <&cpg_clocks R8A7778_CLK_P>, | |
547 | <&cpg_clocks R8A7778_CLK_P>, | |
548 | <&cpg_clocks R8A7778_CLK_P>, | |
549 | <&cpg_clocks R8A7778_CLK_P>, | |
550 | <&cpg_clocks R8A7778_CLK_P>, | |
551 | <&cpg_clocks R8A7778_CLK_P>; | |
552 | #clock-cells = <1>; | |
553 | clock-indices = < | |
554 | R8A7778_CLK_MMC R8A7778_CLK_SDHI0 | |
555 | R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2 | |
556 | R8A7778_CLK_SSI4 R8A7778_CLK_SSI5 | |
557 | R8A7778_CLK_SSI6 R8A7778_CLK_SSI7 | |
558 | R8A7778_CLK_SSI8 | |
559 | >; | |
560 | clock-output-names = | |
561 | "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4", | |
562 | "ssi5", "ssi6", "ssi7", "ssi8"; | |
563 | }; | |
564 | mstp5_clks: mstp5_clks@ffc80054 { | |
565 | compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
566 | reg = <0xffc80054 4>; | |
567 | clocks = <&cpg_clocks R8A7778_CLK_P>, | |
568 | <&cpg_clocks R8A7778_CLK_P>, | |
569 | <&cpg_clocks R8A7778_CLK_P>, | |
570 | <&cpg_clocks R8A7778_CLK_P>, | |
571 | <&cpg_clocks R8A7778_CLK_P>, | |
572 | <&cpg_clocks R8A7778_CLK_P>, | |
573 | <&cpg_clocks R8A7778_CLK_P>, | |
574 | <&cpg_clocks R8A7778_CLK_P>, | |
575 | <&cpg_clocks R8A7778_CLK_P>; | |
576 | #clock-cells = <1>; | |
577 | clock-indices = < | |
578 | R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1 | |
579 | R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3 | |
580 | R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5 | |
581 | R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7 | |
582 | R8A7778_CLK_SRU_SRC8 | |
583 | >; | |
584 | clock-output-names = | |
585 | "sru-src0", "sru-src1", "sru-src2", | |
586 | "sru-src3", "sru-src4", "sru-src5", | |
587 | "sru-src6", "sru-src7", "sru-src8"; | |
588 | }; | |
589 | }; | |
ccb7cc74 | 590 | }; |