projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| cdbfaf64 | 1 | // SPDX-License-Identifier: GPL-2.0 |
| c58a1545 | 2 | /* |
| af69e340 | 3 | * Device Tree Source for the R-Car H1 (R8A77790) SoC |
| c58a1545 SH |
4 | * |
| 5 | * Copyright (C) 2013 Renesas Solutions Corp. | |
| 6 | * Copyright (C) 2013 Simon Horman | |
| c58a1545 SH |
7 | */ |
| 8 | ||
| 1e851538 | 9 | #include <dt-bindings/clock/r8a7779-clock.h> |
| cea80654 | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 5f75e73c | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
| b2df3aa4 | 12 | #include <dt-bindings/power/r8a7779-sysc.h> |
| 5f75e73c | 13 | |
| c58a1545 SH |
14 | / { |
| 15 | compatible = "renesas,r8a7779"; | |
| 9ff254ad | 16 | interrupt-parent = <&gic>; |
| 1cfc0c03 GU |
17 | #address-cells = <1>; |
| 18 | #size-cells = <1>; | |
| c58a1545 SH |
19 | |
| 20 | cpus { | |
| 21 | #address-cells = <1>; | |
| 22 | #size-cells = <0>; | |
| 23 | ||
| 24 | cpu@0 { | |
| 25 | device_type = "cpu"; | |
| 26 | compatible = "arm,cortex-a9"; | |
| 27 | reg = <0>; | |
| 6b060f93 | 28 | clock-frequency = <1000000000>; |
| fa9f95a3 | 29 | clocks = <&cpg_clocks R8A7779_CLK_Z>; |
| c58a1545 SH |
30 | }; |
| 31 | cpu@1 { | |
| 32 | device_type = "cpu"; | |
| 33 | compatible = "arm,cortex-a9"; | |
| 34 | reg = <1>; | |
| 6b060f93 | 35 | clock-frequency = <1000000000>; |
| fa9f95a3 | 36 | clocks = <&cpg_clocks R8A7779_CLK_Z>; |
| b2df3aa4 | 37 | power-domains = <&sysc R8A7779_PD_ARM1>; |
| c58a1545 SH |
38 | }; |
| 39 | cpu@2 { | |
| 40 | device_type = "cpu"; | |
| 41 | compatible = "arm,cortex-a9"; | |
| 42 | reg = <2>; | |
| 6b060f93 | 43 | clock-frequency = <1000000000>; |
| fa9f95a3 | 44 | clocks = <&cpg_clocks R8A7779_CLK_Z>; |
| b2df3aa4 | 45 | power-domains = <&sysc R8A7779_PD_ARM2>; |
| c58a1545 SH |
46 | }; |
| 47 | cpu@3 { | |
| 48 | device_type = "cpu"; | |
| 49 | compatible = "arm,cortex-a9"; | |
| 50 | reg = <3>; | |
| 6b060f93 | 51 | clock-frequency = <1000000000>; |
| fa9f95a3 | 52 | clocks = <&cpg_clocks R8A7779_CLK_Z>; |
| b2df3aa4 | 53 | power-domains = <&sysc R8A7779_PD_ARM3>; |
| c58a1545 SH |
54 | }; |
| 55 | }; | |
| 56 | ||
| 3c3f6ad3 SH |
57 | aliases { |
| 58 | spi0 = &hspi0; | |
| 59 | spi1 = &hspi1; | |
| 60 | spi2 = &hspi2; | |
| 61 | }; | |
| 62 | ||
| cc703a59 SH |
63 | gic: interrupt-controller@f0001000 { |
| 64 | compatible = "arm,cortex-a9-gic"; | |
| 65 | #interrupt-cells = <3>; | |
| 66 | interrupt-controller; | |
| 67 | reg = <0xf0001000 0x1000>, | |
| 68 | <0xf0000100 0x100>; | |
| 69 | }; | |
| 10e8d4f6 | 70 | |
| cea80654 MD |
71 | timer@f0000600 { |
| 72 | compatible = "arm,cortex-a9-twd-timer"; | |
| 73 | reg = <0xf0000600 0x20>; | |
| 74 | interrupts = <GIC_PPI 13 | |
| e6c24882 | 75 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; |
| cea80654 MD |
76 | clocks = <&cpg_clocks R8A7779_CLK_ZS>; |
| 77 | }; | |
| 78 | ||
| f5c771b5 | 79 | gpio0: gpio@ffc40000 { |
| 88cb141b | 80 | compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; |
| f5c771b5 | 81 | reg = <0xffc40000 0x2c>; |
| 854b7733 | 82 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| f5c771b5 LP |
83 | #gpio-cells = <2>; |
| 84 | gpio-controller; | |
| 85 | gpio-ranges = <&pfc 0 0 32>; | |
| 86 | #interrupt-cells = <2>; | |
| 87 | interrupt-controller; | |
| 88 | }; | |
| 89 | ||
| 90 | gpio1: gpio@ffc41000 { | |
| 88cb141b | 91 | compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; |
| f5c771b5 | 92 | reg = <0xffc41000 0x2c>; |
| 854b7733 | 93 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| f5c771b5 LP |
94 | #gpio-cells = <2>; |
| 95 | gpio-controller; | |
| 96 | gpio-ranges = <&pfc 0 32 32>; | |
| 97 | #interrupt-cells = <2>; | |
| 98 | interrupt-controller; | |
| 99 | }; | |
| 100 | ||
| 101 | gpio2: gpio@ffc42000 { | |
| 88cb141b | 102 | compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; |
| f5c771b5 | 103 | reg = <0xffc42000 0x2c>; |
| 854b7733 | 104 | interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| f5c771b5 LP |
105 | #gpio-cells = <2>; |
| 106 | gpio-controller; | |
| 107 | gpio-ranges = <&pfc 0 64 32>; | |
| 108 | #interrupt-cells = <2>; | |
| 109 | interrupt-controller; | |
| 110 | }; | |
| 111 | ||
| 112 | gpio3: gpio@ffc43000 { | |
| 88cb141b | 113 | compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; |
| f5c771b5 | 114 | reg = <0xffc43000 0x2c>; |
| 854b7733 | 115 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| f5c771b5 LP |
116 | #gpio-cells = <2>; |
| 117 | gpio-controller; | |
| 118 | gpio-ranges = <&pfc 0 96 32>; | |
| 119 | #interrupt-cells = <2>; | |
| 120 | interrupt-controller; | |
| 121 | }; | |
| 122 | ||
| 123 | gpio4: gpio@ffc44000 { | |
| 88cb141b | 124 | compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; |
| f5c771b5 | 125 | reg = <0xffc44000 0x2c>; |
| 854b7733 | 126 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| f5c771b5 LP |
127 | #gpio-cells = <2>; |
| 128 | gpio-controller; | |
| 129 | gpio-ranges = <&pfc 0 128 32>; | |
| 130 | #interrupt-cells = <2>; | |
| 131 | interrupt-controller; | |
| 132 | }; | |
| 133 | ||
| 134 | gpio5: gpio@ffc45000 { | |
| 88cb141b | 135 | compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; |
| f5c771b5 | 136 | reg = <0xffc45000 0x2c>; |
| 854b7733 | 137 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
| f5c771b5 LP |
138 | #gpio-cells = <2>; |
| 139 | gpio-controller; | |
| 140 | gpio-ranges = <&pfc 0 160 32>; | |
| 141 | #interrupt-cells = <2>; | |
| 142 | interrupt-controller; | |
| 143 | }; | |
| 144 | ||
| 145 | gpio6: gpio@ffc46000 { | |
| 88cb141b | 146 | compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; |
| f5c771b5 | 147 | reg = <0xffc46000 0x2c>; |
| 854b7733 | 148 | interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; |
| f5c771b5 LP |
149 | #gpio-cells = <2>; |
| 150 | gpio-controller; | |
| 151 | gpio-ranges = <&pfc 0 192 9>; | |
| 152 | #interrupt-cells = <2>; | |
| 153 | interrupt-controller; | |
| 154 | }; | |
| 155 | ||
| 7bf46d0b | 156 | irqpin0: interrupt-controller@fe78001c { |
| 11ef0340 | 157 | compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; |
| 24603f3c | 158 | #interrupt-cells = <2>; |
| 84b47dfc | 159 | status = "disabled"; |
| 24603f3c GL |
160 | interrupt-controller; |
| 161 | reg = <0xfe78001c 4>, | |
| 162 | <0xfe780010 4>, | |
| 163 | <0xfe780024 4>, | |
| 164 | <0xfe780044 4>, | |
| 7bf46d0b MD |
165 | <0xfe780064 4>, |
| 166 | <0xfe780000 4>; | |
| 854b7733 SH |
167 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH |
| 168 | GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH | |
| 169 | GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH | |
| 170 | GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 24603f3c GL |
171 | sense-bitfield-width = <2>; |
| 172 | }; | |
| 173 | ||
| 98724b7e | 174 | i2c0: i2c@ffc70000 { |
| 10e8d4f6 SH |
175 | #address-cells = <1>; |
| 176 | #size-cells = <0>; | |
| 137d27f1 | 177 | compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; |
| 10e8d4f6 | 178 | reg = <0xffc70000 0x1000>; |
| 854b7733 | 179 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 3325cbe8 | 180 | clocks = <&mstp0_clks R8A7779_CLK_I2C0>; |
| 751e29bb | 181 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| eda3a4fa | 182 | status = "disabled"; |
| 10e8d4f6 SH |
183 | }; |
| 184 | ||
| 98724b7e | 185 | i2c1: i2c@ffc71000 { |
| 10e8d4f6 SH |
186 | #address-cells = <1>; |
| 187 | #size-cells = <0>; | |
| 137d27f1 | 188 | compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; |
| 10e8d4f6 | 189 | reg = <0xffc71000 0x1000>; |
| 854b7733 | 190 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 3325cbe8 | 191 | clocks = <&mstp0_clks R8A7779_CLK_I2C1>; |
| 751e29bb | 192 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| eda3a4fa | 193 | status = "disabled"; |
| 10e8d4f6 SH |
194 | }; |
| 195 | ||
| 98724b7e | 196 | i2c2: i2c@ffc72000 { |
| 10e8d4f6 SH |
197 | #address-cells = <1>; |
| 198 | #size-cells = <0>; | |
| 137d27f1 | 199 | compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; |
| 10e8d4f6 | 200 | reg = <0xffc72000 0x1000>; |
| 854b7733 | 201 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| 3325cbe8 | 202 | clocks = <&mstp0_clks R8A7779_CLK_I2C2>; |
| 751e29bb | 203 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| eda3a4fa | 204 | status = "disabled"; |
| 10e8d4f6 SH |
205 | }; |
| 206 | ||
| 98724b7e | 207 | i2c3: i2c@ffc73000 { |
| 10e8d4f6 SH |
208 | #address-cells = <1>; |
| 209 | #size-cells = <0>; | |
| 137d27f1 | 210 | compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; |
| 10e8d4f6 | 211 | reg = <0xffc73000 0x1000>; |
| 854b7733 | 212 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| 3325cbe8 | 213 | clocks = <&mstp0_clks R8A7779_CLK_I2C3>; |
| 751e29bb | 214 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| eda3a4fa | 215 | status = "disabled"; |
| 10e8d4f6 | 216 | }; |
| 25a65975 | 217 | |
| fd953b89 | 218 | scif0: serial@ffe40000 { |
| b2ac44fa GU |
219 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
| 220 | "renesas,scif"; | |
| fd953b89 | 221 | reg = <0xffe40000 0x100>; |
| 854b7733 | 222 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
| f2be5f00 GU |
223 | clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, |
| 224 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
| 225 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 751e29bb | 226 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| fd953b89 SH |
227 | status = "disabled"; |
| 228 | }; | |
| 229 | ||
| 230 | scif1: serial@ffe41000 { | |
| b2ac44fa GU |
231 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
| 232 | "renesas,scif"; | |
| fd953b89 | 233 | reg = <0xffe41000 0x100>; |
| 854b7733 | 234 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| f2be5f00 GU |
235 | clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, |
| 236 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
| 237 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 751e29bb | 238 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| fd953b89 SH |
239 | status = "disabled"; |
| 240 | }; | |
| 241 | ||
| 242 | scif2: serial@ffe42000 { | |
| b2ac44fa GU |
243 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
| 244 | "renesas,scif"; | |
| fd953b89 | 245 | reg = <0xffe42000 0x100>; |
| 854b7733 | 246 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| f2be5f00 GU |
247 | clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, |
| 248 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
| 249 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 751e29bb | 250 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| fd953b89 SH |
251 | status = "disabled"; |
| 252 | }; | |
| 253 | ||
| 254 | scif3: serial@ffe43000 { | |
| b2ac44fa GU |
255 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
| 256 | "renesas,scif"; | |
| fd953b89 | 257 | reg = <0xffe43000 0x100>; |
| 854b7733 | 258 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| f2be5f00 GU |
259 | clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, |
| 260 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
| 261 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 751e29bb | 262 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| fd953b89 SH |
263 | status = "disabled"; |
| 264 | }; | |
| 265 | ||
| 266 | scif4: serial@ffe44000 { | |
| b2ac44fa GU |
267 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
| 268 | "renesas,scif"; | |
| fd953b89 | 269 | reg = <0xffe44000 0x100>; |
| 854b7733 | 270 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| f2be5f00 GU |
271 | clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, |
| 272 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
| 273 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 751e29bb | 274 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| fd953b89 SH |
275 | status = "disabled"; |
| 276 | }; | |
| 277 | ||
| 278 | scif5: serial@ffe45000 { | |
| b2ac44fa GU |
279 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
| 280 | "renesas,scif"; | |
| fd953b89 | 281 | reg = <0xffe45000 0x100>; |
| 854b7733 | 282 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| f2be5f00 GU |
283 | clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, |
| 284 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
| 285 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 751e29bb | 286 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| fd953b89 SH |
287 | status = "disabled"; |
| 288 | }; | |
| 289 | ||
| 055d15a8 UH |
290 | hscif0: serial@ffe48000 { |
| 291 | compatible = "renesas,hscif-r8a7779", | |
| 292 | "renesas,rcar-gen1-hscif", "renesas,hscif"; | |
| 293 | reg = <0xffe48000 96>; | |
| 294 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
| 295 | clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>, | |
| 296 | <&cpg_clocks R8A7779_CLK_S>, | |
| 297 | <&scif_clk>; | |
| 298 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 299 | power-domains = <&cpg_clocks>; | |
| 300 | status = "disabled"; | |
| 301 | }; | |
| 302 | ||
| 303 | hscif1: serial@ffe49000 { | |
| 304 | compatible = "renesas,hscif-r8a7779", | |
| 305 | "renesas,rcar-gen1-hscif", "renesas,hscif"; | |
| 306 | reg = <0xffe49000 96>; | |
| 307 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
| 308 | clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>, | |
| 309 | <&cpg_clocks R8A7779_CLK_S>, | |
| 310 | <&scif_clk>; | |
| 311 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 312 | power-domains = <&cpg_clocks>; | |
| 313 | status = "disabled"; | |
| 314 | }; | |
| 315 | ||
| b07b763c | 316 | pfc: pin-controller@fffc0000 { |
| 3ab03d01 LP |
317 | compatible = "renesas,pfc-r8a7779"; |
| 318 | reg = <0xfffc0000 0x23c>; | |
| 319 | }; | |
| 320 | ||
| 25a65975 | 321 | thermal@ffc48000 { |
| 4d50e6dd | 322 | compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; |
| 25a65975 KM |
323 | reg = <0xffc48000 0x38>; |
| 324 | }; | |
| 7840a65a | 325 | |
| ef890ea2 | 326 | tmu0: timer@ffd80000 { |
| a51b7b38 | 327 | compatible = "renesas,tmu-r8a7779", "renesas,tmu"; |
| ef890ea2 | 328 | reg = <0xffd80000 0x30>; |
| 854b7733 SH |
329 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 330 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
| 331 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
| ef890ea2 LP |
332 | clocks = <&mstp0_clks R8A7779_CLK_TMU0>; |
| 333 | clock-names = "fck"; | |
| 751e29bb | 334 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| ef890ea2 LP |
335 | |
| 336 | #renesas,channels = <3>; | |
| 337 | ||
| 338 | status = "disabled"; | |
| 339 | }; | |
| 340 | ||
| 341 | tmu1: timer@ffd81000 { | |
| a51b7b38 | 342 | compatible = "renesas,tmu-r8a7779", "renesas,tmu"; |
| ef890ea2 | 343 | reg = <0xffd81000 0x30>; |
| 854b7733 SH |
344 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, |
| 345 | <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, | |
| 346 | <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
| ef890ea2 LP |
347 | clocks = <&mstp0_clks R8A7779_CLK_TMU1>; |
| 348 | clock-names = "fck"; | |
| 751e29bb | 349 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| ef890ea2 LP |
350 | |
| 351 | #renesas,channels = <3>; | |
| 352 | ||
| 353 | status = "disabled"; | |
| 354 | }; | |
| 355 | ||
| 356 | tmu2: timer@ffd82000 { | |
| a51b7b38 | 357 | compatible = "renesas,tmu-r8a7779", "renesas,tmu"; |
| ef890ea2 | 358 | reg = <0xffd82000 0x30>; |
| 854b7733 SH |
359 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| 360 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
| 361 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
| ef890ea2 LP |
362 | clocks = <&mstp0_clks R8A7779_CLK_TMU2>; |
| 363 | clock-names = "fck"; | |
| 751e29bb | 364 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| ef890ea2 LP |
365 | |
| 366 | #renesas,channels = <3>; | |
| 367 | ||
| 368 | status = "disabled"; | |
| 369 | }; | |
| 370 | ||
| 7840a65a | 371 | sata: sata@fc600000 { |
| 25af9c83 | 372 | compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; |
| 441f61e3 | 373 | reg = <0xfc600000 0x200000>; |
| 854b7733 | 374 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 3325cbe8 | 375 | clocks = <&mstp1_clks R8A7779_CLK_SATA>; |
| 751e29bb | 376 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| e8aa6811 | 377 | status = "disabled"; |
| 7840a65a | 378 | }; |
| c4866e70 | 379 | |
| 2624705c | 380 | sdhi0: sd@ffe4c000 { |
| 0863a6ef SH |
381 | compatible = "renesas,sdhi-r8a7779", |
| 382 | "renesas,rcar-gen1-sdhi"; | |
| c4866e70 | 383 | reg = <0xffe4c000 0x100>; |
| 854b7733 | 384 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
| 3325cbe8 | 385 | clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; |
| 751e29bb | 386 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| c4866e70 KM |
387 | status = "disabled"; |
| 388 | }; | |
| 389 | ||
| 2624705c | 390 | sdhi1: sd@ffe4d000 { |
| 0863a6ef SH |
391 | compatible = "renesas,sdhi-r8a7779", |
| 392 | "renesas,rcar-gen1-sdhi"; | |
| c4866e70 | 393 | reg = <0xffe4d000 0x100>; |
| 854b7733 | 394 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| 3325cbe8 | 395 | clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; |
| 751e29bb | 396 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| c4866e70 KM |
397 | status = "disabled"; |
| 398 | }; | |
| 399 | ||
| 2624705c | 400 | sdhi2: sd@ffe4e000 { |
| 0863a6ef SH |
401 | compatible = "renesas,sdhi-r8a7779", |
| 402 | "renesas,rcar-gen1-sdhi"; | |
| c4866e70 | 403 | reg = <0xffe4e000 0x100>; |
| 854b7733 | 404 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| 3325cbe8 | 405 | clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; |
| 751e29bb | 406 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| c4866e70 KM |
407 | status = "disabled"; |
| 408 | }; | |
| 409 | ||
| 2624705c | 410 | sdhi3: sd@ffe4f000 { |
| 0863a6ef SH |
411 | compatible = "renesas,sdhi-r8a7779", |
| 412 | "renesas,rcar-gen1-sdhi"; | |
| c4866e70 | 413 | reg = <0xffe4f000 0x100>; |
| 854b7733 | 414 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| 3325cbe8 | 415 | clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; |
| 751e29bb | 416 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| c4866e70 KM |
417 | status = "disabled"; |
| 418 | }; | |
| 3c3f6ad3 SH |
419 | |
| 420 | hspi0: spi@fffc7000 { | |
| 7709c33b | 421 | compatible = "renesas,hspi-r8a7779", "renesas,hspi"; |
| 3c3f6ad3 | 422 | reg = <0xfffc7000 0x18>; |
| 854b7733 | 423 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 7709c33b GU |
424 | #address-cells = <1>; |
| 425 | #size-cells = <0>; | |
| 3325cbe8 | 426 | clocks = <&mstp0_clks R8A7779_CLK_HSPI>; |
| 751e29bb | 427 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| 3c3f6ad3 SH |
428 | status = "disabled"; |
| 429 | }; | |
| 430 | ||
| 431 | hspi1: spi@fffc8000 { | |
| 7709c33b | 432 | compatible = "renesas,hspi-r8a7779", "renesas,hspi"; |
| 3c3f6ad3 | 433 | reg = <0xfffc8000 0x18>; |
| 854b7733 | 434 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 7709c33b GU |
435 | #address-cells = <1>; |
| 436 | #size-cells = <0>; | |
| 3325cbe8 | 437 | clocks = <&mstp0_clks R8A7779_CLK_HSPI>; |
| 751e29bb | 438 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| 3c3f6ad3 SH |
439 | status = "disabled"; |
| 440 | }; | |
| 441 | ||
| 442 | hspi2: spi@fffc6000 { | |
| 7709c33b | 443 | compatible = "renesas,hspi-r8a7779", "renesas,hspi"; |
| 3c3f6ad3 | 444 | reg = <0xfffc6000 0x18>; |
| 854b7733 | 445 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 7709c33b GU |
446 | #address-cells = <1>; |
| 447 | #size-cells = <0>; | |
| 3325cbe8 | 448 | clocks = <&mstp0_clks R8A7779_CLK_HSPI>; |
| 751e29bb | 449 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| 3c3f6ad3 SH |
450 | status = "disabled"; |
| 451 | }; | |
| 1e851538 | 452 | |
| 1f08bbe8 LP |
453 | du: display@fff80000 { |
| 454 | compatible = "renesas,du-r8a7779"; | |
| 30524edf | 455 | reg = <0xfff80000 0x40000>; |
| 854b7733 | 456 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 1f08bbe8 | 457 | clocks = <&mstp1_clks R8A7779_CLK_DU>; |
| 751e29bb | 458 | power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; |
| 1f08bbe8 LP |
459 | status = "disabled"; |
| 460 | ||
| 461 | ports { | |
| 462 | #address-cells = <1>; | |
| 463 | #size-cells = <0>; | |
| 464 | ||
| 465 | port@0 { | |
| 466 | reg = <0>; | |
| 467 | du_out_rgb0: endpoint { | |
| 468 | }; | |
| 469 | }; | |
| 470 | port@1 { | |
| 471 | reg = <1>; | |
| 472 | du_out_rgb1: endpoint { | |
| 473 | }; | |
| 474 | }; | |
| 475 | }; | |
| 476 | }; | |
| 477 | ||
| 1e851538 | 478 | clocks { |
| 5cc8afcb GU |
479 | #address-cells = <1>; |
| 480 | #size-cells = <1>; | |
| 1e851538 SH |
481 | ranges; |
| 482 | ||
| 483 | /* External root clock */ | |
| 3f6dba70 | 484 | extal_clk: extal { |
| 1e851538 SH |
485 | compatible = "fixed-clock"; |
| 486 | #clock-cells = <0>; | |
| 487 | /* This value must be overriden by the board. */ | |
| 488 | clock-frequency = <0>; | |
| 1e851538 SH |
489 | }; |
| 490 | ||
| f2be5f00 GU |
491 | /* External SCIF clock */ |
| 492 | scif_clk: scif { | |
| 493 | compatible = "fixed-clock"; | |
| 494 | #clock-cells = <0>; | |
| 495 | /* This value must be overridden by the board. */ | |
| 496 | clock-frequency = <0>; | |
| f2be5f00 GU |
497 | }; |
| 498 | ||
| 1e851538 | 499 | /* Special CPG clocks */ |
| 2909b874 | 500 | cpg_clocks: clocks@ffc80000 { |
| 1e851538 | 501 | compatible = "renesas,r8a7779-cpg-clocks"; |
| 5cc8afcb | 502 | reg = <0xffc80000 0x30>; |
| 1e851538 SH |
503 | clocks = <&extal_clk>; |
| 504 | #clock-cells = <1>; | |
| 505 | clock-output-names = "plla", "z", "zs", "s", | |
| 506 | "s1", "p", "b", "out"; | |
| 33c3632a | 507 | #power-domain-cells = <0>; |
| 1e851538 SH |
508 | }; |
| 509 | ||
| 510 | /* Fixed factor clocks */ | |
| 3f6dba70 | 511 | i_clk: i { |
| 1e851538 SH |
512 | compatible = "fixed-factor-clock"; |
| 513 | clocks = <&cpg_clocks R8A7779_CLK_PLLA>; | |
| 514 | #clock-cells = <0>; | |
| 515 | clock-div = <2>; | |
| 516 | clock-mult = <1>; | |
| 1e851538 | 517 | }; |
| 3f6dba70 | 518 | s3_clk: s3 { |
| 1e851538 SH |
519 | compatible = "fixed-factor-clock"; |
| 520 | clocks = <&cpg_clocks R8A7779_CLK_PLLA>; | |
| 521 | #clock-cells = <0>; | |
| 522 | clock-div = <8>; | |
| 523 | clock-mult = <1>; | |
| 1e851538 | 524 | }; |
| 3f6dba70 | 525 | s4_clk: s4 { |
| 1e851538 SH |
526 | compatible = "fixed-factor-clock"; |
| 527 | clocks = <&cpg_clocks R8A7779_CLK_PLLA>; | |
| 528 | #clock-cells = <0>; | |
| 529 | clock-div = <16>; | |
| 530 | clock-mult = <1>; | |
| 1e851538 | 531 | }; |
| 3f6dba70 | 532 | g_clk: g { |
| 1e851538 SH |
533 | compatible = "fixed-factor-clock"; |
| 534 | clocks = <&cpg_clocks R8A7779_CLK_PLLA>; | |
| 535 | #clock-cells = <0>; | |
| 536 | clock-div = <24>; | |
| 537 | clock-mult = <1>; | |
| 1e851538 SH |
538 | }; |
| 539 | ||
| 540 | /* Gate clocks */ | |
| 2909b874 | 541 | mstp0_clks: clocks@ffc80030 { |
| 1e851538 | 542 | compatible = "renesas,r8a7779-mstp-clocks", |
| 99e544c7 | 543 | "renesas,cpg-mstp-clocks"; |
| 5cc8afcb | 544 | reg = <0xffc80030 4>; |
| 1e851538 | 545 | clocks = <&cpg_clocks R8A7779_CLK_S>, |
| 99e544c7 | 546 | <&cpg_clocks R8A7779_CLK_P>, |
| 1e851538 SH |
547 | <&cpg_clocks R8A7779_CLK_P>, |
| 548 | <&cpg_clocks R8A7779_CLK_P>, | |
| 549 | <&cpg_clocks R8A7779_CLK_S>, | |
| 550 | <&cpg_clocks R8A7779_CLK_S>, | |
| c6ce3cdf MD |
551 | <&cpg_clocks R8A7779_CLK_P>, |
| 552 | <&cpg_clocks R8A7779_CLK_P>, | |
| 553 | <&cpg_clocks R8A7779_CLK_P>, | |
| 554 | <&cpg_clocks R8A7779_CLK_P>, | |
| 555 | <&cpg_clocks R8A7779_CLK_P>, | |
| 556 | <&cpg_clocks R8A7779_CLK_P>, | |
| 1e851538 SH |
557 | <&cpg_clocks R8A7779_CLK_P>, |
| 558 | <&cpg_clocks R8A7779_CLK_P>, | |
| 559 | <&cpg_clocks R8A7779_CLK_P>, | |
| 560 | <&cpg_clocks R8A7779_CLK_P>; | |
| 561 | #clock-cells = <1>; | |
| 64530fc2 | 562 | clock-indices = < |
| 1e851538 SH |
563 | R8A7779_CLK_HSPI R8A7779_CLK_TMU2 |
| 564 | R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 | |
| 565 | R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 | |
| 566 | R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4 | |
| 567 | R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 | |
| 568 | R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0 | |
| 569 | R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 | |
| 570 | R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 | |
| 571 | >; | |
| 572 | clock-output-names = | |
| 573 | "hspi", "tmu2", "tmu1", "tmu0", "hscif1", | |
| 574 | "hscif0", "scif5", "scif4", "scif3", "scif2", | |
| 575 | "scif1", "scif0", "i2c3", "i2c2", "i2c1", | |
| 576 | "i2c0"; | |
| 577 | }; | |
| 2909b874 | 578 | mstp1_clks: clocks@ffc80034 { |
| 1e851538 | 579 | compatible = "renesas,r8a7779-mstp-clocks", |
| 99e544c7 | 580 | "renesas,cpg-mstp-clocks"; |
| 5cc8afcb | 581 | reg = <0xffc80034 4>, <0xffc80044 4>; |
| 1e851538 SH |
582 | clocks = <&cpg_clocks R8A7779_CLK_P>, |
| 583 | <&cpg_clocks R8A7779_CLK_P>, | |
| 584 | <&cpg_clocks R8A7779_CLK_S>, | |
| 585 | <&cpg_clocks R8A7779_CLK_S>, | |
| 586 | <&cpg_clocks R8A7779_CLK_S>, | |
| 587 | <&cpg_clocks R8A7779_CLK_S>, | |
| 588 | <&cpg_clocks R8A7779_CLK_P>, | |
| 589 | <&cpg_clocks R8A7779_CLK_P>, | |
| 590 | <&cpg_clocks R8A7779_CLK_P>, | |
| 591 | <&cpg_clocks R8A7779_CLK_S>; | |
| 592 | #clock-cells = <1>; | |
| 64530fc2 | 593 | clock-indices = < |
| 1e851538 SH |
594 | R8A7779_CLK_USB01 R8A7779_CLK_USB2 |
| 595 | R8A7779_CLK_DU R8A7779_CLK_VIN2 | |
| 596 | R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 | |
| 597 | R8A7779_CLK_ETHER R8A7779_CLK_SATA | |
| 598 | R8A7779_CLK_PCIE R8A7779_CLK_VIN3 | |
| 599 | >; | |
| 600 | clock-output-names = | |
| 601 | "usb01", "usb2", | |
| 602 | "du", "vin2", | |
| 603 | "vin1", "vin0", | |
| 604 | "ether", "sata", | |
| 605 | "pcie", "vin3"; | |
| 606 | }; | |
| 2909b874 | 607 | mstp3_clks: clocks@ffc8003c { |
| 1e851538 | 608 | compatible = "renesas,r8a7779-mstp-clocks", |
| 99e544c7 | 609 | "renesas,cpg-mstp-clocks"; |
| 5cc8afcb | 610 | reg = <0xffc8003c 4>; |
| 1e851538 SH |
611 | clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, |
| 612 | <&s4_clk>, <&s4_clk>; | |
| 613 | #clock-cells = <1>; | |
| 64530fc2 | 614 | clock-indices = < |
| 1e851538 SH |
615 | R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 |
| 616 | R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 | |
| 617 | R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 | |
| 618 | >; | |
| 619 | clock-output-names = | |
| 620 | "sdhi3", "sdhi2", "sdhi1", "sdhi0", | |
| 621 | "mmc1", "mmc0"; | |
| 622 | }; | |
| 623 | }; | |
| b2df3aa4 | 624 | |
| 9ba368e2 GU |
625 | prr: chipid@ff000044 { |
| 626 | compatible = "renesas,prr"; | |
| 627 | reg = <0xff000044 4>; | |
| 628 | }; | |
| 629 | ||
| ad40150a GU |
630 | rst: reset-controller@ffcc0000 { |
| 631 | compatible = "renesas,r8a7779-reset-wdt"; | |
| 632 | reg = <0xffcc0000 0x48>; | |
| 633 | }; | |
| 634 | ||
| b2df3aa4 GU |
635 | sysc: system-controller@ffd85000 { |
| 636 | compatible = "renesas,r8a7779-sysc"; | |
| 637 | reg = <0xffd85000 0x0200>; | |
| 638 | #power-domain-cells = <1>; | |
| 639 | }; | |
| c58a1545 | 640 | }; |