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Commit | Line | Data |
---|---|---|
c58a1545 | 1 | /* |
349f556e | 2 | * Device Tree Source for Renesas r8a7779 |
c58a1545 SH |
3 | * |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * Copyright (C) 2013 Simon Horman | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | /include/ "skeleton.dtsi" | |
13 | ||
1e851538 | 14 | #include <dt-bindings/clock/r8a7779-clock.h> |
cea80654 | 15 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
5f75e73c LP |
16 | #include <dt-bindings/interrupt-controller/irq.h> |
17 | ||
c58a1545 SH |
18 | / { |
19 | compatible = "renesas,r8a7779"; | |
9ff254ad | 20 | interrupt-parent = <&gic>; |
c58a1545 SH |
21 | |
22 | cpus { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <0>; | |
25 | ||
26 | cpu@0 { | |
27 | device_type = "cpu"; | |
28 | compatible = "arm,cortex-a9"; | |
29 | reg = <0>; | |
6b060f93 | 30 | clock-frequency = <1000000000>; |
c58a1545 SH |
31 | }; |
32 | cpu@1 { | |
33 | device_type = "cpu"; | |
34 | compatible = "arm,cortex-a9"; | |
35 | reg = <1>; | |
6b060f93 | 36 | clock-frequency = <1000000000>; |
c58a1545 SH |
37 | }; |
38 | cpu@2 { | |
39 | device_type = "cpu"; | |
40 | compatible = "arm,cortex-a9"; | |
41 | reg = <2>; | |
6b060f93 | 42 | clock-frequency = <1000000000>; |
c58a1545 SH |
43 | }; |
44 | cpu@3 { | |
45 | device_type = "cpu"; | |
46 | compatible = "arm,cortex-a9"; | |
47 | reg = <3>; | |
6b060f93 | 48 | clock-frequency = <1000000000>; |
c58a1545 SH |
49 | }; |
50 | }; | |
51 | ||
3c3f6ad3 SH |
52 | aliases { |
53 | spi0 = &hspi0; | |
54 | spi1 = &hspi1; | |
55 | spi2 = &hspi2; | |
56 | }; | |
57 | ||
cc703a59 SH |
58 | gic: interrupt-controller@f0001000 { |
59 | compatible = "arm,cortex-a9-gic"; | |
60 | #interrupt-cells = <3>; | |
61 | interrupt-controller; | |
62 | reg = <0xf0001000 0x1000>, | |
63 | <0xf0000100 0x100>; | |
64 | }; | |
10e8d4f6 | 65 | |
cea80654 MD |
66 | timer@f0000600 { |
67 | compatible = "arm,cortex-a9-twd-timer"; | |
68 | reg = <0xf0000600 0x20>; | |
69 | interrupts = <GIC_PPI 13 | |
70 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
71 | clocks = <&cpg_clocks R8A7779_CLK_ZS>; | |
72 | }; | |
73 | ||
f5c771b5 LP |
74 | gpio0: gpio@ffc40000 { |
75 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | |
76 | reg = <0xffc40000 0x2c>; | |
854b7733 | 77 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
f5c771b5 LP |
78 | #gpio-cells = <2>; |
79 | gpio-controller; | |
80 | gpio-ranges = <&pfc 0 0 32>; | |
81 | #interrupt-cells = <2>; | |
82 | interrupt-controller; | |
83 | }; | |
84 | ||
85 | gpio1: gpio@ffc41000 { | |
86 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | |
87 | reg = <0xffc41000 0x2c>; | |
854b7733 | 88 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
f5c771b5 LP |
89 | #gpio-cells = <2>; |
90 | gpio-controller; | |
91 | gpio-ranges = <&pfc 0 32 32>; | |
92 | #interrupt-cells = <2>; | |
93 | interrupt-controller; | |
94 | }; | |
95 | ||
96 | gpio2: gpio@ffc42000 { | |
97 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | |
98 | reg = <0xffc42000 0x2c>; | |
854b7733 | 99 | interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
f5c771b5 LP |
100 | #gpio-cells = <2>; |
101 | gpio-controller; | |
102 | gpio-ranges = <&pfc 0 64 32>; | |
103 | #interrupt-cells = <2>; | |
104 | interrupt-controller; | |
105 | }; | |
106 | ||
107 | gpio3: gpio@ffc43000 { | |
108 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | |
109 | reg = <0xffc43000 0x2c>; | |
854b7733 | 110 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
f5c771b5 LP |
111 | #gpio-cells = <2>; |
112 | gpio-controller; | |
113 | gpio-ranges = <&pfc 0 96 32>; | |
114 | #interrupt-cells = <2>; | |
115 | interrupt-controller; | |
116 | }; | |
117 | ||
118 | gpio4: gpio@ffc44000 { | |
119 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | |
120 | reg = <0xffc44000 0x2c>; | |
854b7733 | 121 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
f5c771b5 LP |
122 | #gpio-cells = <2>; |
123 | gpio-controller; | |
124 | gpio-ranges = <&pfc 0 128 32>; | |
125 | #interrupt-cells = <2>; | |
126 | interrupt-controller; | |
127 | }; | |
128 | ||
129 | gpio5: gpio@ffc45000 { | |
130 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | |
131 | reg = <0xffc45000 0x2c>; | |
854b7733 | 132 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
f5c771b5 LP |
133 | #gpio-cells = <2>; |
134 | gpio-controller; | |
135 | gpio-ranges = <&pfc 0 160 32>; | |
136 | #interrupt-cells = <2>; | |
137 | interrupt-controller; | |
138 | }; | |
139 | ||
140 | gpio6: gpio@ffc46000 { | |
141 | compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; | |
142 | reg = <0xffc46000 0x2c>; | |
854b7733 | 143 | interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; |
f5c771b5 LP |
144 | #gpio-cells = <2>; |
145 | gpio-controller; | |
146 | gpio-ranges = <&pfc 0 192 9>; | |
147 | #interrupt-cells = <2>; | |
148 | interrupt-controller; | |
149 | }; | |
150 | ||
7bf46d0b | 151 | irqpin0: interrupt-controller@fe78001c { |
11ef0340 | 152 | compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; |
24603f3c | 153 | #interrupt-cells = <2>; |
84b47dfc | 154 | status = "disabled"; |
24603f3c GL |
155 | interrupt-controller; |
156 | reg = <0xfe78001c 4>, | |
157 | <0xfe780010 4>, | |
158 | <0xfe780024 4>, | |
159 | <0xfe780044 4>, | |
7bf46d0b MD |
160 | <0xfe780064 4>, |
161 | <0xfe780000 4>; | |
854b7733 SH |
162 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH |
163 | GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH | |
164 | GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH | |
165 | GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
24603f3c GL |
166 | sense-bitfield-width = <2>; |
167 | }; | |
168 | ||
98724b7e | 169 | i2c0: i2c@ffc70000 { |
10e8d4f6 SH |
170 | #address-cells = <1>; |
171 | #size-cells = <0>; | |
6363070e | 172 | compatible = "renesas,i2c-r8a7779"; |
10e8d4f6 | 173 | reg = <0xffc70000 0x1000>; |
854b7733 | 174 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
3325cbe8 | 175 | clocks = <&mstp0_clks R8A7779_CLK_I2C0>; |
33c3632a | 176 | power-domains = <&cpg_clocks>; |
eda3a4fa | 177 | status = "disabled"; |
10e8d4f6 SH |
178 | }; |
179 | ||
98724b7e | 180 | i2c1: i2c@ffc71000 { |
10e8d4f6 SH |
181 | #address-cells = <1>; |
182 | #size-cells = <0>; | |
6363070e | 183 | compatible = "renesas,i2c-r8a7779"; |
10e8d4f6 | 184 | reg = <0xffc71000 0x1000>; |
854b7733 | 185 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
3325cbe8 | 186 | clocks = <&mstp0_clks R8A7779_CLK_I2C1>; |
33c3632a | 187 | power-domains = <&cpg_clocks>; |
eda3a4fa | 188 | status = "disabled"; |
10e8d4f6 SH |
189 | }; |
190 | ||
98724b7e | 191 | i2c2: i2c@ffc72000 { |
10e8d4f6 SH |
192 | #address-cells = <1>; |
193 | #size-cells = <0>; | |
6363070e | 194 | compatible = "renesas,i2c-r8a7779"; |
10e8d4f6 | 195 | reg = <0xffc72000 0x1000>; |
854b7733 | 196 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
3325cbe8 | 197 | clocks = <&mstp0_clks R8A7779_CLK_I2C2>; |
33c3632a | 198 | power-domains = <&cpg_clocks>; |
eda3a4fa | 199 | status = "disabled"; |
10e8d4f6 SH |
200 | }; |
201 | ||
98724b7e | 202 | i2c3: i2c@ffc73000 { |
10e8d4f6 SH |
203 | #address-cells = <1>; |
204 | #size-cells = <0>; | |
6363070e | 205 | compatible = "renesas,i2c-r8a7779"; |
10e8d4f6 | 206 | reg = <0xffc73000 0x1000>; |
854b7733 | 207 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
3325cbe8 | 208 | clocks = <&mstp0_clks R8A7779_CLK_I2C3>; |
33c3632a | 209 | power-domains = <&cpg_clocks>; |
eda3a4fa | 210 | status = "disabled"; |
10e8d4f6 | 211 | }; |
25a65975 | 212 | |
fd953b89 | 213 | scif0: serial@ffe40000 { |
b2ac44fa GU |
214 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
215 | "renesas,scif"; | |
fd953b89 | 216 | reg = <0xffe40000 0x100>; |
854b7733 | 217 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
f2be5f00 GU |
218 | clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, |
219 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
220 | clock-names = "fck", "brg_int", "scif_clk"; | |
33c3632a | 221 | power-domains = <&cpg_clocks>; |
fd953b89 SH |
222 | status = "disabled"; |
223 | }; | |
224 | ||
225 | scif1: serial@ffe41000 { | |
b2ac44fa GU |
226 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
227 | "renesas,scif"; | |
fd953b89 | 228 | reg = <0xffe41000 0x100>; |
854b7733 | 229 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
f2be5f00 GU |
230 | clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, |
231 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
232 | clock-names = "fck", "brg_int", "scif_clk"; | |
33c3632a | 233 | power-domains = <&cpg_clocks>; |
fd953b89 SH |
234 | status = "disabled"; |
235 | }; | |
236 | ||
237 | scif2: serial@ffe42000 { | |
b2ac44fa GU |
238 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
239 | "renesas,scif"; | |
fd953b89 | 240 | reg = <0xffe42000 0x100>; |
854b7733 | 241 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
f2be5f00 GU |
242 | clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, |
243 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
244 | clock-names = "fck", "brg_int", "scif_clk"; | |
33c3632a | 245 | power-domains = <&cpg_clocks>; |
fd953b89 SH |
246 | status = "disabled"; |
247 | }; | |
248 | ||
249 | scif3: serial@ffe43000 { | |
b2ac44fa GU |
250 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
251 | "renesas,scif"; | |
fd953b89 | 252 | reg = <0xffe43000 0x100>; |
854b7733 | 253 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
f2be5f00 GU |
254 | clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, |
255 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
256 | clock-names = "fck", "brg_int", "scif_clk"; | |
33c3632a | 257 | power-domains = <&cpg_clocks>; |
fd953b89 SH |
258 | status = "disabled"; |
259 | }; | |
260 | ||
261 | scif4: serial@ffe44000 { | |
b2ac44fa GU |
262 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
263 | "renesas,scif"; | |
fd953b89 | 264 | reg = <0xffe44000 0x100>; |
854b7733 | 265 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
f2be5f00 GU |
266 | clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, |
267 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
268 | clock-names = "fck", "brg_int", "scif_clk"; | |
33c3632a | 269 | power-domains = <&cpg_clocks>; |
fd953b89 SH |
270 | status = "disabled"; |
271 | }; | |
272 | ||
273 | scif5: serial@ffe45000 { | |
b2ac44fa GU |
274 | compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", |
275 | "renesas,scif"; | |
fd953b89 | 276 | reg = <0xffe45000 0x100>; |
854b7733 | 277 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
f2be5f00 GU |
278 | clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, |
279 | <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; | |
280 | clock-names = "fck", "brg_int", "scif_clk"; | |
33c3632a | 281 | power-domains = <&cpg_clocks>; |
fd953b89 SH |
282 | status = "disabled"; |
283 | }; | |
284 | ||
3ab03d01 LP |
285 | pfc: pfc@fffc0000 { |
286 | compatible = "renesas,pfc-r8a7779"; | |
287 | reg = <0xfffc0000 0x23c>; | |
288 | }; | |
289 | ||
25a65975 | 290 | thermal@ffc48000 { |
4d50e6dd | 291 | compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; |
25a65975 KM |
292 | reg = <0xffc48000 0x38>; |
293 | }; | |
7840a65a | 294 | |
ef890ea2 | 295 | tmu0: timer@ffd80000 { |
a51b7b38 | 296 | compatible = "renesas,tmu-r8a7779", "renesas,tmu"; |
ef890ea2 | 297 | reg = <0xffd80000 0x30>; |
854b7733 SH |
298 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
299 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
300 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
ef890ea2 LP |
301 | clocks = <&mstp0_clks R8A7779_CLK_TMU0>; |
302 | clock-names = "fck"; | |
33c3632a | 303 | power-domains = <&cpg_clocks>; |
ef890ea2 LP |
304 | |
305 | #renesas,channels = <3>; | |
306 | ||
307 | status = "disabled"; | |
308 | }; | |
309 | ||
310 | tmu1: timer@ffd81000 { | |
a51b7b38 | 311 | compatible = "renesas,tmu-r8a7779", "renesas,tmu"; |
ef890ea2 | 312 | reg = <0xffd81000 0x30>; |
854b7733 SH |
313 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, |
314 | <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, | |
315 | <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
ef890ea2 LP |
316 | clocks = <&mstp0_clks R8A7779_CLK_TMU1>; |
317 | clock-names = "fck"; | |
33c3632a | 318 | power-domains = <&cpg_clocks>; |
ef890ea2 LP |
319 | |
320 | #renesas,channels = <3>; | |
321 | ||
322 | status = "disabled"; | |
323 | }; | |
324 | ||
325 | tmu2: timer@ffd82000 { | |
a51b7b38 | 326 | compatible = "renesas,tmu-r8a7779", "renesas,tmu"; |
ef890ea2 | 327 | reg = <0xffd82000 0x30>; |
854b7733 SH |
328 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
329 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
330 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
ef890ea2 LP |
331 | clocks = <&mstp0_clks R8A7779_CLK_TMU2>; |
332 | clock-names = "fck"; | |
33c3632a | 333 | power-domains = <&cpg_clocks>; |
ef890ea2 LP |
334 | |
335 | #renesas,channels = <3>; | |
336 | ||
337 | status = "disabled"; | |
338 | }; | |
339 | ||
7840a65a | 340 | sata: sata@fc600000 { |
25af9c83 | 341 | compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; |
7840a65a | 342 | reg = <0xfc600000 0x2000>; |
854b7733 | 343 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
3325cbe8 | 344 | clocks = <&mstp1_clks R8A7779_CLK_SATA>; |
33c3632a | 345 | power-domains = <&cpg_clocks>; |
7840a65a | 346 | }; |
c4866e70 | 347 | |
2624705c | 348 | sdhi0: sd@ffe4c000 { |
c4866e70 KM |
349 | compatible = "renesas,sdhi-r8a7779"; |
350 | reg = <0xffe4c000 0x100>; | |
854b7733 | 351 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
3325cbe8 | 352 | clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; |
33c3632a | 353 | power-domains = <&cpg_clocks>; |
c4866e70 KM |
354 | status = "disabled"; |
355 | }; | |
356 | ||
2624705c | 357 | sdhi1: sd@ffe4d000 { |
c4866e70 KM |
358 | compatible = "renesas,sdhi-r8a7779"; |
359 | reg = <0xffe4d000 0x100>; | |
854b7733 | 360 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
3325cbe8 | 361 | clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; |
33c3632a | 362 | power-domains = <&cpg_clocks>; |
c4866e70 KM |
363 | status = "disabled"; |
364 | }; | |
365 | ||
2624705c | 366 | sdhi2: sd@ffe4e000 { |
c4866e70 KM |
367 | compatible = "renesas,sdhi-r8a7779"; |
368 | reg = <0xffe4e000 0x100>; | |
854b7733 | 369 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
3325cbe8 | 370 | clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; |
33c3632a | 371 | power-domains = <&cpg_clocks>; |
c4866e70 KM |
372 | status = "disabled"; |
373 | }; | |
374 | ||
2624705c | 375 | sdhi3: sd@ffe4f000 { |
c4866e70 KM |
376 | compatible = "renesas,sdhi-r8a7779"; |
377 | reg = <0xffe4f000 0x100>; | |
854b7733 | 378 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
3325cbe8 | 379 | clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; |
33c3632a | 380 | power-domains = <&cpg_clocks>; |
c4866e70 KM |
381 | status = "disabled"; |
382 | }; | |
3c3f6ad3 SH |
383 | |
384 | hspi0: spi@fffc7000 { | |
7709c33b | 385 | compatible = "renesas,hspi-r8a7779", "renesas,hspi"; |
3c3f6ad3 | 386 | reg = <0xfffc7000 0x18>; |
854b7733 | 387 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
7709c33b GU |
388 | #address-cells = <1>; |
389 | #size-cells = <0>; | |
3325cbe8 | 390 | clocks = <&mstp0_clks R8A7779_CLK_HSPI>; |
33c3632a | 391 | power-domains = <&cpg_clocks>; |
3c3f6ad3 SH |
392 | status = "disabled"; |
393 | }; | |
394 | ||
395 | hspi1: spi@fffc8000 { | |
7709c33b | 396 | compatible = "renesas,hspi-r8a7779", "renesas,hspi"; |
3c3f6ad3 | 397 | reg = <0xfffc8000 0x18>; |
854b7733 | 398 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
7709c33b GU |
399 | #address-cells = <1>; |
400 | #size-cells = <0>; | |
3325cbe8 | 401 | clocks = <&mstp0_clks R8A7779_CLK_HSPI>; |
33c3632a | 402 | power-domains = <&cpg_clocks>; |
3c3f6ad3 SH |
403 | status = "disabled"; |
404 | }; | |
405 | ||
406 | hspi2: spi@fffc6000 { | |
7709c33b | 407 | compatible = "renesas,hspi-r8a7779", "renesas,hspi"; |
3c3f6ad3 | 408 | reg = <0xfffc6000 0x18>; |
854b7733 | 409 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
7709c33b GU |
410 | #address-cells = <1>; |
411 | #size-cells = <0>; | |
3325cbe8 | 412 | clocks = <&mstp0_clks R8A7779_CLK_HSPI>; |
33c3632a | 413 | power-domains = <&cpg_clocks>; |
3c3f6ad3 SH |
414 | status = "disabled"; |
415 | }; | |
1e851538 | 416 | |
1f08bbe8 LP |
417 | du: display@fff80000 { |
418 | compatible = "renesas,du-r8a7779"; | |
419 | reg = <0 0xfff80000 0 0x40000>; | |
854b7733 | 420 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
1f08bbe8 | 421 | clocks = <&mstp1_clks R8A7779_CLK_DU>; |
33c3632a | 422 | power-domains = <&cpg_clocks>; |
1f08bbe8 LP |
423 | status = "disabled"; |
424 | ||
425 | ports { | |
426 | #address-cells = <1>; | |
427 | #size-cells = <0>; | |
428 | ||
429 | port@0 { | |
430 | reg = <0>; | |
431 | du_out_rgb0: endpoint { | |
432 | }; | |
433 | }; | |
434 | port@1 { | |
435 | reg = <1>; | |
436 | du_out_rgb1: endpoint { | |
437 | }; | |
438 | }; | |
439 | }; | |
440 | }; | |
441 | ||
1e851538 | 442 | clocks { |
5cc8afcb GU |
443 | #address-cells = <1>; |
444 | #size-cells = <1>; | |
1e851538 SH |
445 | ranges; |
446 | ||
447 | /* External root clock */ | |
448 | extal_clk: extal_clk { | |
449 | compatible = "fixed-clock"; | |
450 | #clock-cells = <0>; | |
451 | /* This value must be overriden by the board. */ | |
452 | clock-frequency = <0>; | |
453 | clock-output-names = "extal"; | |
454 | }; | |
455 | ||
f2be5f00 GU |
456 | /* External SCIF clock */ |
457 | scif_clk: scif { | |
458 | compatible = "fixed-clock"; | |
459 | #clock-cells = <0>; | |
460 | /* This value must be overridden by the board. */ | |
461 | clock-frequency = <0>; | |
462 | status = "disabled"; | |
463 | }; | |
464 | ||
1e851538 | 465 | /* Special CPG clocks */ |
2909b874 | 466 | cpg_clocks: clocks@ffc80000 { |
1e851538 | 467 | compatible = "renesas,r8a7779-cpg-clocks"; |
5cc8afcb | 468 | reg = <0xffc80000 0x30>; |
1e851538 SH |
469 | clocks = <&extal_clk>; |
470 | #clock-cells = <1>; | |
471 | clock-output-names = "plla", "z", "zs", "s", | |
472 | "s1", "p", "b", "out"; | |
33c3632a | 473 | #power-domain-cells = <0>; |
1e851538 SH |
474 | }; |
475 | ||
476 | /* Fixed factor clocks */ | |
477 | i_clk: i_clk { | |
478 | compatible = "fixed-factor-clock"; | |
479 | clocks = <&cpg_clocks R8A7779_CLK_PLLA>; | |
480 | #clock-cells = <0>; | |
481 | clock-div = <2>; | |
482 | clock-mult = <1>; | |
483 | clock-output-names = "i"; | |
484 | }; | |
485 | s3_clk: s3_clk { | |
486 | compatible = "fixed-factor-clock"; | |
487 | clocks = <&cpg_clocks R8A7779_CLK_PLLA>; | |
488 | #clock-cells = <0>; | |
489 | clock-div = <8>; | |
490 | clock-mult = <1>; | |
491 | clock-output-names = "s3"; | |
492 | }; | |
493 | s4_clk: s4_clk { | |
494 | compatible = "fixed-factor-clock"; | |
495 | clocks = <&cpg_clocks R8A7779_CLK_PLLA>; | |
496 | #clock-cells = <0>; | |
497 | clock-div = <16>; | |
498 | clock-mult = <1>; | |
499 | clock-output-names = "s4"; | |
500 | }; | |
501 | g_clk: g_clk { | |
502 | compatible = "fixed-factor-clock"; | |
503 | clocks = <&cpg_clocks R8A7779_CLK_PLLA>; | |
504 | #clock-cells = <0>; | |
505 | clock-div = <24>; | |
506 | clock-mult = <1>; | |
507 | clock-output-names = "g"; | |
508 | }; | |
509 | ||
510 | /* Gate clocks */ | |
2909b874 | 511 | mstp0_clks: clocks@ffc80030 { |
1e851538 | 512 | compatible = "renesas,r8a7779-mstp-clocks", |
99e544c7 | 513 | "renesas,cpg-mstp-clocks"; |
5cc8afcb | 514 | reg = <0xffc80030 4>; |
1e851538 | 515 | clocks = <&cpg_clocks R8A7779_CLK_S>, |
99e544c7 | 516 | <&cpg_clocks R8A7779_CLK_P>, |
1e851538 SH |
517 | <&cpg_clocks R8A7779_CLK_P>, |
518 | <&cpg_clocks R8A7779_CLK_P>, | |
519 | <&cpg_clocks R8A7779_CLK_S>, | |
520 | <&cpg_clocks R8A7779_CLK_S>, | |
c6ce3cdf MD |
521 | <&cpg_clocks R8A7779_CLK_P>, |
522 | <&cpg_clocks R8A7779_CLK_P>, | |
523 | <&cpg_clocks R8A7779_CLK_P>, | |
524 | <&cpg_clocks R8A7779_CLK_P>, | |
525 | <&cpg_clocks R8A7779_CLK_P>, | |
526 | <&cpg_clocks R8A7779_CLK_P>, | |
1e851538 SH |
527 | <&cpg_clocks R8A7779_CLK_P>, |
528 | <&cpg_clocks R8A7779_CLK_P>, | |
529 | <&cpg_clocks R8A7779_CLK_P>, | |
530 | <&cpg_clocks R8A7779_CLK_P>; | |
531 | #clock-cells = <1>; | |
64530fc2 | 532 | clock-indices = < |
1e851538 SH |
533 | R8A7779_CLK_HSPI R8A7779_CLK_TMU2 |
534 | R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 | |
535 | R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 | |
536 | R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4 | |
537 | R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 | |
538 | R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0 | |
539 | R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 | |
540 | R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 | |
541 | >; | |
542 | clock-output-names = | |
543 | "hspi", "tmu2", "tmu1", "tmu0", "hscif1", | |
544 | "hscif0", "scif5", "scif4", "scif3", "scif2", | |
545 | "scif1", "scif0", "i2c3", "i2c2", "i2c1", | |
546 | "i2c0"; | |
547 | }; | |
2909b874 | 548 | mstp1_clks: clocks@ffc80034 { |
1e851538 | 549 | compatible = "renesas,r8a7779-mstp-clocks", |
99e544c7 | 550 | "renesas,cpg-mstp-clocks"; |
5cc8afcb | 551 | reg = <0xffc80034 4>, <0xffc80044 4>; |
1e851538 SH |
552 | clocks = <&cpg_clocks R8A7779_CLK_P>, |
553 | <&cpg_clocks R8A7779_CLK_P>, | |
554 | <&cpg_clocks R8A7779_CLK_S>, | |
555 | <&cpg_clocks R8A7779_CLK_S>, | |
556 | <&cpg_clocks R8A7779_CLK_S>, | |
557 | <&cpg_clocks R8A7779_CLK_S>, | |
558 | <&cpg_clocks R8A7779_CLK_P>, | |
559 | <&cpg_clocks R8A7779_CLK_P>, | |
560 | <&cpg_clocks R8A7779_CLK_P>, | |
561 | <&cpg_clocks R8A7779_CLK_S>; | |
562 | #clock-cells = <1>; | |
64530fc2 | 563 | clock-indices = < |
1e851538 SH |
564 | R8A7779_CLK_USB01 R8A7779_CLK_USB2 |
565 | R8A7779_CLK_DU R8A7779_CLK_VIN2 | |
566 | R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 | |
567 | R8A7779_CLK_ETHER R8A7779_CLK_SATA | |
568 | R8A7779_CLK_PCIE R8A7779_CLK_VIN3 | |
569 | >; | |
570 | clock-output-names = | |
571 | "usb01", "usb2", | |
572 | "du", "vin2", | |
573 | "vin1", "vin0", | |
574 | "ether", "sata", | |
575 | "pcie", "vin3"; | |
576 | }; | |
2909b874 | 577 | mstp3_clks: clocks@ffc8003c { |
1e851538 | 578 | compatible = "renesas,r8a7779-mstp-clocks", |
99e544c7 | 579 | "renesas,cpg-mstp-clocks"; |
5cc8afcb | 580 | reg = <0xffc8003c 4>; |
1e851538 SH |
581 | clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, |
582 | <&s4_clk>, <&s4_clk>; | |
583 | #clock-cells = <1>; | |
64530fc2 | 584 | clock-indices = < |
1e851538 SH |
585 | R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 |
586 | R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 | |
587 | R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 | |
588 | >; | |
589 | clock-output-names = | |
590 | "sdhi3", "sdhi2", "sdhi1", "sdhi0", | |
591 | "mmc1", "mmc0"; | |
592 | }; | |
593 | }; | |
c58a1545 | 594 | }; |