[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / r8a7779.dtsi

/*
 * Device Tree Source for Renesas r8a7779
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Simon Horman
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/clock/r8a7779-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/r8a7779-sysc.h>

/ {
	compatible = "renesas,r8a7779";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <1000000000>;
			clocks = <&cpg_clocks R8A7779_CLK_Z>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clock-frequency = <1000000000>;
			clocks = <&cpg_clocks R8A7779_CLK_Z>;
			power-domains = <&sysc R8A7779_PD_ARM1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			clock-frequency = <1000000000>;
			clocks = <&cpg_clocks R8A7779_CLK_Z>;
			power-domains = <&sysc R8A7779_PD_ARM2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			clock-frequency = <1000000000>;
			clocks = <&cpg_clocks R8A7779_CLK_Z>;
			power-domains = <&sysc R8A7779_PD_ARM3>;
		};
	};

	aliases {
		spi0 = &hspi0;
		spi1 = &hspi1;
		spi2 = &hspi2;
	};

	gic: interrupt-controller@f0001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xf0001000 0x1000>,
		      <0xf0000100 0x100>;
	};

	timer@f0000600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0xf0000600 0x20>;
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&cpg_clocks R8A7779_CLK_ZS>;
	};

	gpio0: gpio@ffc40000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc40000 0x2c>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio1: gpio@ffc41000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc41000 0x2c>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio2: gpio@ffc42000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc42000 0x2c>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio3: gpio@ffc43000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc43000 0x2c>;
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio4: gpio@ffc44000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc44000 0x2c>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio5: gpio@ffc45000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc45000 0x2c>;
		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio6: gpio@ffc46000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc46000 0x2c>;
		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 192 9>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	irqpin0: interrupt-controller@fe78001c {
		compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		status = "disabled";
		interrupt-controller;
		reg = <0xfe78001c 4>,
			<0xfe780010 4>,
			<0xfe780024 4>,
			<0xfe780044 4>,
			<0xfe780064 4>,
			<0xfe780000 4>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		sense-bitfield-width = <2>;
	};

	i2c0: i2c@ffc70000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
		reg = <0xffc70000 0x1000>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	i2c1: i2c@ffc71000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
		reg = <0xffc71000 0x1000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	i2c2: i2c@ffc72000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
		reg = <0xffc72000 0x1000>;
		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	i2c3: i2c@ffc73000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
		reg = <0xffc73000 0x1000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif0: serial@ffe40000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe40000 0x100>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif1: serial@ffe41000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe41000 0x100>;
		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif2: serial@ffe42000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe42000 0x100>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif3: serial@ffe43000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe43000 0x100>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif4: serial@ffe44000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe44000 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif5: serial@ffe45000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe45000 0x100>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	pfc: pin-controller@fffc0000 {
		compatible = "renesas,pfc-r8a7779";
		reg = <0xfffc0000 0x23c>;
	};

	thermal@ffc48000 {
		compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
		reg = <0xffc48000 0x38>;
	};

	tmu0: timer@ffd80000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd80000 0x30>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
		clock-names = "fck";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu1: timer@ffd81000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd81000 0x30>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
		clock-names = "fck";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu2: timer@ffd82000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd82000 0x30>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
		clock-names = "fck";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	sata: sata@fc600000 {
		compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
		reg = <0xfc600000 0x200000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	sdhi0: sd@ffe4c000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4c000 0x100>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	sdhi1: sd@ffe4d000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4d000 0x100>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	sdhi2: sd@ffe4e000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4e000 0x100>;
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	sdhi3: sd@ffe4f000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4f000 0x100>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	hspi0: spi@fffc7000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc7000 0x18>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	hspi1: spi@fffc8000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc8000 0x18>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	hspi2: spi@fffc6000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc6000 0x18>;
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	du: display@fff80000 {
		compatible = "renesas,du-r8a7779";
		reg = <0xfff80000 0x40000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7779_CLK_DU>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				du_out_rgb0: endpoint {
				};
			};
			port@1 {
				reg = <1>;
				du_out_rgb1: endpoint {
				};
			};
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* External root clock */
		extal_clk: extal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overriden by the board. */
			clock-frequency = <0>;
		};

		/* External SCIF clock */
		scif_clk: scif {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overridden by the board. */
			clock-frequency = <0>;
		};

		/* Special CPG clocks */
		cpg_clocks: clocks@ffc80000 {
			compatible = "renesas,r8a7779-cpg-clocks";
			reg = <0xffc80000 0x30>;
			clocks = <&extal_clk>;
			#clock-cells = <1>;
			clock-output-names = "plla", "z", "zs", "s",
					     "s1", "p", "b", "out";
			#power-domain-cells = <0>;
		};

		/* Fixed factor clocks */
		i_clk: i {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};
		s3_clk: s3 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
		};
		s4_clk: s4 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <16>;
			clock-mult = <1>;
		};
		g_clk: g {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <24>;
			clock-mult = <1>;
		};

		/* Gate clocks */
		mstp0_clks: clocks@ffc80030 {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc80030 4>;
			clocks = <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_HSPI R8A7779_CLK_TMU2
				R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
				R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
			>;
			clock-output-names =
				"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
				"hscif0", "scif5", "scif4", "scif3", "scif2",
				"scif1", "scif0", "i2c3", "i2c2", "i2c1",
				"i2c0";
		};
		mstp1_clks: clocks@ffc80034 {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc80034 4>, <0xffc80044 4>;
			clocks = <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_USB01 R8A7779_CLK_USB2
				R8A7779_CLK_DU R8A7779_CLK_VIN2
				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
				R8A7779_CLK_ETHER R8A7779_CLK_SATA
				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
			>;
			clock-output-names =
				"usb01", "usb2",
				"du", "vin2",
				"vin1", "vin0",
				"ether", "sata",
				"pcie", "vin3";
		};
		mstp3_clks: clocks@ffc8003c {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc8003c 4>;
			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
				 <&s4_clk>, <&s4_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
			>;
			clock-output-names =
				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
				"mmc1", "mmc0";
		};
	};

	prr: chipid@ff000044 {
		compatible = "renesas,prr";
		reg = <0xff000044 4>;
	};

	rst: reset-controller@ffcc0000 {
		compatible = "renesas,r8a7779-reset-wdt";
		reg = <0xffcc0000 0x48>;
	};

	sysc: system-controller@ffd85000 {
		compatible = "renesas,r8a7779-sysc";
		reg = <0xffd85000 0x0200>;
		#power-domain-cells = <1>;
	};
};
Commit	Line	Data
c58a1545	1	/*
349f556e	2	* Device Tree Source for Renesas r8a7779
c58a1545 SH	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Simon Horman
	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
1e851538	12	#include <dt-bindings/clock/r8a7779-clock.h>
cea80654	13	#include <dt-bindings/interrupt-controller/arm-gic.h>
5f75e73c	14	#include <dt-bindings/interrupt-controller/irq.h>
b2df3aa4	15	#include <dt-bindings/power/r8a7779-sysc.h>
5f75e73c	16
c58a1545 SH	17	/ {
c58a1545 SH	18	compatible = "renesas,r8a7779";
9ff254ad	19	interrupt-parent = <&gic>;
1cfc0c03 GU	20	#address-cells = <1>;
1cfc0c03 GU	21	#size-cells = <1>;
c58a1545 SH	22
	23	cpus {
	24	#address-cells = <1>;
	25	#size-cells = <0>;
	26
	27	cpu@0 {
	28	device_type = "cpu";
	29	compatible = "arm,cortex-a9";
	30	reg = <0>;
6b060f93	31	clock-frequency = <1000000000>;
fa9f95a3	32	clocks = <&cpg_clocks R8A7779_CLK_Z>;
c58a1545 SH	33	};
	34	cpu@1 {
	35	device_type = "cpu";
	36	compatible = "arm,cortex-a9";
	37	reg = <1>;
6b060f93	38	clock-frequency = <1000000000>;
fa9f95a3	39	clocks = <&cpg_clocks R8A7779_CLK_Z>;
b2df3aa4	40	power-domains = <&sysc R8A7779_PD_ARM1>;
c58a1545 SH	41	};
	42	cpu@2 {
	43	device_type = "cpu";
	44	compatible = "arm,cortex-a9";
	45	reg = <2>;
6b060f93	46	clock-frequency = <1000000000>;
fa9f95a3	47	clocks = <&cpg_clocks R8A7779_CLK_Z>;
b2df3aa4	48	power-domains = <&sysc R8A7779_PD_ARM2>;
c58a1545 SH	49	};
	50	cpu@3 {
	51	device_type = "cpu";
	52	compatible = "arm,cortex-a9";
	53	reg = <3>;
6b060f93	54	clock-frequency = <1000000000>;
fa9f95a3	55	clocks = <&cpg_clocks R8A7779_CLK_Z>;
b2df3aa4	56	power-domains = <&sysc R8A7779_PD_ARM3>;
c58a1545 SH	57	};
	58	};
	59
3c3f6ad3 SH	60	aliases {
	61	spi0 = &hspi0;
	62	spi1 = &hspi1;
	63	spi2 = &hspi2;
	64	};
	65
cc703a59 SH	66	gic: interrupt-controller@f0001000 {
	67	compatible = "arm,cortex-a9-gic";
	68	#interrupt-cells = <3>;
	69	interrupt-controller;
	70	reg = <0xf0001000 0x1000>,
	71	<0xf0000100 0x100>;
	72	};
10e8d4f6	73
cea80654 MD	74	timer@f0000600 {
	75	compatible = "arm,cortex-a9-twd-timer";
	76	reg = <0xf0000600 0x20>;
	77	interrupts = <GIC_PPI 13
e6c24882	78	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>;
cea80654 MD	79	clocks = <&cpg_clocks R8A7779_CLK_ZS>;
	80	};
	81
f5c771b5	82	gpio0: gpio@ffc40000 {
88cb141b	83	compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
f5c771b5	84	reg = <0xffc40000 0x2c>;
854b7733	85	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	86	#gpio-cells = <2>;
	87	gpio-controller;
	88	gpio-ranges = <&pfc 0 0 32>;
	89	#interrupt-cells = <2>;
	90	interrupt-controller;
	91	};
	92
	93	gpio1: gpio@ffc41000 {
88cb141b	94	compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
f5c771b5	95	reg = <0xffc41000 0x2c>;
854b7733	96	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	97	#gpio-cells = <2>;
	98	gpio-controller;
	99	gpio-ranges = <&pfc 0 32 32>;
	100	#interrupt-cells = <2>;
	101	interrupt-controller;
	102	};
	103
	104	gpio2: gpio@ffc42000 {
88cb141b	105	compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
f5c771b5	106	reg = <0xffc42000 0x2c>;
854b7733	107	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	108	#gpio-cells = <2>;
	109	gpio-controller;
	110	gpio-ranges = <&pfc 0 64 32>;
	111	#interrupt-cells = <2>;
	112	interrupt-controller;
	113	};
	114
	115	gpio3: gpio@ffc43000 {
88cb141b	116	compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
f5c771b5	117	reg = <0xffc43000 0x2c>;
854b7733	118	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	119	#gpio-cells = <2>;
	120	gpio-controller;
	121	gpio-ranges = <&pfc 0 96 32>;
	122	#interrupt-cells = <2>;
	123	interrupt-controller;
	124	};
	125
	126	gpio4: gpio@ffc44000 {
88cb141b	127	compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
f5c771b5	128	reg = <0xffc44000 0x2c>;
854b7733	129	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	130	#gpio-cells = <2>;
	131	gpio-controller;
	132	gpio-ranges = <&pfc 0 128 32>;
	133	#interrupt-cells = <2>;
	134	interrupt-controller;
	135	};
	136
	137	gpio5: gpio@ffc45000 {
88cb141b	138	compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
f5c771b5	139	reg = <0xffc45000 0x2c>;
854b7733	140	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	141	#gpio-cells = <2>;
	142	gpio-controller;
	143	gpio-ranges = <&pfc 0 160 32>;
	144	#interrupt-cells = <2>;
	145	interrupt-controller;
	146	};
	147
	148	gpio6: gpio@ffc46000 {
88cb141b	149	compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
f5c771b5	150	reg = <0xffc46000 0x2c>;
854b7733	151	interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	152	#gpio-cells = <2>;
	153	gpio-controller;
	154	gpio-ranges = <&pfc 0 192 9>;
	155	#interrupt-cells = <2>;
	156	interrupt-controller;
	157	};
	158
7bf46d0b	159	irqpin0: interrupt-controller@fe78001c {
11ef0340	160	compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
24603f3c	161	#interrupt-cells = <2>;
84b47dfc	162	status = "disabled";
24603f3c GL	163	interrupt-controller;
	164	reg = <0xfe78001c 4>,
	165	<0xfe780010 4>,
	166	<0xfe780024 4>,
	167	<0xfe780044 4>,
7bf46d0b MD	168	<0xfe780064 4>,
7bf46d0b MD	169	<0xfe780000 4>;
854b7733 SH	170	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
	171	GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
	172	GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
	173	GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
24603f3c GL	174	sense-bitfield-width = <2>;
	175	};
	176
98724b7e	177	i2c0: i2c@ffc70000 {
10e8d4f6 SH	178	#address-cells = <1>;
10e8d4f6 SH	179	#size-cells = <0>;
137d27f1	180	compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
10e8d4f6	181	reg = <0xffc70000 0x1000>;
854b7733	182	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	183	clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
751e29bb	184	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
eda3a4fa	185	status = "disabled";
10e8d4f6 SH	186	};
10e8d4f6 SH	187
98724b7e	188	i2c1: i2c@ffc71000 {
10e8d4f6 SH	189	#address-cells = <1>;
10e8d4f6 SH	190	#size-cells = <0>;
137d27f1	191	compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
10e8d4f6	192	reg = <0xffc71000 0x1000>;
854b7733	193	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	194	clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
751e29bb	195	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
eda3a4fa	196	status = "disabled";
10e8d4f6 SH	197	};
10e8d4f6 SH	198
98724b7e	199	i2c2: i2c@ffc72000 {
10e8d4f6 SH	200	#address-cells = <1>;
10e8d4f6 SH	201	#size-cells = <0>;
137d27f1	202	compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
10e8d4f6	203	reg = <0xffc72000 0x1000>;
854b7733	204	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	205	clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
751e29bb	206	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
eda3a4fa	207	status = "disabled";
10e8d4f6 SH	208	};
10e8d4f6 SH	209
98724b7e	210	i2c3: i2c@ffc73000 {
10e8d4f6 SH	211	#address-cells = <1>;
10e8d4f6 SH	212	#size-cells = <0>;
137d27f1	213	compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
10e8d4f6	214	reg = <0xffc73000 0x1000>;
854b7733	215	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	216	clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
751e29bb	217	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
eda3a4fa	218	status = "disabled";
10e8d4f6	219	};
25a65975	220
fd953b89	221	scif0: serial@ffe40000 {
b2ac44fa GU	222	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	223	"renesas,scif";
fd953b89	224	reg = <0xffe40000 0x100>;
854b7733	225	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	226	clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
	227	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	228	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	229	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	230	status = "disabled";
	231	};
	232
	233	scif1: serial@ffe41000 {
b2ac44fa GU	234	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	235	"renesas,scif";
fd953b89	236	reg = <0xffe41000 0x100>;
854b7733	237	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	238	clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
	239	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	240	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	241	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	242	status = "disabled";
	243	};
	244
	245	scif2: serial@ffe42000 {
b2ac44fa GU	246	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	247	"renesas,scif";
fd953b89	248	reg = <0xffe42000 0x100>;
854b7733	249	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	250	clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
	251	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	252	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	253	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	254	status = "disabled";
	255	};
	256
	257	scif3: serial@ffe43000 {
b2ac44fa GU	258	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	259	"renesas,scif";
fd953b89	260	reg = <0xffe43000 0x100>;
854b7733	261	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	262	clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
	263	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	264	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	265	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	266	status = "disabled";
	267	};
	268
	269	scif4: serial@ffe44000 {
b2ac44fa GU	270	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	271	"renesas,scif";
fd953b89	272	reg = <0xffe44000 0x100>;
854b7733	273	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	274	clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
	275	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	276	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	277	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	278	status = "disabled";
	279	};
	280
	281	scif5: serial@ffe45000 {
b2ac44fa GU	282	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	283	"renesas,scif";
fd953b89	284	reg = <0xffe45000 0x100>;
854b7733	285	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	286	clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
	287	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	288	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	289	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	290	status = "disabled";
	291	};
	292
b07b763c	293	pfc: pin-controller@fffc0000 {
3ab03d01 LP	294	compatible = "renesas,pfc-r8a7779";
	295	reg = <0xfffc0000 0x23c>;
	296	};
	297
25a65975	298	thermal@ffc48000 {
4d50e6dd	299	compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
25a65975 KM	300	reg = <0xffc48000 0x38>;
25a65975 KM	301	};
7840a65a	302
ef890ea2	303	tmu0: timer@ffd80000 {
a51b7b38	304	compatible = "renesas,tmu-r8a7779", "renesas,tmu";
ef890ea2	305	reg = <0xffd80000 0x30>;
854b7733 SH	306	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	307	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	308	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
ef890ea2 LP	309	clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
ef890ea2 LP	310	clock-names = "fck";
751e29bb	311	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
ef890ea2 LP	312
	313	#renesas,channels = <3>;
	314
	315	status = "disabled";
	316	};
	317
	318	tmu1: timer@ffd81000 {
a51b7b38	319	compatible = "renesas,tmu-r8a7779", "renesas,tmu";
ef890ea2	320	reg = <0xffd81000 0x30>;
854b7733 SH	321	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	322	<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
	323	<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
ef890ea2 LP	324	clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
ef890ea2 LP	325	clock-names = "fck";
751e29bb	326	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
ef890ea2 LP	327
	328	#renesas,channels = <3>;
	329
	330	status = "disabled";
	331	};
	332
	333	tmu2: timer@ffd82000 {
a51b7b38	334	compatible = "renesas,tmu-r8a7779", "renesas,tmu";
ef890ea2	335	reg = <0xffd82000 0x30>;
854b7733 SH	336	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	337	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	338	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ef890ea2 LP	339	clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
ef890ea2 LP	340	clock-names = "fck";
751e29bb	341	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
ef890ea2 LP	342
	343	#renesas,channels = <3>;
	344
	345	status = "disabled";
	346	};
	347
7840a65a	348	sata: sata@fc600000 {
25af9c83	349	compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
88423251	350	reg = <0xfc600000 0x200000>;
854b7733	351	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	352	clocks = <&mstp1_clks R8A7779_CLK_SATA>;
751e29bb	353	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
e8aa6811	354	status = "disabled";
7840a65a	355	};
c4866e70	356
2624705c	357	sdhi0: sd@ffe4c000 {
c4866e70 KM	358	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	359	reg = <0xffe4c000 0x100>;
854b7733	360	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	361	clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
751e29bb	362	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
c4866e70 KM	363	status = "disabled";
	364	};
	365
2624705c	366	sdhi1: sd@ffe4d000 {
c4866e70 KM	367	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	368	reg = <0xffe4d000 0x100>;
854b7733	369	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	370	clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
751e29bb	371	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
c4866e70 KM	372	status = "disabled";
	373	};
	374
2624705c	375	sdhi2: sd@ffe4e000 {
c4866e70 KM	376	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	377	reg = <0xffe4e000 0x100>;
854b7733	378	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	379	clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
751e29bb	380	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
c4866e70 KM	381	status = "disabled";
	382	};
	383
2624705c	384	sdhi3: sd@ffe4f000 {
c4866e70 KM	385	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	386	reg = <0xffe4f000 0x100>;
854b7733	387	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	388	clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
751e29bb	389	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
c4866e70 KM	390	status = "disabled";
c4866e70 KM	391	};
3c3f6ad3 SH	392
3c3f6ad3 SH	393	hspi0: spi@fffc7000 {
7709c33b	394	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	395	reg = <0xfffc7000 0x18>;
854b7733	396	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	397	#address-cells = <1>;
7709c33b GU	398	#size-cells = <0>;
3325cbe8	399	clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
751e29bb	400	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
3c3f6ad3 SH	401	status = "disabled";
	402	};
	403
	404	hspi1: spi@fffc8000 {
7709c33b	405	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	406	reg = <0xfffc8000 0x18>;
854b7733	407	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	408	#address-cells = <1>;
7709c33b GU	409	#size-cells = <0>;
3325cbe8	410	clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
751e29bb	411	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
3c3f6ad3 SH	412	status = "disabled";
	413	};
	414
	415	hspi2: spi@fffc6000 {
7709c33b	416	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	417	reg = <0xfffc6000 0x18>;
854b7733	418	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	419	#address-cells = <1>;
7709c33b GU	420	#size-cells = <0>;
3325cbe8	421	clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
751e29bb	422	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
3c3f6ad3 SH	423	status = "disabled";
3c3f6ad3 SH	424	};
1e851538	425
1f08bbe8 LP	426	du: display@fff80000 {
1f08bbe8 LP	427	compatible = "renesas,du-r8a7779";
30524edf	428	reg = <0xfff80000 0x40000>;
854b7733	429	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1f08bbe8	430	clocks = <&mstp1_clks R8A7779_CLK_DU>;
751e29bb	431	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
1f08bbe8 LP	432	status = "disabled";
	433
	434	ports {
	435	#address-cells = <1>;
	436	#size-cells = <0>;
	437
	438	port@0 {
	439	reg = <0>;
	440	du_out_rgb0: endpoint {
	441	};
	442	};
	443	port@1 {
	444	reg = <1>;
	445	du_out_rgb1: endpoint {
	446	};
	447	};
	448	};
	449	};
	450
1e851538	451	clocks {
5cc8afcb GU	452	#address-cells = <1>;
5cc8afcb GU	453	#size-cells = <1>;
1e851538 SH	454	ranges;
	455
	456	/* External root clock */
3f6dba70	457	extal_clk: extal {
1e851538 SH	458	compatible = "fixed-clock";
	459	#clock-cells = <0>;
	460	/* This value must be overriden by the board. */
	461	clock-frequency = <0>;
1e851538 SH	462	};
1e851538 SH	463
f2be5f00 GU	464	/* External SCIF clock */
	465	scif_clk: scif {
	466	compatible = "fixed-clock";
	467	#clock-cells = <0>;
	468	/* This value must be overridden by the board. */
	469	clock-frequency = <0>;
f2be5f00 GU	470	};
f2be5f00 GU	471
1e851538	472	/* Special CPG clocks */
2909b874	473	cpg_clocks: clocks@ffc80000 {
1e851538	474	compatible = "renesas,r8a7779-cpg-clocks";
5cc8afcb	475	reg = <0xffc80000 0x30>;
1e851538 SH	476	clocks = <&extal_clk>;
	477	#clock-cells = <1>;
	478	clock-output-names = "plla", "z", "zs", "s",
	479	"s1", "p", "b", "out";
33c3632a	480	#power-domain-cells = <0>;
1e851538 SH	481	};
	482
	483	/* Fixed factor clocks */
3f6dba70	484	i_clk: i {
1e851538 SH	485	compatible = "fixed-factor-clock";
	486	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	487	#clock-cells = <0>;
	488	clock-div = <2>;
	489	clock-mult = <1>;
1e851538	490	};
3f6dba70	491	s3_clk: s3 {
1e851538 SH	492	compatible = "fixed-factor-clock";
	493	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	494	#clock-cells = <0>;
	495	clock-div = <8>;
	496	clock-mult = <1>;
1e851538	497	};
3f6dba70	498	s4_clk: s4 {
1e851538 SH	499	compatible = "fixed-factor-clock";
	500	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	501	#clock-cells = <0>;
	502	clock-div = <16>;
	503	clock-mult = <1>;
1e851538	504	};
3f6dba70	505	g_clk: g {
1e851538 SH	506	compatible = "fixed-factor-clock";
	507	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	508	#clock-cells = <0>;
	509	clock-div = <24>;
	510	clock-mult = <1>;
1e851538 SH	511	};
	512
	513	/* Gate clocks */
2909b874	514	mstp0_clks: clocks@ffc80030 {
1e851538	515	compatible = "renesas,r8a7779-mstp-clocks",
99e544c7	516	"renesas,cpg-mstp-clocks";
5cc8afcb	517	reg = <0xffc80030 4>;
1e851538	518	clocks = <&cpg_clocks R8A7779_CLK_S>,
99e544c7	519	<&cpg_clocks R8A7779_CLK_P>,
1e851538 SH	520	<&cpg_clocks R8A7779_CLK_P>,
	521	<&cpg_clocks R8A7779_CLK_P>,
	522	<&cpg_clocks R8A7779_CLK_S>,
	523	<&cpg_clocks R8A7779_CLK_S>,
c6ce3cdf MD	524	<&cpg_clocks R8A7779_CLK_P>,
	525	<&cpg_clocks R8A7779_CLK_P>,
	526	<&cpg_clocks R8A7779_CLK_P>,
	527	<&cpg_clocks R8A7779_CLK_P>,
	528	<&cpg_clocks R8A7779_CLK_P>,
	529	<&cpg_clocks R8A7779_CLK_P>,
1e851538 SH	530	<&cpg_clocks R8A7779_CLK_P>,
	531	<&cpg_clocks R8A7779_CLK_P>,
	532	<&cpg_clocks R8A7779_CLK_P>,
	533	<&cpg_clocks R8A7779_CLK_P>;
	534	#clock-cells = <1>;
64530fc2	535	clock-indices = <
1e851538 SH	536	R8A7779_CLK_HSPI R8A7779_CLK_TMU2
	537	R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
	538	R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
	539	R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
	540	R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
	541	R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
	542	R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
	543	R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
	544	>;
	545	clock-output-names =
	546	"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
	547	"hscif0", "scif5", "scif4", "scif3", "scif2",
	548	"scif1", "scif0", "i2c3", "i2c2", "i2c1",
	549	"i2c0";
	550	};
2909b874	551	mstp1_clks: clocks@ffc80034 {
1e851538	552	compatible = "renesas,r8a7779-mstp-clocks",
99e544c7	553	"renesas,cpg-mstp-clocks";
5cc8afcb	554	reg = <0xffc80034 4>, <0xffc80044 4>;
1e851538 SH	555	clocks = <&cpg_clocks R8A7779_CLK_P>,
	556	<&cpg_clocks R8A7779_CLK_P>,
	557	<&cpg_clocks R8A7779_CLK_S>,
	558	<&cpg_clocks R8A7779_CLK_S>,
	559	<&cpg_clocks R8A7779_CLK_S>,
	560	<&cpg_clocks R8A7779_CLK_S>,
	561	<&cpg_clocks R8A7779_CLK_P>,
	562	<&cpg_clocks R8A7779_CLK_P>,
	563	<&cpg_clocks R8A7779_CLK_P>,
	564	<&cpg_clocks R8A7779_CLK_S>;
	565	#clock-cells = <1>;
64530fc2	566	clock-indices = <
1e851538 SH	567	R8A7779_CLK_USB01 R8A7779_CLK_USB2
	568	R8A7779_CLK_DU R8A7779_CLK_VIN2
	569	R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
	570	R8A7779_CLK_ETHER R8A7779_CLK_SATA
	571	R8A7779_CLK_PCIE R8A7779_CLK_VIN3
	572	>;
	573	clock-output-names =
	574	"usb01", "usb2",
	575	"du", "vin2",
	576	"vin1", "vin0",
	577	"ether", "sata",
	578	"pcie", "vin3";
	579	};
2909b874	580	mstp3_clks: clocks@ffc8003c {
1e851538	581	compatible = "renesas,r8a7779-mstp-clocks",
99e544c7	582	"renesas,cpg-mstp-clocks";
5cc8afcb	583	reg = <0xffc8003c 4>;
1e851538 SH	584	clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
	585	<&s4_clk>, <&s4_clk>;
	586	#clock-cells = <1>;
64530fc2	587	clock-indices = <
1e851538 SH	588	R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
	589	R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
	590	R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
	591	>;
	592	clock-output-names =
	593	"sdhi3", "sdhi2", "sdhi1", "sdhi0",
	594	"mmc1", "mmc0";
	595	};
	596	};
b2df3aa4	597
9ba368e2 GU	598	prr: chipid@ff000044 {
	599	compatible = "renesas,prr";
	600	reg = <0xff000044 4>;
	601	};
	602
ad40150a GU	603	rst: reset-controller@ffcc0000 {
	604	compatible = "renesas,r8a7779-reset-wdt";
	605	reg = <0xffcc0000 0x48>;
	606	};
	607
b2df3aa4 GU	608	sysc: system-controller@ffd85000 {
	609	compatible = "renesas,r8a7779-sysc";
	610	reg = <0xffd85000 0x0200>;
	611	#power-domain-cells = <1>;
	612	};
c58a1545	613	};