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ARM: shmobile: r8a7779: Use R8A7779_CLK_P as SCIF parent clock
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c58a1545 1/*
349f556e 2 * Device Tree Source for Renesas r8a7779
c58a1545
SH
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/include/ "skeleton.dtsi"
13
1e851538 14#include <dt-bindings/clock/r8a7779-clock.h>
5f75e73c
LP
15#include <dt-bindings/interrupt-controller/irq.h>
16
c58a1545
SH
17/ {
18 compatible = "renesas,r8a7779";
9ff254ad 19 interrupt-parent = <&gic>;
c58a1545
SH
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <0>;
6b060f93 29 clock-frequency = <1000000000>;
c58a1545
SH
30 };
31 cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 reg = <1>;
6b060f93 35 clock-frequency = <1000000000>;
c58a1545
SH
36 };
37 cpu@2 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a9";
40 reg = <2>;
6b060f93 41 clock-frequency = <1000000000>;
c58a1545
SH
42 };
43 cpu@3 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a9";
46 reg = <3>;
6b060f93 47 clock-frequency = <1000000000>;
c58a1545
SH
48 };
49 };
50
3c3f6ad3
SH
51 aliases {
52 spi0 = &hspi0;
53 spi1 = &hspi1;
54 spi2 = &hspi2;
55 };
56
cc703a59
SH
57 gic: interrupt-controller@f0001000 {
58 compatible = "arm,cortex-a9-gic";
59 #interrupt-cells = <3>;
60 interrupt-controller;
61 reg = <0xf0001000 0x1000>,
62 <0xf0000100 0x100>;
63 };
10e8d4f6 64
f5c771b5
LP
65 gpio0: gpio@ffc40000 {
66 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
67 reg = <0xffc40000 0x2c>;
5f75e73c 68 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5
LP
69 #gpio-cells = <2>;
70 gpio-controller;
71 gpio-ranges = <&pfc 0 0 32>;
72 #interrupt-cells = <2>;
73 interrupt-controller;
74 };
75
76 gpio1: gpio@ffc41000 {
77 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
78 reg = <0xffc41000 0x2c>;
5f75e73c 79 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5
LP
80 #gpio-cells = <2>;
81 gpio-controller;
82 gpio-ranges = <&pfc 0 32 32>;
83 #interrupt-cells = <2>;
84 interrupt-controller;
85 };
86
87 gpio2: gpio@ffc42000 {
88 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
89 reg = <0xffc42000 0x2c>;
5f75e73c 90 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5
LP
91 #gpio-cells = <2>;
92 gpio-controller;
93 gpio-ranges = <&pfc 0 64 32>;
94 #interrupt-cells = <2>;
95 interrupt-controller;
96 };
97
98 gpio3: gpio@ffc43000 {
99 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
100 reg = <0xffc43000 0x2c>;
5f75e73c 101 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5
LP
102 #gpio-cells = <2>;
103 gpio-controller;
104 gpio-ranges = <&pfc 0 96 32>;
105 #interrupt-cells = <2>;
106 interrupt-controller;
107 };
108
109 gpio4: gpio@ffc44000 {
110 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
111 reg = <0xffc44000 0x2c>;
5f75e73c 112 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5
LP
113 #gpio-cells = <2>;
114 gpio-controller;
115 gpio-ranges = <&pfc 0 128 32>;
116 #interrupt-cells = <2>;
117 interrupt-controller;
118 };
119
120 gpio5: gpio@ffc45000 {
121 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
122 reg = <0xffc45000 0x2c>;
5f75e73c 123 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5
LP
124 #gpio-cells = <2>;
125 gpio-controller;
126 gpio-ranges = <&pfc 0 160 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
129 };
130
131 gpio6: gpio@ffc46000 {
132 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
133 reg = <0xffc46000 0x2c>;
5f75e73c 134 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5
LP
135 #gpio-cells = <2>;
136 gpio-controller;
137 gpio-ranges = <&pfc 0 192 9>;
138 #interrupt-cells = <2>;
139 interrupt-controller;
140 };
141
24603f3c 142 irqpin0: irqpin@fe780010 {
11ef0340 143 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
24603f3c 144 #interrupt-cells = <2>;
84b47dfc 145 status = "disabled";
24603f3c
GL
146 interrupt-controller;
147 reg = <0xfe78001c 4>,
148 <0xfe780010 4>,
149 <0xfe780024 4>,
150 <0xfe780044 4>,
151 <0xfe780064 4>;
5f75e73c
LP
152 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
153 0 28 IRQ_TYPE_LEVEL_HIGH
154 0 29 IRQ_TYPE_LEVEL_HIGH
155 0 30 IRQ_TYPE_LEVEL_HIGH>;
24603f3c
GL
156 sense-bitfield-width = <2>;
157 };
158
98724b7e 159 i2c0: i2c@ffc70000 {
10e8d4f6
SH
160 #address-cells = <1>;
161 #size-cells = <0>;
6363070e 162 compatible = "renesas,i2c-r8a7779";
10e8d4f6 163 reg = <0xffc70000 0x1000>;
5f75e73c 164 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8 165 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
eda3a4fa 166 status = "disabled";
10e8d4f6
SH
167 };
168
98724b7e 169 i2c1: i2c@ffc71000 {
10e8d4f6
SH
170 #address-cells = <1>;
171 #size-cells = <0>;
6363070e 172 compatible = "renesas,i2c-r8a7779";
10e8d4f6 173 reg = <0xffc71000 0x1000>;
5f75e73c 174 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8 175 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
eda3a4fa 176 status = "disabled";
10e8d4f6
SH
177 };
178
98724b7e 179 i2c2: i2c@ffc72000 {
10e8d4f6
SH
180 #address-cells = <1>;
181 #size-cells = <0>;
6363070e 182 compatible = "renesas,i2c-r8a7779";
10e8d4f6 183 reg = <0xffc72000 0x1000>;
5f75e73c 184 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8 185 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
eda3a4fa 186 status = "disabled";
10e8d4f6
SH
187 };
188
98724b7e 189 i2c3: i2c@ffc73000 {
10e8d4f6
SH
190 #address-cells = <1>;
191 #size-cells = <0>;
6363070e 192 compatible = "renesas,i2c-r8a7779";
10e8d4f6 193 reg = <0xffc73000 0x1000>;
5f75e73c 194 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8 195 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
eda3a4fa 196 status = "disabled";
10e8d4f6 197 };
25a65975 198
fd953b89
SH
199 scif0: serial@ffe40000 {
200 compatible = "renesas,scif-r8a7779", "renesas,scif";
201 reg = <0xffe40000 0x100>;
fd953b89
SH
202 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&cpg_clocks R8A7779_CLK_P>;
204 clock-names = "sci_ick";
205 status = "disabled";
206 };
207
208 scif1: serial@ffe41000 {
209 compatible = "renesas,scif-r8a7779", "renesas,scif";
210 reg = <0xffe41000 0x100>;
fd953b89
SH
211 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cpg_clocks R8A7779_CLK_P>;
213 clock-names = "sci_ick";
214 status = "disabled";
215 };
216
217 scif2: serial@ffe42000 {
218 compatible = "renesas,scif-r8a7779", "renesas,scif";
219 reg = <0xffe42000 0x100>;
fd953b89
SH
220 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cpg_clocks R8A7779_CLK_P>;
222 clock-names = "sci_ick";
223 status = "disabled";
224 };
225
226 scif3: serial@ffe43000 {
227 compatible = "renesas,scif-r8a7779", "renesas,scif";
228 reg = <0xffe43000 0x100>;
fd953b89
SH
229 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cpg_clocks R8A7779_CLK_P>;
231 clock-names = "sci_ick";
232 status = "disabled";
233 };
234
235 scif4: serial@ffe44000 {
236 compatible = "renesas,scif-r8a7779", "renesas,scif";
237 reg = <0xffe44000 0x100>;
fd953b89
SH
238 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&cpg_clocks R8A7779_CLK_P>;
240 clock-names = "sci_ick";
241 status = "disabled";
242 };
243
244 scif5: serial@ffe45000 {
245 compatible = "renesas,scif-r8a7779", "renesas,scif";
246 reg = <0xffe45000 0x100>;
fd953b89
SH
247 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cpg_clocks R8A7779_CLK_P>;
249 clock-names = "sci_ick";
250 status = "disabled";
251 };
252
3ab03d01
LP
253 pfc: pfc@fffc0000 {
254 compatible = "renesas,pfc-r8a7779";
255 reg = <0xfffc0000 0x23c>;
256 };
257
25a65975 258 thermal@ffc48000 {
4d50e6dd 259 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
25a65975
KM
260 reg = <0xffc48000 0x38>;
261 };
7840a65a 262
ef890ea2 263 tmu0: timer@ffd80000 {
a51b7b38 264 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
ef890ea2
LP
265 reg = <0xffd80000 0x30>;
266 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
267 <0 33 IRQ_TYPE_LEVEL_HIGH>,
268 <0 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
270 clock-names = "fck";
271
272 #renesas,channels = <3>;
273
274 status = "disabled";
275 };
276
277 tmu1: timer@ffd81000 {
a51b7b38 278 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
ef890ea2
LP
279 reg = <0xffd81000 0x30>;
280 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
281 <0 37 IRQ_TYPE_LEVEL_HIGH>,
282 <0 38 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
284 clock-names = "fck";
285
286 #renesas,channels = <3>;
287
288 status = "disabled";
289 };
290
291 tmu2: timer@ffd82000 {
a51b7b38 292 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
ef890ea2
LP
293 reg = <0xffd82000 0x30>;
294 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
295 <0 41 IRQ_TYPE_LEVEL_HIGH>,
296 <0 42 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
298 clock-names = "fck";
299
300 #renesas,channels = <3>;
301
302 status = "disabled";
303 };
304
7840a65a 305 sata: sata@fc600000 {
25af9c83 306 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
7840a65a 307 reg = <0xfc600000 0x2000>;
5f75e73c 308 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8 309 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
7840a65a 310 };
c4866e70 311
2624705c 312 sdhi0: sd@ffe4c000 {
c4866e70
KM
313 compatible = "renesas,sdhi-r8a7779";
314 reg = <0xffe4c000 0x100>;
5f75e73c 315 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8 316 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
c4866e70
KM
317 status = "disabled";
318 };
319
2624705c 320 sdhi1: sd@ffe4d000 {
c4866e70
KM
321 compatible = "renesas,sdhi-r8a7779";
322 reg = <0xffe4d000 0x100>;
5f75e73c 323 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8 324 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
c4866e70
KM
325 status = "disabled";
326 };
327
2624705c 328 sdhi2: sd@ffe4e000 {
c4866e70
KM
329 compatible = "renesas,sdhi-r8a7779";
330 reg = <0xffe4e000 0x100>;
5f75e73c 331 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8 332 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
c4866e70
KM
333 status = "disabled";
334 };
335
2624705c 336 sdhi3: sd@ffe4f000 {
c4866e70
KM
337 compatible = "renesas,sdhi-r8a7779";
338 reg = <0xffe4f000 0x100>;
5f75e73c 339 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8 340 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
c4866e70
KM
341 status = "disabled";
342 };
3c3f6ad3
SH
343
344 hspi0: spi@fffc7000 {
7709c33b 345 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3 346 reg = <0xfffc7000 0x18>;
3c3f6ad3 347 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
7709c33b
GU
348 #address-cells = <1>;
349 #size-cells = <0>;
3325cbe8 350 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
3c3f6ad3
SH
351 status = "disabled";
352 };
353
354 hspi1: spi@fffc8000 {
7709c33b 355 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3 356 reg = <0xfffc8000 0x18>;
3c3f6ad3 357 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
7709c33b
GU
358 #address-cells = <1>;
359 #size-cells = <0>;
3325cbe8 360 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
3c3f6ad3
SH
361 status = "disabled";
362 };
363
364 hspi2: spi@fffc6000 {
7709c33b 365 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3 366 reg = <0xfffc6000 0x18>;
3c3f6ad3 367 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
7709c33b
GU
368 #address-cells = <1>;
369 #size-cells = <0>;
3325cbe8 370 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
3c3f6ad3
SH
371 status = "disabled";
372 };
1e851538 373
1f08bbe8
LP
374 du: display@fff80000 {
375 compatible = "renesas,du-r8a7779";
376 reg = <0 0xfff80000 0 0x40000>;
377 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&mstp1_clks R8A7779_CLK_DU>;
379 status = "disabled";
380
381 ports {
382 #address-cells = <1>;
383 #size-cells = <0>;
384
385 port@0 {
386 reg = <0>;
387 du_out_rgb0: endpoint {
388 };
389 };
390 port@1 {
391 reg = <1>;
392 du_out_rgb1: endpoint {
393 };
394 };
395 };
396 };
397
1e851538 398 clocks {
5cc8afcb
GU
399 #address-cells = <1>;
400 #size-cells = <1>;
1e851538
SH
401 ranges;
402
403 /* External root clock */
404 extal_clk: extal_clk {
405 compatible = "fixed-clock";
406 #clock-cells = <0>;
407 /* This value must be overriden by the board. */
408 clock-frequency = <0>;
409 clock-output-names = "extal";
410 };
411
412 /* Special CPG clocks */
2909b874 413 cpg_clocks: clocks@ffc80000 {
1e851538 414 compatible = "renesas,r8a7779-cpg-clocks";
5cc8afcb 415 reg = <0xffc80000 0x30>;
1e851538
SH
416 clocks = <&extal_clk>;
417 #clock-cells = <1>;
418 clock-output-names = "plla", "z", "zs", "s",
419 "s1", "p", "b", "out";
420 };
421
422 /* Fixed factor clocks */
423 i_clk: i_clk {
424 compatible = "fixed-factor-clock";
425 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
426 #clock-cells = <0>;
427 clock-div = <2>;
428 clock-mult = <1>;
429 clock-output-names = "i";
430 };
431 s3_clk: s3_clk {
432 compatible = "fixed-factor-clock";
433 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
434 #clock-cells = <0>;
435 clock-div = <8>;
436 clock-mult = <1>;
437 clock-output-names = "s3";
438 };
439 s4_clk: s4_clk {
440 compatible = "fixed-factor-clock";
441 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
442 #clock-cells = <0>;
443 clock-div = <16>;
444 clock-mult = <1>;
445 clock-output-names = "s4";
446 };
447 g_clk: g_clk {
448 compatible = "fixed-factor-clock";
449 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
450 #clock-cells = <0>;
451 clock-div = <24>;
452 clock-mult = <1>;
453 clock-output-names = "g";
454 };
455
456 /* Gate clocks */
2909b874 457 mstp0_clks: clocks@ffc80030 {
1e851538 458 compatible = "renesas,r8a7779-mstp-clocks",
99e544c7 459 "renesas,cpg-mstp-clocks";
5cc8afcb 460 reg = <0xffc80030 4>;
1e851538 461 clocks = <&cpg_clocks R8A7779_CLK_S>,
99e544c7 462 <&cpg_clocks R8A7779_CLK_P>,
1e851538
SH
463 <&cpg_clocks R8A7779_CLK_P>,
464 <&cpg_clocks R8A7779_CLK_P>,
465 <&cpg_clocks R8A7779_CLK_S>,
466 <&cpg_clocks R8A7779_CLK_S>,
c6ce3cdf
MD
467 <&cpg_clocks R8A7779_CLK_P>,
468 <&cpg_clocks R8A7779_CLK_P>,
469 <&cpg_clocks R8A7779_CLK_P>,
470 <&cpg_clocks R8A7779_CLK_P>,
471 <&cpg_clocks R8A7779_CLK_P>,
472 <&cpg_clocks R8A7779_CLK_P>,
1e851538
SH
473 <&cpg_clocks R8A7779_CLK_P>,
474 <&cpg_clocks R8A7779_CLK_P>,
475 <&cpg_clocks R8A7779_CLK_P>,
476 <&cpg_clocks R8A7779_CLK_P>;
477 #clock-cells = <1>;
64530fc2 478 clock-indices = <
1e851538
SH
479 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
480 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
481 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
482 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
483 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
484 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
485 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
486 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
487 >;
488 clock-output-names =
489 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
490 "hscif0", "scif5", "scif4", "scif3", "scif2",
491 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
492 "i2c0";
493 };
2909b874 494 mstp1_clks: clocks@ffc80034 {
1e851538 495 compatible = "renesas,r8a7779-mstp-clocks",
99e544c7 496 "renesas,cpg-mstp-clocks";
5cc8afcb 497 reg = <0xffc80034 4>, <0xffc80044 4>;
1e851538
SH
498 clocks = <&cpg_clocks R8A7779_CLK_P>,
499 <&cpg_clocks R8A7779_CLK_P>,
500 <&cpg_clocks R8A7779_CLK_S>,
501 <&cpg_clocks R8A7779_CLK_S>,
502 <&cpg_clocks R8A7779_CLK_S>,
503 <&cpg_clocks R8A7779_CLK_S>,
504 <&cpg_clocks R8A7779_CLK_P>,
505 <&cpg_clocks R8A7779_CLK_P>,
506 <&cpg_clocks R8A7779_CLK_P>,
507 <&cpg_clocks R8A7779_CLK_S>;
508 #clock-cells = <1>;
64530fc2 509 clock-indices = <
1e851538
SH
510 R8A7779_CLK_USB01 R8A7779_CLK_USB2
511 R8A7779_CLK_DU R8A7779_CLK_VIN2
512 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
513 R8A7779_CLK_ETHER R8A7779_CLK_SATA
514 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
515 >;
516 clock-output-names =
517 "usb01", "usb2",
518 "du", "vin2",
519 "vin1", "vin0",
520 "ether", "sata",
521 "pcie", "vin3";
522 };
2909b874 523 mstp3_clks: clocks@ffc8003c {
1e851538 524 compatible = "renesas,r8a7779-mstp-clocks",
99e544c7 525 "renesas,cpg-mstp-clocks";
5cc8afcb 526 reg = <0xffc8003c 4>;
1e851538
SH
527 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
528 <&s4_clk>, <&s4_clk>;
529 #clock-cells = <1>;
64530fc2 530 clock-indices = <
1e851538
SH
531 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
532 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
533 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
534 >;
535 clock-output-names =
536 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
537 "mmc1", "mmc0";
538 };
539 };
c58a1545 540};