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ARM: dts: am43xx-clocks: use ti, fixed-factor-clock for dpll_per_clkdcoldo
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / r8a7790.dtsi
CommitLineData
0468b2d6
MD		 1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
d8913c67
SS		 4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2014 Cogent Embedded Inc.
0468b2d6
MD		 6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
22a1f595 12#include <dt-bindings/clock/r8a7790-clock.h>
5f75e73c
LP		 13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
0468b2d6
MD		 16/ {
17 compatible = "renesas,r8a7790";
18 interrupt-parent = <&gic>;
8585deb1
TY		 19 #address-cells = <2>;
20 #size-cells = <2>;
0468b2d6 21
6b1d7c68
WS		 22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 };
28
0468b2d6
MD		 29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a15";
36 reg = <0>;
37 clock-frequency = <1300000000>;
38 };
c1f95979
MD		 39
40 cpu1: cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <1>;
44 clock-frequency = <1300000000>;
45 };
46
47 cpu2: cpu@2 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <2>;
51 clock-frequency = <1300000000>;
52 };
53
54 cpu3: cpu@3 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a15";
57 reg = <3>;
58 clock-frequency = <1300000000>;
59 };
2007e74c
MD		 60
61 cpu4: cpu@4 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a7";
64 reg = <0x100>;
65 clock-frequency = <780000000>;
66 };
67
68 cpu5: cpu@5 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a7";
71 reg = <0x101>;
72 clock-frequency = <780000000>;
73 };
74
75 cpu6: cpu@6 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a7";
78 reg = <0x102>;
79 clock-frequency = <780000000>;
80 };
81
82 cpu7: cpu@7 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a7";
85 reg = <0x103>;
86 clock-frequency = <780000000>;
87 };
0468b2d6
MD		 88 };
89
90 gic: interrupt-controller@f1001000 {
91 compatible = "arm,cortex-a15-gic";
92 #interrupt-cells = <3>;
93 #address-cells = <0>;
94 interrupt-controller;
8585deb1
TY		 95 reg = <0 0xf1001000 0 0x1000>,
96 <0 0xf1002000 0 0x1000>,
97 <0 0xf1004000 0 0x2000>,
98 <0 0xf1006000 0 0x2000>;
5f75e73c 99 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0468b2d6
MD		 100 };
101
23de2278 102 gpio0: gpio@e6050000 {
f98e10c8 103 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 104 reg = <0 0xe6050000 0 0x50>;
5f75e73c 105 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 106 #gpio-cells = <2>;
107 gpio-controller;
108 gpio-ranges = <&pfc 0 0 32>;
109 #interrupt-cells = <2>;
110 interrupt-controller;
111 };
112
23de2278 113 gpio1: gpio@e6051000 {
f98e10c8 114 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 115 reg = <0 0xe6051000 0 0x50>;
5f75e73c 116 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 117 #gpio-cells = <2>;
118 gpio-controller;
119 gpio-ranges = <&pfc 0 32 32>;
120 #interrupt-cells = <2>;
121 interrupt-controller;
122 };
123
23de2278 124 gpio2: gpio@e6052000 {
f98e10c8 125 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 126 reg = <0 0xe6052000 0 0x50>;
5f75e73c 127 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 128 #gpio-cells = <2>;
129 gpio-controller;
130 gpio-ranges = <&pfc 0 64 32>;
131 #interrupt-cells = <2>;
132 interrupt-controller;
133 };
134
23de2278 135 gpio3: gpio@e6053000 {
f98e10c8 136 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 137 reg = <0 0xe6053000 0 0x50>;
5f75e73c 138 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 139 #gpio-cells = <2>;
140 gpio-controller;
141 gpio-ranges = <&pfc 0 96 32>;
142 #interrupt-cells = <2>;
143 interrupt-controller;
144 };
145
23de2278 146 gpio4: gpio@e6054000 {
f98e10c8 147 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 148 reg = <0 0xe6054000 0 0x50>;
5f75e73c 149 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 150 #gpio-cells = <2>;
151 gpio-controller;
152 gpio-ranges = <&pfc 0 128 32>;
153 #interrupt-cells = <2>;
154 interrupt-controller;
155 };
156
23de2278 157 gpio5: gpio@e6055000 {
f98e10c8 158 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 159 reg = <0 0xe6055000 0 0x50>;
5f75e73c 160 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 161 #gpio-cells = <2>;
162 gpio-controller;
163 gpio-ranges = <&pfc 0 160 32>;
164 #interrupt-cells = <2>;
165 interrupt-controller;
166 };
167
03e2f56b
MD		 168 thermal@e61f0000 {
169 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
170 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
03e2f56b 171 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
d3a439db 172 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
03e2f56b
MD		 173 };
174
0468b2d6
MD		 175 timer {
176 compatible = "arm,armv7-timer";
5f75e73c
LP		 177 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
178 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
179 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
180 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0468b2d6 181 };
8f5ec0a5
MD		 182
183 irqc0: interrupt-controller@e61c0000 {
220fc352 184 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
8f5ec0a5
MD		 185 #interrupt-cells = <2>;
186 interrupt-controller;
8585deb1 187 reg = <0 0xe61c0000 0 0x200>;
5f75e73c
LP		 188 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
189 <0 1 IRQ_TYPE_LEVEL_HIGH>,
190 <0 2 IRQ_TYPE_LEVEL_HIGH>,
191 <0 3 IRQ_TYPE_LEVEL_HIGH>;
8f5ec0a5 192 };
8c9b1aa4 193
edd2b9f4
GL		 194 i2c0: i2c@e6508000 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "renesas,i2c-r8a7790";
198 reg = <0 0xe6508000 0 0x40>;
5f75e73c 199 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
2450badf 200 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
edd2b9f4
GL		 201 status = "disabled";
202 };
203
204 i2c1: i2c@e6518000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "renesas,i2c-r8a7790";
208 reg = <0 0xe6518000 0 0x40>;
5f75e73c 209 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
2450badf 210 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
edd2b9f4
GL		 211 status = "disabled";
212 };
213
214 i2c2: i2c@e6530000 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "renesas,i2c-r8a7790";
218 reg = <0 0xe6530000 0 0x40>;
5f75e73c 219 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
2450badf 220 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
edd2b9f4
GL		 221 status = "disabled";
222 };
223
224 i2c3: i2c@e6540000 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "renesas,i2c-r8a7790";
228 reg = <0 0xe6540000 0 0x40>;
5f75e73c 229 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
2450badf 230 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
edd2b9f4
GL		 231 status = "disabled";
232 };
233
8c9b1aa4 234 mmcif0: mmcif@ee200000 {
063e8560 235 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 236 reg = <0 0xee200000 0 0x80>;
5f75e73c 237 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 238 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
8c9b1aa4
GL		 239 reg-io-width = <4>;
240 status = "disabled";
241 };
242
b718aa44 243 mmcif1: mmc@ee220000 {
063e8560 244 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 245 reg = <0 0xee220000 0 0x80>;
5f75e73c 246 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 247 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
8c9b1aa4
GL		 248 reg-io-width = <4>;
249 status = "disabled";
250 };
251
9694c778
LP		 252 pfc: pfc@e6060000 {
253 compatible = "renesas,pfc-r8a7790";
254 reg = <0 0xe6060000 0 0x250>;
255 };
55689bfa 256
b718aa44 257 sdhi0: sd@ee100000 {
df1d0584 258 compatible = "renesas,sdhi-r8a7790";
d721a15c 259 reg = <0 0xee100000 0 0x200>;
5f75e73c 260 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 261 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
8c9b1aa4
GL		 262 cap-sd-highspeed;
263 status = "disabled";
264 };
265
b718aa44 266 sdhi1: sd@ee120000 {
df1d0584 267 compatible = "renesas,sdhi-r8a7790";
d721a15c 268 reg = <0 0xee120000 0 0x200>;
5f75e73c 269 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 270 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
8c9b1aa4
GL		 271 cap-sd-highspeed;
272 status = "disabled";
273 };
274
b718aa44 275 sdhi2: sd@ee140000 {
df1d0584 276 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 277 reg = <0 0xee140000 0 0x100>;
5f75e73c 278 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 279 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
8c9b1aa4
GL		 280 cap-sd-highspeed;
281 status = "disabled";
282 };
283
b718aa44 284 sdhi3: sd@ee160000 {
df1d0584 285 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 286 reg = <0 0xee160000 0 0x100>;
5f75e73c 287 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 288 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
8c9b1aa4
GL		 289 cap-sd-highspeed;
290 status = "disabled";
291 };
22a1f595 292
597af20f 293 scifa0: serial@e6c40000 {
59d2b517 294 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 295 reg = <0 0xe6c40000 0 64>;
1f4c745b 296 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 297 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
298 clock-names = "sci_ick";
299 status = "disabled";
300 };
301
302 scifa1: serial@e6c50000 {
59d2b517 303 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 304 reg = <0 0xe6c50000 0 64>;
1f4c745b 305 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 306 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
307 clock-names = "sci_ick";
308 status = "disabled";
309 };
310
311 scifa2: serial@e6c60000 {
59d2b517 312 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 313 reg = <0 0xe6c60000 0 64>;
1f4c745b 314 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 315 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
316 clock-names = "sci_ick";
317 status = "disabled";
318 };
319
320 scifb0: serial@e6c20000 {
59d2b517 321 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 322 reg = <0 0xe6c20000 0 64>;
1f4c745b 323 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 324 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
325 clock-names = "sci_ick";
326 status = "disabled";
327 };
328
329 scifb1: serial@e6c30000 {
59d2b517 330 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 331 reg = <0 0xe6c30000 0 64>;
1f4c745b 332 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 333 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
334 clock-names = "sci_ick";
335 status = "disabled";
336 };
337
338 scifb2: serial@e6ce0000 {
59d2b517 339 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 340 reg = <0 0xe6ce0000 0 64>;
1f4c745b 341 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 342 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
343 clock-names = "sci_ick";
344 status = "disabled";
345 };
346
347 scif0: serial@e6e60000 {
59d2b517 348 compatible = "renesas,scif-r8a7790", "renesas,scif";
597af20f 349 reg = <0 0xe6e60000 0 64>;
1f4c745b 350 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 351 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
352 clock-names = "sci_ick";
353 status = "disabled";
354 };
355
356 scif1: serial@e6e68000 {
59d2b517 357 compatible = "renesas,scif-r8a7790", "renesas,scif";
597af20f 358 reg = <0 0xe6e68000 0 64>;
1f4c745b 359 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 360 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
361 clock-names = "sci_ick";
362 status = "disabled";
363 };
364
365 hscif0: serial@e62c0000 {
59d2b517 366 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
597af20f 367 reg = <0 0xe62c0000 0 96>;
1f4c745b 368 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 369 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
370 clock-names = "sci_ick";
371 status = "disabled";
372 };
373
374 hscif1: serial@e62c8000 {
59d2b517 375 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
597af20f 376 reg = <0 0xe62c8000 0 96>;
1f4c745b 377 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 378 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
379 clock-names = "sci_ick";
380 status = "disabled";
381 };
382
d8913c67
SS		 383 ether: ethernet@ee700000 {
384 compatible = "renesas,ether-r8a7790";
385 reg = <0 0xee700000 0 0x400>;
386 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
388 phy-mode = "rmii";
389 #address-cells = <1>;
390 #size-cells = <0>;
391 status = "disabled";
392 };
393
cde630f7
VB		 394 sata0: sata@ee300000 {
395 compatible = "renesas,sata-r8a7790";
396 reg = <0 0xee300000 0 0x2000>;
cde630f7
VB		 397 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
399 status = "disabled";
400 };
401
402 sata1: sata@ee500000 {
403 compatible = "renesas,sata-r8a7790";
404 reg = <0 0xee500000 0 0x2000>;
cde630f7
VB		 405 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
407 status = "disabled";
408 };
409
22a1f595
LP		 410 clocks {
411 #address-cells = <2>;
412 #size-cells = <2>;
413 ranges;
414
415 /* External root clock */
416 extal_clk: extal_clk {
417 compatible = "fixed-clock";
418 #clock-cells = <0>;
419 /* This value must be overriden by the board. */
420 clock-frequency = <0>;
421 clock-output-names = "extal";
422 };
423
c7c2ec3a
KM		 424 /*
425 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
426 * default. Boards that provide audio clocks should override them.
427 */
428 audio_clk_a: audio_clk_a {
429 compatible = "fixed-clock";
430 #clock-cells = <0>;
431 clock-frequency = <0>;
432 clock-output-names = "audio_clk_a";
433 };
434 audio_clk_b: audio_clk_b {
435 compatible = "fixed-clock";
436 #clock-cells = <0>;
437 clock-frequency = <0>;
438 clock-output-names = "audio_clk_b";
439 };
440 audio_clk_c: audio_clk_c {
441 compatible = "fixed-clock";
442 #clock-cells = <0>;
443 clock-frequency = <0>;
444 clock-output-names = "audio_clk_c";
445 };
446
22a1f595
LP		 447 /* Special CPG clocks */
448 cpg_clocks: cpg_clocks@e6150000 {
449 compatible = "renesas,r8a7790-cpg-clocks",
450 "renesas,rcar-gen2-cpg-clocks";
451 reg = <0 0xe6150000 0 0x1000>;
452 clocks = <&extal_clk>;
453 #clock-cells = <1>;
454 clock-output-names = "main", "pll0", "pll1", "pll3",
455 "lb", "qspi", "sdh", "sd0", "sd1",
456 "z";
457 };
458
459 /* Variable factor clocks */
460 sd2_clk: sd2_clk@e6150078 {
461 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
462 reg = <0 0xe6150078 0 4>;
463 clocks = <&pll1_div2_clk>;
464 #clock-cells = <0>;
465 clock-output-names = "sd2";
466 };
467 sd3_clk: sd3_clk@e615007c {
468 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
469 reg = <0 0xe615007c 0 4>;
470 clocks = <&pll1_div2_clk>;
471 #clock-cells = <0>;
472 clock-output-names = "sd3";
473 };
474 mmc0_clk: mmc0_clk@e6150240 {
475 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
476 reg = <0 0xe6150240 0 4>;
477 clocks = <&pll1_div2_clk>;
478 #clock-cells = <0>;
479 clock-output-names = "mmc0";
480 };
481 mmc1_clk: mmc1_clk@e6150244 {
482 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
483 reg = <0 0xe6150244 0 4>;
484 clocks = <&pll1_div2_clk>;
485 #clock-cells = <0>;
486 clock-output-names = "mmc1";
487 };
488 ssp_clk: ssp_clk@e6150248 {
489 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
490 reg = <0 0xe6150248 0 4>;
491 clocks = <&pll1_div2_clk>;
492 #clock-cells = <0>;
493 clock-output-names = "ssp";
494 };
495 ssprs_clk: ssprs_clk@e615024c {
496 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
497 reg = <0 0xe615024c 0 4>;
498 clocks = <&pll1_div2_clk>;
499 #clock-cells = <0>;
500 clock-output-names = "ssprs";
501 };
502
503 /* Fixed factor clocks */
504 pll1_div2_clk: pll1_div2_clk {
505 compatible = "fixed-factor-clock";
506 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
507 #clock-cells = <0>;
508 clock-div = <2>;
509 clock-mult = <1>;
510 clock-output-names = "pll1_div2";
511 };
512 z2_clk: z2_clk {
513 compatible = "fixed-factor-clock";
514 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
515 #clock-cells = <0>;
516 clock-div = <2>;
517 clock-mult = <1>;
518 clock-output-names = "z2";
519 };
520 zg_clk: zg_clk {
521 compatible = "fixed-factor-clock";
522 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
523 #clock-cells = <0>;
524 clock-div = <3>;
525 clock-mult = <1>;
526 clock-output-names = "zg";
527 };
528 zx_clk: zx_clk {
529 compatible = "fixed-factor-clock";
530 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
531 #clock-cells = <0>;
532 clock-div = <3>;
533 clock-mult = <1>;
534 clock-output-names = "zx";
535 };
536 zs_clk: zs_clk {
537 compatible = "fixed-factor-clock";
538 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
539 #clock-cells = <0>;
540 clock-div = <6>;
541 clock-mult = <1>;
542 clock-output-names = "zs";
543 };
544 hp_clk: hp_clk {
545 compatible = "fixed-factor-clock";
546 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
547 #clock-cells = <0>;
548 clock-div = <12>;
549 clock-mult = <1>;
550 clock-output-names = "hp";
551 };
552 i_clk: i_clk {
553 compatible = "fixed-factor-clock";
554 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
555 #clock-cells = <0>;
556 clock-div = <2>;
557 clock-mult = <1>;
558 clock-output-names = "i";
559 };
560 b_clk: b_clk {
561 compatible = "fixed-factor-clock";
562 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
563 #clock-cells = <0>;
564 clock-div = <12>;
565 clock-mult = <1>;
566 clock-output-names = "b";
567 };
568 p_clk: p_clk {
569 compatible = "fixed-factor-clock";
570 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
571 #clock-cells = <0>;
572 clock-div = <24>;
573 clock-mult = <1>;
574 clock-output-names = "p";
575 };
576 cl_clk: cl_clk {
577 compatible = "fixed-factor-clock";
578 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
579 #clock-cells = <0>;
580 clock-div = <48>;
581 clock-mult = <1>;
582 clock-output-names = "cl";
583 };
584 m2_clk: m2_clk {
585 compatible = "fixed-factor-clock";
586 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
587 #clock-cells = <0>;
588 clock-div = <8>;
589 clock-mult = <1>;
590 clock-output-names = "m2";
591 };
592 imp_clk: imp_clk {
593 compatible = "fixed-factor-clock";
594 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
595 #clock-cells = <0>;
596 clock-div = <4>;
597 clock-mult = <1>;
598 clock-output-names = "imp";
599 };
600 rclk_clk: rclk_clk {
601 compatible = "fixed-factor-clock";
602 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
603 #clock-cells = <0>;
604 clock-div = <(48 * 1024)>;
605 clock-mult = <1>;
606 clock-output-names = "rclk";
607 };
608 oscclk_clk: oscclk_clk {
609 compatible = "fixed-factor-clock";
610 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
611 #clock-cells = <0>;
612 clock-div = <(12 * 1024)>;
613 clock-mult = <1>;
614 clock-output-names = "oscclk";
615 };
616 zb3_clk: zb3_clk {
617 compatible = "fixed-factor-clock";
618 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
619 #clock-cells = <0>;
620 clock-div = <4>;
621 clock-mult = <1>;
622 clock-output-names = "zb3";
623 };
624 zb3d2_clk: zb3d2_clk {
625 compatible = "fixed-factor-clock";
626 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
627 #clock-cells = <0>;
628 clock-div = <8>;
629 clock-mult = <1>;
630 clock-output-names = "zb3d2";
631 };
632 ddr_clk: ddr_clk {
633 compatible = "fixed-factor-clock";
634 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
635 #clock-cells = <0>;
636 clock-div = <8>;
637 clock-mult = <1>;
638 clock-output-names = "ddr";
639 };
640 mp_clk: mp_clk {
641 compatible = "fixed-factor-clock";
642 clocks = <&pll1_div2_clk>;
643 #clock-cells = <0>;
644 clock-div = <15>;
645 clock-mult = <1>;
646 clock-output-names = "mp";
647 };
648 cp_clk: cp_clk {
649 compatible = "fixed-factor-clock";
650 clocks = <&extal_clk>;
651 #clock-cells = <0>;
652 clock-div = <2>;
653 clock-mult = <1>;
654 clock-output-names = "cp";
655 };
656
657 /* Gate clocks */
9d90951a
LP		 658 mstp0_clks: mstp0_clks@e6150130 {
659 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
660 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
661 clocks = <&mp_clk>;
662 #clock-cells = <1>;
663 renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
664 clock-output-names = "msiof0";
665 };
22a1f595
LP		 666 mstp1_clks: mstp1_clks@e6150134 {
667 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
668 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
669 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
670 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
671 <&zs_clk>;
672 #clock-cells = <1>;
673 renesas,clock-indices = <
674 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
675 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
676 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
677 >;
678 clock-output-names =
679 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
680 "vsp1-du0", "vsp1-rt", "vsp1-sy";
681 };
682 mstp2_clks: mstp2_clks@e6150138 {
683 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
684 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
685 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
9d90951a 686 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
22a1f595
LP		 687 #clock-cells = <1>;
688 renesas,clock-indices = <
689 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
9d90951a
LP		 690 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
691 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
22a1f595
LP		 692 >;
693 clock-output-names =
9d90951a
LP		 694 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
695 "scifb1", "msiof1", "msiof3", "scifb2";
22a1f595
LP		 696 };
697 mstp3_clks: mstp3_clks@e615013c {
698 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
699 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
700 clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
701 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
702 <&mmc0_clk>, <&rclk_clk>;
703 #clock-cells = <1>;
704 renesas,clock-indices = <
705 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
706 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
707 R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
708 >;
709 clock-output-names =
710 "tpu0", "mmcif1", "sdhi3", "sdhi2",
711 "sdhi1", "sdhi0", "mmcif0", "cmt1";
712 };
713 mstp5_clks: mstp5_clks@e6150144 {
714 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
715 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
716 clocks = <&extal_clk>, <&p_clk>;
717 #clock-cells = <1>;
718 renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
719 clock-output-names = "thermal", "pwm";
720 };
721 mstp7_clks: mstp7_clks@e615014c {
722 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
723 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
724 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
725 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
726 <&zx_clk>;
727 #clock-cells = <1>;
728 renesas,clock-indices = <
729 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
730 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
731 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
732 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
733 >;
734 clock-output-names =
735 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
736 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
737 };
738 mstp8_clks: mstp8_clks@e6150990 {
739 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
740 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
bccccc3d
LP		 741 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
742 <&zs_clk>, <&zs_clk>;
22a1f595 743 #clock-cells = <1>;
3f2beaa9
LP		 744 renesas,clock-indices = <
745 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
bccccc3d
LP		 746 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
747 R8A7790_CLK_SATA0
3f2beaa9 748 >;
bccccc3d
LP		 749 clock-output-names =
750 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
22a1f595
LP		 751 };
752 mstp9_clks: mstp9_clks@e6150994 {
753 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
754 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
91b56ca1
LP		 755 clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
756 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
22a1f595
LP		 757 #clock-cells = <1>;
758 renesas,clock-indices = <
91b56ca1
LP		 759 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
760 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
761 R8A7790_CLK_I2C0
22a1f595 762 >;
91b56ca1
LP		 763 clock-output-names =
764 "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
22a1f595
LP		 765 };
766 };
7053e134
GU		 767
768 spi: spi@e6b10000 {
769 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
770 reg = <0 0xe6b10000 0 0x2c>;
7053e134
GU		 771 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
773 num-cs = <1>;
774 #address-cells = <1>;
775 #size-cells = <0>;
776 status = "disabled";
777 };
0468b2d6 778};
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