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Commit | Line | Data |
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0468b2d6 MD |
1 | /* |
2 | * Device Tree Source for the r8a7790 SoC | |
3 | * | |
d8913c67 SS |
4 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
5 | * Copyright (C) 2014 Cogent Embedded Inc. | |
0468b2d6 MD |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
22a1f595 | 12 | #include <dt-bindings/clock/r8a7790-clock.h> |
5f75e73c LP |
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
14 | #include <dt-bindings/interrupt-controller/irq.h> | |
15 | ||
0468b2d6 MD |
16 | / { |
17 | compatible = "renesas,r8a7790"; | |
18 | interrupt-parent = <&gic>; | |
8585deb1 TY |
19 | #address-cells = <2>; |
20 | #size-cells = <2>; | |
0468b2d6 | 21 | |
6b1d7c68 WS |
22 | aliases { |
23 | i2c0 = &i2c0; | |
24 | i2c1 = &i2c1; | |
25 | i2c2 = &i2c2; | |
26 | i2c3 = &i2c3; | |
05f39916 WS |
27 | i2c4 = &iic0; |
28 | i2c5 = &iic1; | |
29 | i2c6 = &iic2; | |
30 | i2c7 = &iic3; | |
fad6d45c | 31 | spi0 = &qspi; |
ae8a6146 GU |
32 | spi1 = &msiof0; |
33 | spi2 = &msiof1; | |
34 | spi3 = &msiof2; | |
35 | spi4 = &msiof3; | |
6b1d7c68 WS |
36 | }; |
37 | ||
0468b2d6 MD |
38 | cpus { |
39 | #address-cells = <1>; | |
40 | #size-cells = <0>; | |
41 | ||
42 | cpu0: cpu@0 { | |
43 | device_type = "cpu"; | |
44 | compatible = "arm,cortex-a15"; | |
45 | reg = <0>; | |
46 | clock-frequency = <1300000000>; | |
47 | }; | |
c1f95979 MD |
48 | |
49 | cpu1: cpu@1 { | |
50 | device_type = "cpu"; | |
51 | compatible = "arm,cortex-a15"; | |
52 | reg = <1>; | |
53 | clock-frequency = <1300000000>; | |
54 | }; | |
55 | ||
56 | cpu2: cpu@2 { | |
57 | device_type = "cpu"; | |
58 | compatible = "arm,cortex-a15"; | |
59 | reg = <2>; | |
60 | clock-frequency = <1300000000>; | |
61 | }; | |
62 | ||
63 | cpu3: cpu@3 { | |
64 | device_type = "cpu"; | |
65 | compatible = "arm,cortex-a15"; | |
66 | reg = <3>; | |
67 | clock-frequency = <1300000000>; | |
68 | }; | |
2007e74c MD |
69 | |
70 | cpu4: cpu@4 { | |
71 | device_type = "cpu"; | |
72 | compatible = "arm,cortex-a7"; | |
73 | reg = <0x100>; | |
74 | clock-frequency = <780000000>; | |
75 | }; | |
76 | ||
77 | cpu5: cpu@5 { | |
78 | device_type = "cpu"; | |
79 | compatible = "arm,cortex-a7"; | |
80 | reg = <0x101>; | |
81 | clock-frequency = <780000000>; | |
82 | }; | |
83 | ||
84 | cpu6: cpu@6 { | |
85 | device_type = "cpu"; | |
86 | compatible = "arm,cortex-a7"; | |
87 | reg = <0x102>; | |
88 | clock-frequency = <780000000>; | |
89 | }; | |
90 | ||
91 | cpu7: cpu@7 { | |
92 | device_type = "cpu"; | |
93 | compatible = "arm,cortex-a7"; | |
94 | reg = <0x103>; | |
95 | clock-frequency = <780000000>; | |
96 | }; | |
0468b2d6 MD |
97 | }; |
98 | ||
99 | gic: interrupt-controller@f1001000 { | |
100 | compatible = "arm,cortex-a15-gic"; | |
101 | #interrupt-cells = <3>; | |
102 | #address-cells = <0>; | |
103 | interrupt-controller; | |
8585deb1 TY |
104 | reg = <0 0xf1001000 0 0x1000>, |
105 | <0 0xf1002000 0 0x1000>, | |
106 | <0 0xf1004000 0 0x2000>, | |
107 | <0 0xf1006000 0 0x2000>; | |
5f75e73c | 108 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
0468b2d6 MD |
109 | }; |
110 | ||
23de2278 | 111 | gpio0: gpio@e6050000 { |
f98e10c8 | 112 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 113 | reg = <0 0xe6050000 0 0x50>; |
5f75e73c | 114 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
115 | #gpio-cells = <2>; |
116 | gpio-controller; | |
117 | gpio-ranges = <&pfc 0 0 32>; | |
118 | #interrupt-cells = <2>; | |
119 | interrupt-controller; | |
81f6883f | 120 | clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; |
f98e10c8 LP |
121 | }; |
122 | ||
23de2278 | 123 | gpio1: gpio@e6051000 { |
f98e10c8 | 124 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 125 | reg = <0 0xe6051000 0 0x50>; |
5f75e73c | 126 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
127 | #gpio-cells = <2>; |
128 | gpio-controller; | |
129 | gpio-ranges = <&pfc 0 32 32>; | |
130 | #interrupt-cells = <2>; | |
131 | interrupt-controller; | |
81f6883f | 132 | clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; |
f98e10c8 LP |
133 | }; |
134 | ||
23de2278 | 135 | gpio2: gpio@e6052000 { |
f98e10c8 | 136 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 137 | reg = <0 0xe6052000 0 0x50>; |
5f75e73c | 138 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
139 | #gpio-cells = <2>; |
140 | gpio-controller; | |
141 | gpio-ranges = <&pfc 0 64 32>; | |
142 | #interrupt-cells = <2>; | |
143 | interrupt-controller; | |
81f6883f | 144 | clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; |
f98e10c8 LP |
145 | }; |
146 | ||
23de2278 | 147 | gpio3: gpio@e6053000 { |
f98e10c8 | 148 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 149 | reg = <0 0xe6053000 0 0x50>; |
5f75e73c | 150 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
151 | #gpio-cells = <2>; |
152 | gpio-controller; | |
153 | gpio-ranges = <&pfc 0 96 32>; | |
154 | #interrupt-cells = <2>; | |
155 | interrupt-controller; | |
81f6883f | 156 | clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; |
f98e10c8 LP |
157 | }; |
158 | ||
23de2278 | 159 | gpio4: gpio@e6054000 { |
f98e10c8 | 160 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 161 | reg = <0 0xe6054000 0 0x50>; |
5f75e73c | 162 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
163 | #gpio-cells = <2>; |
164 | gpio-controller; | |
165 | gpio-ranges = <&pfc 0 128 32>; | |
166 | #interrupt-cells = <2>; | |
167 | interrupt-controller; | |
81f6883f | 168 | clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; |
f98e10c8 LP |
169 | }; |
170 | ||
23de2278 | 171 | gpio5: gpio@e6055000 { |
f98e10c8 | 172 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 173 | reg = <0 0xe6055000 0 0x50>; |
5f75e73c | 174 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
175 | #gpio-cells = <2>; |
176 | gpio-controller; | |
177 | gpio-ranges = <&pfc 0 160 32>; | |
178 | #interrupt-cells = <2>; | |
179 | interrupt-controller; | |
81f6883f | 180 | clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; |
f98e10c8 LP |
181 | }; |
182 | ||
03e2f56b MD |
183 | thermal@e61f0000 { |
184 | compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; | |
185 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | |
03e2f56b | 186 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
d3a439db | 187 | clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; |
03e2f56b MD |
188 | }; |
189 | ||
0468b2d6 MD |
190 | timer { |
191 | compatible = "arm,armv7-timer"; | |
5f75e73c LP |
192 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
193 | <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
194 | <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
195 | <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
0468b2d6 | 196 | }; |
8f5ec0a5 MD |
197 | |
198 | irqc0: interrupt-controller@e61c0000 { | |
220fc352 | 199 | compatible = "renesas,irqc-r8a7790", "renesas,irqc"; |
8f5ec0a5 MD |
200 | #interrupt-cells = <2>; |
201 | interrupt-controller; | |
8585deb1 | 202 | reg = <0 0xe61c0000 0 0x200>; |
5f75e73c LP |
203 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
204 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
205 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
206 | <0 3 IRQ_TYPE_LEVEL_HIGH>; | |
8f5ec0a5 | 207 | }; |
8c9b1aa4 | 208 | |
edd2b9f4 GL |
209 | i2c0: i2c@e6508000 { |
210 | #address-cells = <1>; | |
211 | #size-cells = <0>; | |
212 | compatible = "renesas,i2c-r8a7790"; | |
213 | reg = <0 0xe6508000 0 0x40>; | |
5f75e73c | 214 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; |
2450badf | 215 | clocks = <&mstp9_clks R8A7790_CLK_I2C0>; |
edd2b9f4 GL |
216 | status = "disabled"; |
217 | }; | |
218 | ||
219 | i2c1: i2c@e6518000 { | |
220 | #address-cells = <1>; | |
221 | #size-cells = <0>; | |
222 | compatible = "renesas,i2c-r8a7790"; | |
223 | reg = <0 0xe6518000 0 0x40>; | |
5f75e73c | 224 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; |
2450badf | 225 | clocks = <&mstp9_clks R8A7790_CLK_I2C1>; |
edd2b9f4 GL |
226 | status = "disabled"; |
227 | }; | |
228 | ||
229 | i2c2: i2c@e6530000 { | |
230 | #address-cells = <1>; | |
231 | #size-cells = <0>; | |
232 | compatible = "renesas,i2c-r8a7790"; | |
233 | reg = <0 0xe6530000 0 0x40>; | |
5f75e73c | 234 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; |
2450badf | 235 | clocks = <&mstp9_clks R8A7790_CLK_I2C2>; |
edd2b9f4 GL |
236 | status = "disabled"; |
237 | }; | |
238 | ||
239 | i2c3: i2c@e6540000 { | |
240 | #address-cells = <1>; | |
241 | #size-cells = <0>; | |
242 | compatible = "renesas,i2c-r8a7790"; | |
243 | reg = <0 0xe6540000 0 0x40>; | |
5f75e73c | 244 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; |
2450badf | 245 | clocks = <&mstp9_clks R8A7790_CLK_I2C3>; |
edd2b9f4 GL |
246 | status = "disabled"; |
247 | }; | |
248 | ||
05f39916 WS |
249 | iic0: i2c@e6500000 { |
250 | #address-cells = <1>; | |
251 | #size-cells = <0>; | |
252 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
253 | reg = <0 0xe6500000 0 0x425>; | |
254 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; | |
255 | clocks = <&mstp3_clks R8A7790_CLK_IIC0>; | |
256 | status = "disabled"; | |
257 | }; | |
258 | ||
259 | iic1: i2c@e6510000 { | |
260 | #address-cells = <1>; | |
261 | #size-cells = <0>; | |
262 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
263 | reg = <0 0xe6510000 0 0x425>; | |
264 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; | |
265 | clocks = <&mstp3_clks R8A7790_CLK_IIC1>; | |
266 | status = "disabled"; | |
267 | }; | |
268 | ||
269 | iic2: i2c@e6520000 { | |
270 | #address-cells = <1>; | |
271 | #size-cells = <0>; | |
272 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
273 | reg = <0 0xe6520000 0 0x425>; | |
274 | interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; | |
275 | clocks = <&mstp3_clks R8A7790_CLK_IIC2>; | |
276 | status = "disabled"; | |
277 | }; | |
278 | ||
279 | iic3: i2c@e60b0000 { | |
280 | #address-cells = <1>; | |
281 | #size-cells = <0>; | |
282 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
283 | reg = <0 0xe60b0000 0 0x425>; | |
284 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; | |
285 | clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; | |
286 | status = "disabled"; | |
287 | }; | |
288 | ||
8c9b1aa4 | 289 | mmcif0: mmcif@ee200000 { |
063e8560 | 290 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
8c9b1aa4 | 291 | reg = <0 0xee200000 0 0x80>; |
5f75e73c | 292 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 293 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; |
8c9b1aa4 GL |
294 | reg-io-width = <4>; |
295 | status = "disabled"; | |
296 | }; | |
297 | ||
b718aa44 | 298 | mmcif1: mmc@ee220000 { |
063e8560 | 299 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
8c9b1aa4 | 300 | reg = <0 0xee220000 0 0x80>; |
5f75e73c | 301 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 302 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; |
8c9b1aa4 GL |
303 | reg-io-width = <4>; |
304 | status = "disabled"; | |
305 | }; | |
306 | ||
9694c778 LP |
307 | pfc: pfc@e6060000 { |
308 | compatible = "renesas,pfc-r8a7790"; | |
309 | reg = <0 0xe6060000 0 0x250>; | |
310 | }; | |
55689bfa | 311 | |
b718aa44 | 312 | sdhi0: sd@ee100000 { |
df1d0584 | 313 | compatible = "renesas,sdhi-r8a7790"; |
d721a15c | 314 | reg = <0 0xee100000 0 0x200>; |
5f75e73c | 315 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 316 | clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; |
8c9b1aa4 GL |
317 | cap-sd-highspeed; |
318 | status = "disabled"; | |
319 | }; | |
320 | ||
b718aa44 | 321 | sdhi1: sd@ee120000 { |
df1d0584 | 322 | compatible = "renesas,sdhi-r8a7790"; |
d721a15c | 323 | reg = <0 0xee120000 0 0x200>; |
5f75e73c | 324 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 325 | clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; |
8c9b1aa4 GL |
326 | cap-sd-highspeed; |
327 | status = "disabled"; | |
328 | }; | |
329 | ||
b718aa44 | 330 | sdhi2: sd@ee140000 { |
df1d0584 | 331 | compatible = "renesas,sdhi-r8a7790"; |
8c9b1aa4 | 332 | reg = <0 0xee140000 0 0x100>; |
5f75e73c | 333 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 334 | clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; |
8c9b1aa4 GL |
335 | cap-sd-highspeed; |
336 | status = "disabled"; | |
337 | }; | |
338 | ||
b718aa44 | 339 | sdhi3: sd@ee160000 { |
df1d0584 | 340 | compatible = "renesas,sdhi-r8a7790"; |
8c9b1aa4 | 341 | reg = <0 0xee160000 0 0x100>; |
5f75e73c | 342 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 343 | clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; |
8c9b1aa4 GL |
344 | cap-sd-highspeed; |
345 | status = "disabled"; | |
346 | }; | |
22a1f595 | 347 | |
597af20f | 348 | scifa0: serial@e6c40000 { |
59d2b517 | 349 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
597af20f | 350 | reg = <0 0xe6c40000 0 64>; |
1f4c745b | 351 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
352 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; |
353 | clock-names = "sci_ick"; | |
354 | status = "disabled"; | |
355 | }; | |
356 | ||
357 | scifa1: serial@e6c50000 { | |
59d2b517 | 358 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
597af20f | 359 | reg = <0 0xe6c50000 0 64>; |
1f4c745b | 360 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
361 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; |
362 | clock-names = "sci_ick"; | |
363 | status = "disabled"; | |
364 | }; | |
365 | ||
366 | scifa2: serial@e6c60000 { | |
59d2b517 | 367 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
597af20f | 368 | reg = <0 0xe6c60000 0 64>; |
1f4c745b | 369 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
370 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; |
371 | clock-names = "sci_ick"; | |
372 | status = "disabled"; | |
373 | }; | |
374 | ||
375 | scifb0: serial@e6c20000 { | |
59d2b517 | 376 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
597af20f | 377 | reg = <0 0xe6c20000 0 64>; |
1f4c745b | 378 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
379 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; |
380 | clock-names = "sci_ick"; | |
381 | status = "disabled"; | |
382 | }; | |
383 | ||
384 | scifb1: serial@e6c30000 { | |
59d2b517 | 385 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
597af20f | 386 | reg = <0 0xe6c30000 0 64>; |
1f4c745b | 387 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
388 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; |
389 | clock-names = "sci_ick"; | |
390 | status = "disabled"; | |
391 | }; | |
392 | ||
393 | scifb2: serial@e6ce0000 { | |
59d2b517 | 394 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
597af20f | 395 | reg = <0 0xe6ce0000 0 64>; |
1f4c745b | 396 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
397 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; |
398 | clock-names = "sci_ick"; | |
399 | status = "disabled"; | |
400 | }; | |
401 | ||
402 | scif0: serial@e6e60000 { | |
59d2b517 | 403 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
597af20f | 404 | reg = <0 0xe6e60000 0 64>; |
1f4c745b | 405 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
406 | clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; |
407 | clock-names = "sci_ick"; | |
408 | status = "disabled"; | |
409 | }; | |
410 | ||
411 | scif1: serial@e6e68000 { | |
59d2b517 | 412 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
597af20f | 413 | reg = <0 0xe6e68000 0 64>; |
1f4c745b | 414 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
415 | clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; |
416 | clock-names = "sci_ick"; | |
417 | status = "disabled"; | |
418 | }; | |
419 | ||
420 | hscif0: serial@e62c0000 { | |
59d2b517 | 421 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
597af20f | 422 | reg = <0 0xe62c0000 0 96>; |
1f4c745b | 423 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
424 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; |
425 | clock-names = "sci_ick"; | |
426 | status = "disabled"; | |
427 | }; | |
428 | ||
429 | hscif1: serial@e62c8000 { | |
59d2b517 | 430 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
597af20f | 431 | reg = <0 0xe62c8000 0 96>; |
1f4c745b | 432 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
433 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; |
434 | clock-names = "sci_ick"; | |
435 | status = "disabled"; | |
436 | }; | |
437 | ||
d8913c67 SS |
438 | ether: ethernet@ee700000 { |
439 | compatible = "renesas,ether-r8a7790"; | |
440 | reg = <0 0xee700000 0 0x400>; | |
441 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
442 | clocks = <&mstp8_clks R8A7790_CLK_ETHER>; | |
443 | phy-mode = "rmii"; | |
444 | #address-cells = <1>; | |
445 | #size-cells = <0>; | |
446 | status = "disabled"; | |
447 | }; | |
448 | ||
cde630f7 VB |
449 | sata0: sata@ee300000 { |
450 | compatible = "renesas,sata-r8a7790"; | |
451 | reg = <0 0xee300000 0 0x2000>; | |
cde630f7 VB |
452 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
453 | clocks = <&mstp8_clks R8A7790_CLK_SATA0>; | |
454 | status = "disabled"; | |
455 | }; | |
456 | ||
457 | sata1: sata@ee500000 { | |
458 | compatible = "renesas,sata-r8a7790"; | |
459 | reg = <0 0xee500000 0 0x2000>; | |
cde630f7 VB |
460 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
461 | clocks = <&mstp8_clks R8A7790_CLK_SATA1>; | |
462 | status = "disabled"; | |
463 | }; | |
464 | ||
22a1f595 LP |
465 | clocks { |
466 | #address-cells = <2>; | |
467 | #size-cells = <2>; | |
468 | ranges; | |
469 | ||
470 | /* External root clock */ | |
471 | extal_clk: extal_clk { | |
472 | compatible = "fixed-clock"; | |
473 | #clock-cells = <0>; | |
474 | /* This value must be overriden by the board. */ | |
475 | clock-frequency = <0>; | |
476 | clock-output-names = "extal"; | |
477 | }; | |
478 | ||
c7c2ec3a KM |
479 | /* |
480 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by | |
481 | * default. Boards that provide audio clocks should override them. | |
482 | */ | |
483 | audio_clk_a: audio_clk_a { | |
484 | compatible = "fixed-clock"; | |
485 | #clock-cells = <0>; | |
486 | clock-frequency = <0>; | |
487 | clock-output-names = "audio_clk_a"; | |
488 | }; | |
489 | audio_clk_b: audio_clk_b { | |
490 | compatible = "fixed-clock"; | |
491 | #clock-cells = <0>; | |
492 | clock-frequency = <0>; | |
493 | clock-output-names = "audio_clk_b"; | |
494 | }; | |
495 | audio_clk_c: audio_clk_c { | |
496 | compatible = "fixed-clock"; | |
497 | #clock-cells = <0>; | |
498 | clock-frequency = <0>; | |
499 | clock-output-names = "audio_clk_c"; | |
500 | }; | |
501 | ||
22a1f595 LP |
502 | /* Special CPG clocks */ |
503 | cpg_clocks: cpg_clocks@e6150000 { | |
504 | compatible = "renesas,r8a7790-cpg-clocks", | |
505 | "renesas,rcar-gen2-cpg-clocks"; | |
506 | reg = <0 0xe6150000 0 0x1000>; | |
507 | clocks = <&extal_clk>; | |
508 | #clock-cells = <1>; | |
509 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
510 | "lb", "qspi", "sdh", "sd0", "sd1", | |
511 | "z"; | |
512 | }; | |
513 | ||
514 | /* Variable factor clocks */ | |
515 | sd2_clk: sd2_clk@e6150078 { | |
516 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
517 | reg = <0 0xe6150078 0 4>; | |
518 | clocks = <&pll1_div2_clk>; | |
519 | #clock-cells = <0>; | |
520 | clock-output-names = "sd2"; | |
521 | }; | |
522 | sd3_clk: sd3_clk@e615007c { | |
523 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
524 | reg = <0 0xe615007c 0 4>; | |
525 | clocks = <&pll1_div2_clk>; | |
526 | #clock-cells = <0>; | |
527 | clock-output-names = "sd3"; | |
528 | }; | |
529 | mmc0_clk: mmc0_clk@e6150240 { | |
530 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
531 | reg = <0 0xe6150240 0 4>; | |
532 | clocks = <&pll1_div2_clk>; | |
533 | #clock-cells = <0>; | |
534 | clock-output-names = "mmc0"; | |
535 | }; | |
536 | mmc1_clk: mmc1_clk@e6150244 { | |
537 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
538 | reg = <0 0xe6150244 0 4>; | |
539 | clocks = <&pll1_div2_clk>; | |
540 | #clock-cells = <0>; | |
541 | clock-output-names = "mmc1"; | |
542 | }; | |
543 | ssp_clk: ssp_clk@e6150248 { | |
544 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
545 | reg = <0 0xe6150248 0 4>; | |
546 | clocks = <&pll1_div2_clk>; | |
547 | #clock-cells = <0>; | |
548 | clock-output-names = "ssp"; | |
549 | }; | |
550 | ssprs_clk: ssprs_clk@e615024c { | |
551 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
552 | reg = <0 0xe615024c 0 4>; | |
553 | clocks = <&pll1_div2_clk>; | |
554 | #clock-cells = <0>; | |
555 | clock-output-names = "ssprs"; | |
556 | }; | |
557 | ||
558 | /* Fixed factor clocks */ | |
559 | pll1_div2_clk: pll1_div2_clk { | |
560 | compatible = "fixed-factor-clock"; | |
561 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
562 | #clock-cells = <0>; | |
563 | clock-div = <2>; | |
564 | clock-mult = <1>; | |
565 | clock-output-names = "pll1_div2"; | |
566 | }; | |
567 | z2_clk: z2_clk { | |
568 | compatible = "fixed-factor-clock"; | |
569 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
570 | #clock-cells = <0>; | |
571 | clock-div = <2>; | |
572 | clock-mult = <1>; | |
573 | clock-output-names = "z2"; | |
574 | }; | |
575 | zg_clk: zg_clk { | |
576 | compatible = "fixed-factor-clock"; | |
577 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
578 | #clock-cells = <0>; | |
579 | clock-div = <3>; | |
580 | clock-mult = <1>; | |
581 | clock-output-names = "zg"; | |
582 | }; | |
583 | zx_clk: zx_clk { | |
584 | compatible = "fixed-factor-clock"; | |
585 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
586 | #clock-cells = <0>; | |
587 | clock-div = <3>; | |
588 | clock-mult = <1>; | |
589 | clock-output-names = "zx"; | |
590 | }; | |
591 | zs_clk: zs_clk { | |
592 | compatible = "fixed-factor-clock"; | |
593 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
594 | #clock-cells = <0>; | |
595 | clock-div = <6>; | |
596 | clock-mult = <1>; | |
597 | clock-output-names = "zs"; | |
598 | }; | |
599 | hp_clk: hp_clk { | |
600 | compatible = "fixed-factor-clock"; | |
601 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
602 | #clock-cells = <0>; | |
603 | clock-div = <12>; | |
604 | clock-mult = <1>; | |
605 | clock-output-names = "hp"; | |
606 | }; | |
607 | i_clk: i_clk { | |
608 | compatible = "fixed-factor-clock"; | |
609 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
610 | #clock-cells = <0>; | |
611 | clock-div = <2>; | |
612 | clock-mult = <1>; | |
613 | clock-output-names = "i"; | |
614 | }; | |
615 | b_clk: b_clk { | |
616 | compatible = "fixed-factor-clock"; | |
617 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
618 | #clock-cells = <0>; | |
619 | clock-div = <12>; | |
620 | clock-mult = <1>; | |
621 | clock-output-names = "b"; | |
622 | }; | |
623 | p_clk: p_clk { | |
624 | compatible = "fixed-factor-clock"; | |
625 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
626 | #clock-cells = <0>; | |
627 | clock-div = <24>; | |
628 | clock-mult = <1>; | |
629 | clock-output-names = "p"; | |
630 | }; | |
631 | cl_clk: cl_clk { | |
632 | compatible = "fixed-factor-clock"; | |
633 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
634 | #clock-cells = <0>; | |
635 | clock-div = <48>; | |
636 | clock-mult = <1>; | |
637 | clock-output-names = "cl"; | |
638 | }; | |
639 | m2_clk: m2_clk { | |
640 | compatible = "fixed-factor-clock"; | |
641 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
642 | #clock-cells = <0>; | |
643 | clock-div = <8>; | |
644 | clock-mult = <1>; | |
645 | clock-output-names = "m2"; | |
646 | }; | |
647 | imp_clk: imp_clk { | |
648 | compatible = "fixed-factor-clock"; | |
649 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
650 | #clock-cells = <0>; | |
651 | clock-div = <4>; | |
652 | clock-mult = <1>; | |
653 | clock-output-names = "imp"; | |
654 | }; | |
655 | rclk_clk: rclk_clk { | |
656 | compatible = "fixed-factor-clock"; | |
657 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
658 | #clock-cells = <0>; | |
659 | clock-div = <(48 * 1024)>; | |
660 | clock-mult = <1>; | |
661 | clock-output-names = "rclk"; | |
662 | }; | |
663 | oscclk_clk: oscclk_clk { | |
664 | compatible = "fixed-factor-clock"; | |
665 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
666 | #clock-cells = <0>; | |
667 | clock-div = <(12 * 1024)>; | |
668 | clock-mult = <1>; | |
669 | clock-output-names = "oscclk"; | |
670 | }; | |
671 | zb3_clk: zb3_clk { | |
672 | compatible = "fixed-factor-clock"; | |
673 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
674 | #clock-cells = <0>; | |
675 | clock-div = <4>; | |
676 | clock-mult = <1>; | |
677 | clock-output-names = "zb3"; | |
678 | }; | |
679 | zb3d2_clk: zb3d2_clk { | |
680 | compatible = "fixed-factor-clock"; | |
681 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
682 | #clock-cells = <0>; | |
683 | clock-div = <8>; | |
684 | clock-mult = <1>; | |
685 | clock-output-names = "zb3d2"; | |
686 | }; | |
687 | ddr_clk: ddr_clk { | |
688 | compatible = "fixed-factor-clock"; | |
689 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
690 | #clock-cells = <0>; | |
691 | clock-div = <8>; | |
692 | clock-mult = <1>; | |
693 | clock-output-names = "ddr"; | |
694 | }; | |
695 | mp_clk: mp_clk { | |
696 | compatible = "fixed-factor-clock"; | |
697 | clocks = <&pll1_div2_clk>; | |
698 | #clock-cells = <0>; | |
699 | clock-div = <15>; | |
700 | clock-mult = <1>; | |
701 | clock-output-names = "mp"; | |
702 | }; | |
703 | cp_clk: cp_clk { | |
704 | compatible = "fixed-factor-clock"; | |
705 | clocks = <&extal_clk>; | |
706 | #clock-cells = <0>; | |
707 | clock-div = <2>; | |
708 | clock-mult = <1>; | |
709 | clock-output-names = "cp"; | |
710 | }; | |
711 | ||
712 | /* Gate clocks */ | |
9d90951a LP |
713 | mstp0_clks: mstp0_clks@e6150130 { |
714 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
715 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
716 | clocks = <&mp_clk>; | |
717 | #clock-cells = <1>; | |
718 | renesas,clock-indices = <R8A7790_CLK_MSIOF0>; | |
719 | clock-output-names = "msiof0"; | |
720 | }; | |
22a1f595 LP |
721 | mstp1_clks: mstp1_clks@e6150134 { |
722 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
723 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
724 | clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, | |
725 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, | |
726 | <&zs_clk>; | |
727 | #clock-cells = <1>; | |
728 | renesas,clock-indices = < | |
729 | R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 | |
730 | R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 | |
79ea9934 | 731 | R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S |
22a1f595 LP |
732 | >; |
733 | clock-output-names = | |
734 | "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", | |
735 | "vsp1-du0", "vsp1-rt", "vsp1-sy"; | |
736 | }; | |
737 | mstp2_clks: mstp2_clks@e6150138 { | |
738 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
739 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
740 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
9d90951a | 741 | <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; |
22a1f595 LP |
742 | #clock-cells = <1>; |
743 | renesas,clock-indices = < | |
744 | R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 | |
9d90951a LP |
745 | R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 |
746 | R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 | |
22a1f595 LP |
747 | >; |
748 | clock-output-names = | |
9d90951a LP |
749 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
750 | "scifb1", "msiof1", "msiof3", "scifb2"; | |
22a1f595 LP |
751 | }; |
752 | mstp3_clks: mstp3_clks@e615013c { | |
753 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
754 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
17465149 WS |
755 | clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, |
756 | <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, | |
757 | <&hp_clk>, <&hp_clk>, <&rclk_clk>; | |
22a1f595 LP |
758 | #clock-cells = <1>; |
759 | renesas,clock-indices = < | |
17465149 WS |
760 | R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 |
761 | R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 | |
762 | R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1 | |
22a1f595 LP |
763 | >; |
764 | clock-output-names = | |
17465149 WS |
765 | "iic2", "tpu0", "mmcif1", "sdhi3", |
766 | "sdhi2", "sdhi1", "sdhi0", "mmcif0", | |
767 | "iic0", "iic1", "cmt1"; | |
22a1f595 LP |
768 | }; |
769 | mstp5_clks: mstp5_clks@e6150144 { | |
770 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
771 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
772 | clocks = <&extal_clk>, <&p_clk>; | |
773 | #clock-cells = <1>; | |
774 | renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; | |
775 | clock-output-names = "thermal", "pwm"; | |
776 | }; | |
777 | mstp7_clks: mstp7_clks@e615014c { | |
778 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
779 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
780 | clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, | |
781 | <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, | |
782 | <&zx_clk>; | |
783 | #clock-cells = <1>; | |
784 | renesas,clock-indices = < | |
785 | R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 | |
786 | R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 | |
787 | R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 | |
788 | R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 | |
789 | >; | |
790 | clock-output-names = | |
791 | "ehci", "hsusb", "hscif1", "hscif0", "scif1", | |
792 | "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; | |
793 | }; | |
794 | mstp8_clks: mstp8_clks@e6150990 { | |
795 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
796 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
bccccc3d LP |
797 | clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, |
798 | <&zs_clk>, <&zs_clk>; | |
22a1f595 | 799 | #clock-cells = <1>; |
3f2beaa9 LP |
800 | renesas,clock-indices = < |
801 | R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 | |
bccccc3d LP |
802 | R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 |
803 | R8A7790_CLK_SATA0 | |
3f2beaa9 | 804 | >; |
bccccc3d LP |
805 | clock-output-names = |
806 | "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; | |
22a1f595 LP |
807 | }; |
808 | mstp9_clks: mstp9_clks@e6150994 { | |
809 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
810 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
81f6883f GU |
811 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, |
812 | <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
813 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, | |
3672b059 | 814 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; |
22a1f595 LP |
815 | #clock-cells = <1>; |
816 | renesas,clock-indices = < | |
81f6883f GU |
817 | R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 |
818 | R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 | |
17465149 WS |
819 | R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS |
820 | R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 | |
22a1f595 | 821 | >; |
91b56ca1 | 822 | clock-output-names = |
81f6883f | 823 | "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
17465149 WS |
824 | "rcan1", "rcan0", "qspi_mod", "iic3", |
825 | "i2c3", "i2c2", "i2c1", "i2c0"; | |
22a1f595 LP |
826 | }; |
827 | }; | |
7053e134 | 828 | |
fad6d45c | 829 | qspi: spi@e6b10000 { |
7053e134 GU |
830 | compatible = "renesas,qspi-r8a7790", "renesas,qspi"; |
831 | reg = <0 0xe6b10000 0 0x2c>; | |
7053e134 GU |
832 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
833 | clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; | |
834 | num-cs = <1>; | |
835 | #address-cells = <1>; | |
836 | #size-cells = <0>; | |
837 | status = "disabled"; | |
838 | }; | |
ae8a6146 GU |
839 | |
840 | msiof0: spi@e6e20000 { | |
841 | compatible = "renesas,msiof-r8a7790"; | |
842 | reg = <0 0xe6e20000 0 0x0064>; | |
843 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; | |
844 | clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; | |
845 | #address-cells = <1>; | |
846 | #size-cells = <0>; | |
847 | status = "disabled"; | |
848 | }; | |
849 | ||
850 | msiof1: spi@e6e10000 { | |
851 | compatible = "renesas,msiof-r8a7790"; | |
852 | reg = <0 0xe6e10000 0 0x0064>; | |
853 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; | |
854 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; | |
855 | #address-cells = <1>; | |
856 | #size-cells = <0>; | |
857 | status = "disabled"; | |
858 | }; | |
859 | ||
860 | msiof2: spi@e6e00000 { | |
861 | compatible = "renesas,msiof-r8a7790"; | |
862 | reg = <0 0xe6e00000 0 0x0064>; | |
863 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; | |
864 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; | |
865 | #address-cells = <1>; | |
866 | #size-cells = <0>; | |
867 | status = "disabled"; | |
868 | }; | |
869 | ||
870 | msiof3: spi@e6c90000 { | |
871 | compatible = "renesas,msiof-r8a7790"; | |
872 | reg = <0 0xe6c90000 0 0x0064>; | |
873 | interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; | |
874 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; | |
875 | #address-cells = <1>; | |
876 | #size-cells = <0>; | |
877 | status = "disabled"; | |
878 | }; | |
0468b2d6 | 879 | }; |