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ARM: shmobile: r8a7794: Add VIN clock to device tree
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / r8a7790.dtsi
CommitLineData
0468b2d6
MD		 1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
d8913c67
SS		 4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2014 Cogent Embedded Inc.
0468b2d6
MD		 6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
22a1f595 12#include <dt-bindings/clock/r8a7790-clock.h>
5f75e73c
LP		 13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
0468b2d6
MD		 16/ {
17 compatible = "renesas,r8a7790";
18 interrupt-parent = <&gic>;
8585deb1
TY		 19 #address-cells = <2>;
20 #size-cells = <2>;
0468b2d6 21
6b1d7c68
WS		 22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
05f39916
WS		 27 i2c4 = &iic0;
28 i2c5 = &iic1;
29 i2c6 = &iic2;
30 i2c7 = &iic3;
fad6d45c 31 spi0 = &qspi;
ae8a6146
GU		 32 spi1 = &msiof0;
33 spi2 = &msiof1;
34 spi3 = &msiof2;
35 spi4 = &msiof3;
9f685bfc
BD		 36 vin0 = &vin0;
37 vin1 = &vin1;
38 vin2 = &vin2;
39 vin3 = &vin3;
6b1d7c68
WS		 40 };
41
0468b2d6
MD		 42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <0>;
50 clock-frequency = <1300000000>;
b989e138
BC		 51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7790_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
54
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1400000 1000000>,
57 <1225000 1000000>,
58 <1050000 1000000>,
59 < 875000 1000000>,
60 < 700000 1000000>,
61 < 350000 1000000>;
0468b2d6 62 };
c1f95979
MD		 63
64 cpu1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
68 clock-frequency = <1300000000>;
69 };
70
71 cpu2: cpu@2 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a15";
74 reg = <2>;
75 clock-frequency = <1300000000>;
76 };
77
78 cpu3: cpu@3 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a15";
81 reg = <3>;
82 clock-frequency = <1300000000>;
83 };
2007e74c
MD		 84
85 cpu4: cpu@4 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a7";
88 reg = <0x100>;
89 clock-frequency = <780000000>;
90 };
91
92 cpu5: cpu@5 {
93 device_type = "cpu";
94 compatible = "arm,cortex-a7";
95 reg = <0x101>;
96 clock-frequency = <780000000>;
97 };
98
99 cpu6: cpu@6 {
100 device_type = "cpu";
101 compatible = "arm,cortex-a7";
102 reg = <0x102>;
103 clock-frequency = <780000000>;
104 };
105
106 cpu7: cpu@7 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a7";
109 reg = <0x103>;
110 clock-frequency = <780000000>;
111 };
0468b2d6
MD		 112 };
113
114 gic: interrupt-controller@f1001000 {
115 compatible = "arm,cortex-a15-gic";
116 #interrupt-cells = <3>;
117 #address-cells = <0>;
118 interrupt-controller;
8585deb1
TY		 119 reg = <0 0xf1001000 0 0x1000>,
120 <0 0xf1002000 0 0x1000>,
121 <0 0xf1004000 0 0x2000>,
122 <0 0xf1006000 0 0x2000>;
5f75e73c 123 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0468b2d6
MD		 124 };
125
23de2278 126 gpio0: gpio@e6050000 {
f98e10c8 127 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 128 reg = <0 0xe6050000 0 0x50>;
5f75e73c 129 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 130 #gpio-cells = <2>;
131 gpio-controller;
132 gpio-ranges = <&pfc 0 0 32>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
81f6883f 135 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
f98e10c8
LP		 136 };
137
23de2278 138 gpio1: gpio@e6051000 {
f98e10c8 139 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 140 reg = <0 0xe6051000 0 0x50>;
5f75e73c 141 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 142 #gpio-cells = <2>;
143 gpio-controller;
144 gpio-ranges = <&pfc 0 32 32>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
81f6883f 147 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
f98e10c8
LP		 148 };
149
23de2278 150 gpio2: gpio@e6052000 {
f98e10c8 151 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 152 reg = <0 0xe6052000 0 0x50>;
5f75e73c 153 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 154 #gpio-cells = <2>;
155 gpio-controller;
156 gpio-ranges = <&pfc 0 64 32>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
81f6883f 159 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
f98e10c8
LP		 160 };
161
23de2278 162 gpio3: gpio@e6053000 {
f98e10c8 163 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 164 reg = <0 0xe6053000 0 0x50>;
5f75e73c 165 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 166 #gpio-cells = <2>;
167 gpio-controller;
168 gpio-ranges = <&pfc 0 96 32>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
81f6883f 171 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
f98e10c8
LP		 172 };
173
23de2278 174 gpio4: gpio@e6054000 {
f98e10c8 175 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 176 reg = <0 0xe6054000 0 0x50>;
5f75e73c 177 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 178 #gpio-cells = <2>;
179 gpio-controller;
180 gpio-ranges = <&pfc 0 128 32>;
181 #interrupt-cells = <2>;
182 interrupt-controller;
81f6883f 183 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
f98e10c8
LP		 184 };
185
23de2278 186 gpio5: gpio@e6055000 {
f98e10c8 187 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 188 reg = <0 0xe6055000 0 0x50>;
5f75e73c 189 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 190 #gpio-cells = <2>;
191 gpio-controller;
192 gpio-ranges = <&pfc 0 160 32>;
193 #interrupt-cells = <2>;
194 interrupt-controller;
81f6883f 195 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
f98e10c8
LP		 196 };
197
03e2f56b
MD		 198 thermal@e61f0000 {
199 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
200 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
03e2f56b 201 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
d3a439db 202 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
03e2f56b
MD		 203 };
204
0468b2d6
MD		 205 timer {
206 compatible = "arm,armv7-timer";
5f75e73c
LP		 207 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
208 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
209 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
210 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0468b2d6 211 };
8f5ec0a5 212
39cf6d73 213 cmt0: timer@ffca0000 {
37757030 214 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
39cf6d73
LP		 215 reg = <0 0xffca0000 0 0x1004>;
216 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
217 <0 143 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
219 clock-names = "fck";
220
221 renesas,channels-mask = <0x60>;
222
223 status = "disabled";
224 };
225
226 cmt1: timer@e6130000 {
37757030 227 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
39cf6d73
LP		 228 reg = <0 0xe6130000 0 0x1004>;
229 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
230 <0 121 IRQ_TYPE_LEVEL_HIGH>,
231 <0 122 IRQ_TYPE_LEVEL_HIGH>,
232 <0 123 IRQ_TYPE_LEVEL_HIGH>,
233 <0 124 IRQ_TYPE_LEVEL_HIGH>,
234 <0 125 IRQ_TYPE_LEVEL_HIGH>,
235 <0 126 IRQ_TYPE_LEVEL_HIGH>,
236 <0 127 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
238 clock-names = "fck";
239
240 renesas,channels-mask = <0xff>;
241
242 status = "disabled";
243 };
244
8f5ec0a5 245 irqc0: interrupt-controller@e61c0000 {
220fc352 246 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
8f5ec0a5
MD		 247 #interrupt-cells = <2>;
248 interrupt-controller;
8585deb1 249 reg = <0 0xe61c0000 0 0x200>;
5f75e73c
LP		 250 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
251 <0 1 IRQ_TYPE_LEVEL_HIGH>,
252 <0 2 IRQ_TYPE_LEVEL_HIGH>,
253 <0 3 IRQ_TYPE_LEVEL_HIGH>;
8f5ec0a5 254 };
8c9b1aa4 255
b9fea49c
LP		 256 dmac0: dma-controller@e6700000 {
257 compatible = "renesas,rcar-dmac";
258 reg = <0 0xe6700000 0 0x20000>;
259 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
260 0 200 IRQ_TYPE_LEVEL_HIGH
261 0 201 IRQ_TYPE_LEVEL_HIGH
262 0 202 IRQ_TYPE_LEVEL_HIGH
263 0 203 IRQ_TYPE_LEVEL_HIGH
264 0 204 IRQ_TYPE_LEVEL_HIGH
265 0 205 IRQ_TYPE_LEVEL_HIGH
266 0 206 IRQ_TYPE_LEVEL_HIGH
267 0 207 IRQ_TYPE_LEVEL_HIGH
268 0 208 IRQ_TYPE_LEVEL_HIGH
269 0 209 IRQ_TYPE_LEVEL_HIGH
270 0 210 IRQ_TYPE_LEVEL_HIGH
271 0 211 IRQ_TYPE_LEVEL_HIGH
272 0 212 IRQ_TYPE_LEVEL_HIGH
273 0 213 IRQ_TYPE_LEVEL_HIGH
274 0 214 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-names = "error",
276 "ch0", "ch1", "ch2", "ch3",
277 "ch4", "ch5", "ch6", "ch7",
278 "ch8", "ch9", "ch10", "ch11",
279 "ch12", "ch13", "ch14";
280 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
281 clock-names = "fck";
282 #dma-cells = <1>;
283 dma-channels = <15>;
284 };
285
286 dmac1: dma-controller@e6720000 {
287 compatible = "renesas,rcar-dmac";
288 reg = <0 0xe6720000 0 0x20000>;
289 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
290 0 216 IRQ_TYPE_LEVEL_HIGH
291 0 217 IRQ_TYPE_LEVEL_HIGH
292 0 218 IRQ_TYPE_LEVEL_HIGH
293 0 219 IRQ_TYPE_LEVEL_HIGH
294 0 308 IRQ_TYPE_LEVEL_HIGH
295 0 309 IRQ_TYPE_LEVEL_HIGH
296 0 310 IRQ_TYPE_LEVEL_HIGH
297 0 311 IRQ_TYPE_LEVEL_HIGH
298 0 312 IRQ_TYPE_LEVEL_HIGH
299 0 313 IRQ_TYPE_LEVEL_HIGH
300 0 314 IRQ_TYPE_LEVEL_HIGH
301 0 315 IRQ_TYPE_LEVEL_HIGH
302 0 316 IRQ_TYPE_LEVEL_HIGH
303 0 317 IRQ_TYPE_LEVEL_HIGH
304 0 318 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-names = "error",
306 "ch0", "ch1", "ch2", "ch3",
307 "ch4", "ch5", "ch6", "ch7",
308 "ch8", "ch9", "ch10", "ch11",
309 "ch12", "ch13", "ch14";
310 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
311 clock-names = "fck";
312 #dma-cells = <1>;
313 dma-channels = <15>;
314 };
edd2b9f4
GL		 315 i2c0: i2c@e6508000 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 compatible = "renesas,i2c-r8a7790";
319 reg = <0 0xe6508000 0 0x40>;
5f75e73c 320 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
2450badf 321 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
edd2b9f4
GL		 322 status = "disabled";
323 };
324
325 i2c1: i2c@e6518000 {
326 #address-cells = <1>;
327 #size-cells = <0>;
328 compatible = "renesas,i2c-r8a7790";
329 reg = <0 0xe6518000 0 0x40>;
5f75e73c 330 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
2450badf 331 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
edd2b9f4
GL		 332 status = "disabled";
333 };
334
335 i2c2: i2c@e6530000 {
336 #address-cells = <1>;
337 #size-cells = <0>;
338 compatible = "renesas,i2c-r8a7790";
339 reg = <0 0xe6530000 0 0x40>;
5f75e73c 340 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
2450badf 341 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
edd2b9f4
GL		 342 status = "disabled";
343 };
344
345 i2c3: i2c@e6540000 {
346 #address-cells = <1>;
347 #size-cells = <0>;
348 compatible = "renesas,i2c-r8a7790";
349 reg = <0 0xe6540000 0 0x40>;
5f75e73c 350 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
2450badf 351 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
edd2b9f4
GL		 352 status = "disabled";
353 };
354
05f39916
WS		 355 iic0: i2c@e6500000 {
356 #address-cells = <1>;
357 #size-cells = <0>;
358 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
359 reg = <0 0xe6500000 0 0x425>;
360 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
362 status = "disabled";
363 };
364
365 iic1: i2c@e6510000 {
366 #address-cells = <1>;
367 #size-cells = <0>;
368 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
369 reg = <0 0xe6510000 0 0x425>;
370 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
372 status = "disabled";
373 };
374
375 iic2: i2c@e6520000 {
376 #address-cells = <1>;
377 #size-cells = <0>;
378 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
379 reg = <0 0xe6520000 0 0x425>;
380 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
382 status = "disabled";
383 };
384
385 iic3: i2c@e60b0000 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
389 reg = <0 0xe60b0000 0 0x425>;
390 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
392 status = "disabled";
393 };
394
22c2b78d 395 mmcif0: mmc@ee200000 {
063e8560 396 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 397 reg = <0 0xee200000 0 0x80>;
5f75e73c 398 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 399 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
108216c1
LP		 400 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
401 dma-names = "tx", "rx";
8c9b1aa4
GL		 402 reg-io-width = <4>;
403 status = "disabled";
404 };
405
b718aa44 406 mmcif1: mmc@ee220000 {
063e8560 407 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 408 reg = <0 0xee220000 0 0x80>;
5f75e73c 409 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 410 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
108216c1
LP		 411 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
412 dma-names = "tx", "rx";
8c9b1aa4
GL		 413 reg-io-width = <4>;
414 status = "disabled";
415 };
416
9694c778
LP		 417 pfc: pfc@e6060000 {
418 compatible = "renesas,pfc-r8a7790";
419 reg = <0 0xe6060000 0 0x250>;
420 };
55689bfa 421
b718aa44 422 sdhi0: sd@ee100000 {
df1d0584 423 compatible = "renesas,sdhi-r8a7790";
d721a15c 424 reg = <0 0xee100000 0 0x200>;
5f75e73c 425 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 426 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
8c9b1aa4
GL		 427 cap-sd-highspeed;
428 status = "disabled";
429 };
430
b718aa44 431 sdhi1: sd@ee120000 {
df1d0584 432 compatible = "renesas,sdhi-r8a7790";
d721a15c 433 reg = <0 0xee120000 0 0x200>;
5f75e73c 434 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 435 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
8c9b1aa4
GL		 436 cap-sd-highspeed;
437 status = "disabled";
438 };
439
b718aa44 440 sdhi2: sd@ee140000 {
df1d0584 441 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 442 reg = <0 0xee140000 0 0x100>;
5f75e73c 443 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 444 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
8c9b1aa4
GL		 445 cap-sd-highspeed;
446 status = "disabled";
447 };
448
b718aa44 449 sdhi3: sd@ee160000 {
df1d0584 450 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 451 reg = <0 0xee160000 0 0x100>;
5f75e73c 452 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 453 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
8c9b1aa4
GL		 454 cap-sd-highspeed;
455 status = "disabled";
456 };
22a1f595 457
597af20f 458 scifa0: serial@e6c40000 {
59d2b517 459 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 460 reg = <0 0xe6c40000 0 64>;
1f4c745b 461 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 462 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
463 clock-names = "sci_ick";
464 status = "disabled";
465 };
466
467 scifa1: serial@e6c50000 {
59d2b517 468 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 469 reg = <0 0xe6c50000 0 64>;
1f4c745b 470 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 471 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
472 clock-names = "sci_ick";
473 status = "disabled";
474 };
475
476 scifa2: serial@e6c60000 {
59d2b517 477 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 478 reg = <0 0xe6c60000 0 64>;
1f4c745b 479 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 480 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
481 clock-names = "sci_ick";
482 status = "disabled";
483 };
484
485 scifb0: serial@e6c20000 {
59d2b517 486 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 487 reg = <0 0xe6c20000 0 64>;
1f4c745b 488 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 489 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
490 clock-names = "sci_ick";
491 status = "disabled";
492 };
493
494 scifb1: serial@e6c30000 {
59d2b517 495 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 496 reg = <0 0xe6c30000 0 64>;
1f4c745b 497 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 498 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
499 clock-names = "sci_ick";
500 status = "disabled";
501 };
502
503 scifb2: serial@e6ce0000 {
59d2b517 504 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 505 reg = <0 0xe6ce0000 0 64>;
1f4c745b 506 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 507 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
508 clock-names = "sci_ick";
509 status = "disabled";
510 };
511
512 scif0: serial@e6e60000 {
59d2b517 513 compatible = "renesas,scif-r8a7790", "renesas,scif";
597af20f 514 reg = <0 0xe6e60000 0 64>;
1f4c745b 515 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 516 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
517 clock-names = "sci_ick";
518 status = "disabled";
519 };
520
521 scif1: serial@e6e68000 {
59d2b517 522 compatible = "renesas,scif-r8a7790", "renesas,scif";
597af20f 523 reg = <0 0xe6e68000 0 64>;
1f4c745b 524 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 525 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
526 clock-names = "sci_ick";
527 status = "disabled";
528 };
529
530 hscif0: serial@e62c0000 {
59d2b517 531 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
597af20f 532 reg = <0 0xe62c0000 0 96>;
1f4c745b 533 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 534 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
535 clock-names = "sci_ick";
536 status = "disabled";
537 };
538
539 hscif1: serial@e62c8000 {
59d2b517 540 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
597af20f 541 reg = <0 0xe62c8000 0 96>;
1f4c745b 542 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 543 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
544 clock-names = "sci_ick";
545 status = "disabled";
546 };
547
d8913c67
SS		 548 ether: ethernet@ee700000 {
549 compatible = "renesas,ether-r8a7790";
550 reg = <0 0xee700000 0 0x400>;
551 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
553 phy-mode = "rmii";
554 #address-cells = <1>;
555 #size-cells = <0>;
556 status = "disabled";
557 };
558
cde630f7
VB		 559 sata0: sata@ee300000 {
560 compatible = "renesas,sata-r8a7790";
561 reg = <0 0xee300000 0 0x2000>;
cde630f7
VB		 562 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
564 status = "disabled";
565 };
566
567 sata1: sata@ee500000 {
568 compatible = "renesas,sata-r8a7790";
569 reg = <0 0xee500000 0 0x2000>;
cde630f7
VB		 570 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
572 status = "disabled";
573 };
574
ae0a555b
YS		 575 hsusb: usb@e6590000 {
576 compatible = "renesas,usbhs-r8a7790";
577 reg = <0 0xe6590000 0 0x100>;
578 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
580 renesas,buswait = <4>;
581 phys = <&usb0 1>;
582 phy-names = "usb";
583 status = "disabled";
584 };
585
e089f657
SS		 586 usbphy: usb-phy@e6590100 {
587 compatible = "renesas,usb-phy-r8a7790";
588 reg = <0 0xe6590100 0 0x100>;
589 #address-cells = <1>;
590 #size-cells = <0>;
591 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
592 clock-names = "usbhs";
593 status = "disabled";
594
595 usb0: usb-channel@0 {
596 reg = <0>;
597 #phy-cells = <1>;
598 };
599 usb2: usb-channel@2 {
600 reg = <2>;
601 #phy-cells = <1>;
602 };
603 };
604
9f685bfc
BD		 605 vin0: video@e6ef0000 {
606 compatible = "renesas,vin-r8a7790";
607 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
608 reg = <0 0xe6ef0000 0 0x1000>;
609 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
610 status = "disabled";
611 };
612
613 vin1: video@e6ef1000 {
614 compatible = "renesas,vin-r8a7790";
615 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
616 reg = <0 0xe6ef1000 0 0x1000>;
617 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
618 status = "disabled";
619 };
620
621 vin2: video@e6ef2000 {
622 compatible = "renesas,vin-r8a7790";
623 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
624 reg = <0 0xe6ef2000 0 0x1000>;
625 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
626 status = "disabled";
627 };
628
629 vin3: video@e6ef3000 {
630 compatible = "renesas,vin-r8a7790";
631 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
632 reg = <0 0xe6ef3000 0 0x1000>;
633 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
634 status = "disabled";
635 };
636
3ac6a83c
LP		 637 vsp1@fe920000 {
638 compatible = "renesas,vsp1";
639 reg = <0 0xfe920000 0 0x8000>;
640 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
642
643 renesas,has-sru;
644 renesas,#rpf = <5>;
645 renesas,#uds = <1>;
646 renesas,#wpf = <4>;
647 };
648
649 vsp1@fe928000 {
650 compatible = "renesas,vsp1";
651 reg = <0 0xfe928000 0 0x8000>;
652 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
654
655 renesas,has-lut;
656 renesas,has-sru;
657 renesas,#rpf = <5>;
658 renesas,#uds = <3>;
659 renesas,#wpf = <4>;
660 };
661
662 vsp1@fe930000 {
663 compatible = "renesas,vsp1";
664 reg = <0 0xfe930000 0 0x8000>;
665 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
667
668 renesas,has-lif;
669 renesas,has-lut;
670 renesas,#rpf = <4>;
671 renesas,#uds = <1>;
672 renesas,#wpf = <4>;
673 };
674
675 vsp1@fe938000 {
676 compatible = "renesas,vsp1";
677 reg = <0 0xfe938000 0 0x8000>;
678 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
680
681 renesas,has-lif;
682 renesas,has-lut;
683 renesas,#rpf = <4>;
684 renesas,#uds = <1>;
685 renesas,#wpf = <4>;
686 };
687
688 du: display@feb00000 {
689 compatible = "renesas,du-r8a7790";
690 reg = <0 0xfeb00000 0 0x70000>,
691 <0 0xfeb90000 0 0x1c>,
692 <0 0xfeb94000 0 0x1c>;
693 reg-names = "du", "lvds.0", "lvds.1";
694 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
695 <0 268 IRQ_TYPE_LEVEL_HIGH>,
696 <0 269 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
698 <&mstp7_clks R8A7790_CLK_DU1>,
699 <&mstp7_clks R8A7790_CLK_DU2>,
700 <&mstp7_clks R8A7790_CLK_LVDS0>,
701 <&mstp7_clks R8A7790_CLK_LVDS1>;
702 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
703 status = "disabled";
704
705 ports {
706 #address-cells = <1>;
707 #size-cells = <0>;
708
709 port@0 {
710 reg = <0>;
711 du_out_rgb: endpoint {
712 };
713 };
714 port@1 {
715 reg = <1>;
716 du_out_lvds0: endpoint {
717 };
718 };
719 port@2 {
720 reg = <2>;
721 du_out_lvds1: endpoint {
722 };
723 };
724 };
725 };
726
22a1f595
LP		 727 clocks {
728 #address-cells = <2>;
729 #size-cells = <2>;
730 ranges;
731
732 /* External root clock */
733 extal_clk: extal_clk {
734 compatible = "fixed-clock";
735 #clock-cells = <0>;
736 /* This value must be overriden by the board. */
737 clock-frequency = <0>;
738 clock-output-names = "extal";
739 };
740
51d17918
PE		 741 /* External PCIe clock - can be overridden by the board */
742 pcie_bus_clk: pcie_bus_clk {
743 compatible = "fixed-clock";
744 #clock-cells = <0>;
745 clock-frequency = <100000000>;
746 clock-output-names = "pcie_bus";
747 status = "disabled";
748 };
749
c7c2ec3a
KM		 750 /*
751 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
752 * default. Boards that provide audio clocks should override them.
753 */
754 audio_clk_a: audio_clk_a {
755 compatible = "fixed-clock";
756 #clock-cells = <0>;
757 clock-frequency = <0>;
758 clock-output-names = "audio_clk_a";
759 };
760 audio_clk_b: audio_clk_b {
761 compatible = "fixed-clock";
762 #clock-cells = <0>;
763 clock-frequency = <0>;
764 clock-output-names = "audio_clk_b";
765 };
766 audio_clk_c: audio_clk_c {
767 compatible = "fixed-clock";
768 #clock-cells = <0>;
769 clock-frequency = <0>;
770 clock-output-names = "audio_clk_c";
771 };
772
22a1f595
LP		 773 /* Special CPG clocks */
774 cpg_clocks: cpg_clocks@e6150000 {
775 compatible = "renesas,r8a7790-cpg-clocks",
776 "renesas,rcar-gen2-cpg-clocks";
777 reg = <0 0xe6150000 0 0x1000>;
778 clocks = <&extal_clk>;
779 #clock-cells = <1>;
780 clock-output-names = "main", "pll0", "pll1", "pll3",
781 "lb", "qspi", "sdh", "sd0", "sd1",
782 "z";
783 };
784
785 /* Variable factor clocks */
786 sd2_clk: sd2_clk@e6150078 {
787 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
788 reg = <0 0xe6150078 0 4>;
789 clocks = <&pll1_div2_clk>;
790 #clock-cells = <0>;
791 clock-output-names = "sd2";
792 };
793 sd3_clk: sd3_clk@e615007c {
794 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
795 reg = <0 0xe615007c 0 4>;
796 clocks = <&pll1_div2_clk>;
797 #clock-cells = <0>;
798 clock-output-names = "sd3";
799 };
800 mmc0_clk: mmc0_clk@e6150240 {
801 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
802 reg = <0 0xe6150240 0 4>;
803 clocks = <&pll1_div2_clk>;
804 #clock-cells = <0>;
805 clock-output-names = "mmc0";
806 };
807 mmc1_clk: mmc1_clk@e6150244 {
808 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
809 reg = <0 0xe6150244 0 4>;
810 clocks = <&pll1_div2_clk>;
811 #clock-cells = <0>;
812 clock-output-names = "mmc1";
813 };
814 ssp_clk: ssp_clk@e6150248 {
815 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
816 reg = <0 0xe6150248 0 4>;
817 clocks = <&pll1_div2_clk>;
818 #clock-cells = <0>;
819 clock-output-names = "ssp";
820 };
821 ssprs_clk: ssprs_clk@e615024c {
822 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
823 reg = <0 0xe615024c 0 4>;
824 clocks = <&pll1_div2_clk>;
825 #clock-cells = <0>;
826 clock-output-names = "ssprs";
827 };
828
829 /* Fixed factor clocks */
830 pll1_div2_clk: pll1_div2_clk {
831 compatible = "fixed-factor-clock";
832 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
833 #clock-cells = <0>;
834 clock-div = <2>;
835 clock-mult = <1>;
836 clock-output-names = "pll1_div2";
837 };
838 z2_clk: z2_clk {
839 compatible = "fixed-factor-clock";
840 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
841 #clock-cells = <0>;
842 clock-div = <2>;
843 clock-mult = <1>;
844 clock-output-names = "z2";
845 };
846 zg_clk: zg_clk {
847 compatible = "fixed-factor-clock";
848 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
849 #clock-cells = <0>;
850 clock-div = <3>;
851 clock-mult = <1>;
852 clock-output-names = "zg";
853 };
854 zx_clk: zx_clk {
855 compatible = "fixed-factor-clock";
856 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
857 #clock-cells = <0>;
858 clock-div = <3>;
859 clock-mult = <1>;
860 clock-output-names = "zx";
861 };
862 zs_clk: zs_clk {
863 compatible = "fixed-factor-clock";
864 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
865 #clock-cells = <0>;
866 clock-div = <6>;
867 clock-mult = <1>;
868 clock-output-names = "zs";
869 };
870 hp_clk: hp_clk {
871 compatible = "fixed-factor-clock";
872 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
873 #clock-cells = <0>;
874 clock-div = <12>;
875 clock-mult = <1>;
876 clock-output-names = "hp";
877 };
878 i_clk: i_clk {
879 compatible = "fixed-factor-clock";
880 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
881 #clock-cells = <0>;
882 clock-div = <2>;
883 clock-mult = <1>;
884 clock-output-names = "i";
885 };
886 b_clk: b_clk {
887 compatible = "fixed-factor-clock";
888 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
889 #clock-cells = <0>;
890 clock-div = <12>;
891 clock-mult = <1>;
892 clock-output-names = "b";
893 };
894 p_clk: p_clk {
895 compatible = "fixed-factor-clock";
896 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
897 #clock-cells = <0>;
898 clock-div = <24>;
899 clock-mult = <1>;
900 clock-output-names = "p";
901 };
902 cl_clk: cl_clk {
903 compatible = "fixed-factor-clock";
904 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
905 #clock-cells = <0>;
906 clock-div = <48>;
907 clock-mult = <1>;
908 clock-output-names = "cl";
909 };
910 m2_clk: m2_clk {
911 compatible = "fixed-factor-clock";
912 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
913 #clock-cells = <0>;
914 clock-div = <8>;
915 clock-mult = <1>;
916 clock-output-names = "m2";
917 };
918 imp_clk: imp_clk {
919 compatible = "fixed-factor-clock";
920 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
921 #clock-cells = <0>;
922 clock-div = <4>;
923 clock-mult = <1>;
924 clock-output-names = "imp";
925 };
926 rclk_clk: rclk_clk {
927 compatible = "fixed-factor-clock";
928 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
929 #clock-cells = <0>;
930 clock-div = <(48 * 1024)>;
931 clock-mult = <1>;
932 clock-output-names = "rclk";
933 };
934 oscclk_clk: oscclk_clk {
935 compatible = "fixed-factor-clock";
936 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
937 #clock-cells = <0>;
938 clock-div = <(12 * 1024)>;
939 clock-mult = <1>;
940 clock-output-names = "oscclk";
941 };
942 zb3_clk: zb3_clk {
943 compatible = "fixed-factor-clock";
944 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
945 #clock-cells = <0>;
946 clock-div = <4>;
947 clock-mult = <1>;
948 clock-output-names = "zb3";
949 };
950 zb3d2_clk: zb3d2_clk {
951 compatible = "fixed-factor-clock";
952 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
953 #clock-cells = <0>;
954 clock-div = <8>;
955 clock-mult = <1>;
956 clock-output-names = "zb3d2";
957 };
958 ddr_clk: ddr_clk {
959 compatible = "fixed-factor-clock";
960 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
961 #clock-cells = <0>;
962 clock-div = <8>;
963 clock-mult = <1>;
964 clock-output-names = "ddr";
965 };
966 mp_clk: mp_clk {
967 compatible = "fixed-factor-clock";
968 clocks = <&pll1_div2_clk>;
969 #clock-cells = <0>;
970 clock-div = <15>;
971 clock-mult = <1>;
972 clock-output-names = "mp";
973 };
974 cp_clk: cp_clk {
975 compatible = "fixed-factor-clock";
976 clocks = <&extal_clk>;
977 #clock-cells = <0>;
978 clock-div = <2>;
979 clock-mult = <1>;
980 clock-output-names = "cp";
981 };
982
983 /* Gate clocks */
9d90951a
LP		 984 mstp0_clks: mstp0_clks@e6150130 {
985 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
986 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
987 clocks = <&mp_clk>;
988 #clock-cells = <1>;
989 renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
990 clock-output-names = "msiof0";
991 };
22a1f595
LP		 992 mstp1_clks: mstp1_clks@e6150134 {
993 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
994 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
4ba8f246
YH		 995 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
996 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
997 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
998 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
22a1f595
LP		 999 #clock-cells = <1>;
1000 renesas,clock-indices = <
4ba8f246
YH		 1001 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1002 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1003 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1004 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1005 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1006 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1007 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
22a1f595
LP		 1008 >;
1009 clock-output-names =
4ba8f246
YH		 1010 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1011 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1012 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
2284ff5f 1013 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
22a1f595
LP		 1014 };
1015 mstp2_clks: mstp2_clks@e6150138 {
1016 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1017 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1018 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
c819acda
LP		 1019 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1020 <&zs_clk>;
22a1f595
LP		 1021 #clock-cells = <1>;
1022 renesas,clock-indices = <
1023 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
9d90951a
LP		 1024 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1025 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
c819acda 1026 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
22a1f595
LP		 1027 >;
1028 clock-output-names =
9d90951a 1029 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
c819acda
LP		 1030 "scifb1", "msiof1", "msiof3", "scifb2",
1031 "sys-dmac1", "sys-dmac0";
22a1f595
LP		 1032 };
1033 mstp3_clks: mstp3_clks@e615013c {
1034 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1035 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
17465149
WS		 1036 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1037 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
ecafea8c 1038 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
22a1f595
LP		 1039 #clock-cells = <1>;
1040 renesas,clock-indices = <
17465149
WS		 1041 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1042 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
ecafea8c 1043 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
22a1f595
LP		 1044 >;
1045 clock-output-names =
17465149
WS		 1046 "iic2", "tpu0", "mmcif1", "sdhi3",
1047 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
ecafea8c 1048 "iic0", "pciec", "iic1", "ssusb", "cmt1";
22a1f595
LP		 1049 };
1050 mstp5_clks: mstp5_clks@e6150144 {
1051 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1052 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1053 clocks = <&extal_clk>, <&p_clk>;
1054 #clock-cells = <1>;
1055 renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
1056 clock-output-names = "thermal", "pwm";
1057 };
1058 mstp7_clks: mstp7_clks@e615014c {
1059 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1060 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1061 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1062 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1063 <&zx_clk>;
1064 #clock-cells = <1>;
1065 renesas,clock-indices = <
1066 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1067 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1068 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1069 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1070 >;
1071 clock-output-names =
1072 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1073 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1074 };
1075 mstp8_clks: mstp8_clks@e6150990 {
1076 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1077 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
bccccc3d
LP		 1078 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
1079 <&zs_clk>, <&zs_clk>;
22a1f595 1080 #clock-cells = <1>;
3f2beaa9
LP		 1081 renesas,clock-indices = <
1082 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
bccccc3d
LP		 1083 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
1084 R8A7790_CLK_SATA0
3f2beaa9 1085 >;
bccccc3d
LP		 1086 clock-output-names =
1087 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
22a1f595
LP		 1088 };
1089 mstp9_clks: mstp9_clks@e6150994 {
1090 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1091 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
81f6883f
GU		 1092 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1093 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1094 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
3672b059 1095 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
22a1f595
LP		 1096 #clock-cells = <1>;
1097 renesas,clock-indices = <
81f6883f
GU		 1098 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1099 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
17465149
WS		 1100 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1101 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
22a1f595 1102 >;
91b56ca1 1103 clock-output-names =
81f6883f 1104 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
17465149
WS		 1105 "rcan1", "rcan0", "qspi_mod", "iic3",
1106 "i2c3", "i2c2", "i2c1", "i2c0";
22a1f595 1107 };
bcde3722
KM		 1108 mstp10_clks: mstp10_clks@e6150998 {
1109 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1110 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1111 clocks = <&p_clk>,
1112 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1113 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1114 <&p_clk>,
1115 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1116 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1117 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1118 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1119 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1120 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1121
1122 #clock-cells = <1>;
1123 clock-indices = <
1124 R8A7790_CLK_SSI_ALL
1125 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1126 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1127 R8A7790_CLK_SCU_ALL
1128 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1129 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1130 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1131 >;
1132 clock-output-names =
1133 "ssi-all",
1134 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1135 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1136 "scu-all",
1137 "scu-dvc1", "scu-dvc0",
1138 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1139 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1140 };
22a1f595 1141 };
7053e134 1142
fad6d45c 1143 qspi: spi@e6b10000 {
7053e134
GU		 1144 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1145 reg = <0 0xe6b10000 0 0x2c>;
7053e134
GU		 1146 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1147 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
37cf3d61
GU		 1148 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1149 dma-names = "tx", "rx";
7053e134
GU		 1150 num-cs = <1>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153 status = "disabled";
1154 };
ae8a6146
GU		 1155
1156 msiof0: spi@e6e20000 {
1157 compatible = "renesas,msiof-r8a7790";
fbff6688 1158 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
ae8a6146
GU		 1159 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
fbff6688
GU		 1161 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1162 dma-names = "tx", "rx";
ae8a6146
GU		 1163 #address-cells = <1>;
1164 #size-cells = <0>;
1165 status = "disabled";
1166 };
1167
1168 msiof1: spi@e6e10000 {
1169 compatible = "renesas,msiof-r8a7790";
fbff6688 1170 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
ae8a6146
GU		 1171 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
fbff6688
GU		 1173 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1174 dma-names = "tx", "rx";
ae8a6146
GU		 1175 #address-cells = <1>;
1176 #size-cells = <0>;
1177 status = "disabled";
1178 };
1179
1180 msiof2: spi@e6e00000 {
1181 compatible = "renesas,msiof-r8a7790";
fbff6688 1182 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
ae8a6146
GU		 1183 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1184 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
fbff6688
GU		 1185 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1186 dma-names = "tx", "rx";
ae8a6146
GU		 1187 #address-cells = <1>;
1188 #size-cells = <0>;
1189 status = "disabled";
1190 };
1191
1192 msiof3: spi@e6c90000 {
1193 compatible = "renesas,msiof-r8a7790";
fbff6688 1194 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
ae8a6146
GU		 1195 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1196 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
fbff6688
GU		 1197 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1198 dma-names = "tx", "rx";
ae8a6146
GU		 1199 #address-cells = <1>;
1200 #size-cells = <0>;
1201 status = "disabled";
1202 };
7df2fd57 1203
157fcd8a
YS		 1204 xhci: usb@ee000000 {
1205 compatible = "renesas,xhci-r8a7790";
1206 reg = <0 0xee000000 0 0xc00>;
1207 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1209 phys = <&usb2 1>;
1210 phy-names = "usb";
1211 status = "disabled";
1212 };
1213
ff4f3eb8
BD		 1214 pci0: pci@ee090000 {
1215 compatible = "renesas,pci-r8a7790";
1216 device_type = "pci";
1217 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1218 reg = <0 0xee090000 0 0xc00>,
1219 <0 0xee080000 0 0x1100>;
1220 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1221 status = "disabled";
1222
1223 bus-range = <0 0>;
1224 #address-cells = <3>;
1225 #size-cells = <2>;
1226 #interrupt-cells = <1>;
1227 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1228 interrupt-map-mask = <0xff00 0 0 0x7>;
1229 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
517ec80a
GU		 1230 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1231 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
538c40e5
SS		 1232
1233 usb@0,1 {
1234 reg = <0x800 0 0 0 0>;
1235 device_type = "pci";
1236 phys = <&usb0 0>;
1237 phy-names = "usb";
1238 };
1239
1240 usb@0,2 {
1241 reg = <0x1000 0 0 0 0>;
1242 device_type = "pci";
1243 phys = <&usb0 0>;
1244 phy-names = "usb";
1245 };
ff4f3eb8
BD		 1246 };
1247
1248 pci1: pci@ee0b0000 {
1249 compatible = "renesas,pci-r8a7790";
1250 device_type = "pci";
1251 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1252 reg = <0 0xee0b0000 0 0xc00>,
1253 <0 0xee0a0000 0 0x1100>;
1254 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1255 status = "disabled";
1256
1257 bus-range = <1 1>;
1258 #address-cells = <3>;
1259 #size-cells = <2>;
1260 #interrupt-cells = <1>;
1261 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1262 interrupt-map-mask = <0xff00 0 0 0x7>;
1263 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
517ec80a
GU		 1264 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1265 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
ff4f3eb8
BD		 1266 };
1267
1268 pci2: pci@ee0d0000 {
1269 compatible = "renesas,pci-r8a7790";
1270 device_type = "pci";
1271 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1272 reg = <0 0xee0d0000 0 0xc00>,
1273 <0 0xee0c0000 0 0x1100>;
1274 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1275 status = "disabled";
1276
1277 bus-range = <2 2>;
1278 #address-cells = <3>;
1279 #size-cells = <2>;
1280 #interrupt-cells = <1>;
1281 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1282 interrupt-map-mask = <0xff00 0 0 0x7>;
1283 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
517ec80a
GU		 1284 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1285 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
538c40e5
SS		 1286
1287 usb@0,1 {
1288 reg = <0x800 0 0 0 0>;
1289 device_type = "pci";
1290 phys = <&usb2 0>;
1291 phy-names = "usb";
1292 };
1293
1294 usb@0,2 {
1295 reg = <0x1000 0 0 0 0>;
1296 device_type = "pci";
1297 phys = <&usb2 0>;
1298 phy-names = "usb";
1299 };
ff4f3eb8
BD		 1300 };
1301
745329d2
PE		 1302 pciec: pcie@fe000000 {
1303 compatible = "renesas,pcie-r8a7790";
1304 reg = <0 0xfe000000 0 0x80000>;
1305 #address-cells = <3>;
1306 #size-cells = <2>;
1307 bus-range = <0x00 0xff>;
1308 device_type = "pci";
1309 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1310 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1311 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1312 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1313 /* Map all possible DDR as inbound ranges */
1314 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1315 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1316 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1317 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1318 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1319 #interrupt-cells = <1>;
1320 interrupt-map-mask = <0 0 0 0>;
1321 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1322 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1323 clock-names = "pcie", "pcie_bus";
1324 status = "disabled";
1325 };
1326
7df2fd57
KM		 1327 rcar_sound: rcar_sound@0xec500000 {
1328 #sound-dai-cells = <1>;
1329 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
7df2fd57
KM		 1330 reg = <0 0xec500000 0 0x1000>, /* SCU */
1331 <0 0xec5a0000 0 0x100>, /* ADG */
1332 <0 0xec540000 0 0x1000>, /* SSIU */
1333 <0 0xec541000 0 0x1280>; /* SSI */
1334 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1335 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1336 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1337 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1338 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1339 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1340 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1341 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1342 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1343 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1344 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
334d69a2 1345 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
7df2fd57
KM		 1346 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1347 clock-names = "ssi-all",
1348 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1349 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1350 "src.9", "src.8", "src.7", "src.6", "src.5",
1351 "src.4", "src.3", "src.2", "src.1", "src.0",
334d69a2 1352 "dvc.0", "dvc.1",
7df2fd57
KM		 1353 "clk_a", "clk_b", "clk_c", "clk_i";
1354
1355 status = "disabled";
1356
334d69a2
KM		 1357 rcar_sound,dvc {
1358 dvc0: dvc@0 { };
1359 dvc1: dvc@1 { };
1360 };
1361
7df2fd57
KM		 1362 rcar_sound,src {
1363 src0: src@0 { };
1364 src1: src@1 { };
1365 src2: src@2 { };
1366 src3: src@3 { };
1367 src4: src@4 { };
1368 src5: src@5 { };
1369 src6: src@6 { };
1370 src7: src@7 { };
1371 src8: src@8 { };
1372 src9: src@9 { };
1373 };
1374
1375 rcar_sound,ssi {
1376 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1377 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1378 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1379 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1380 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1381 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1382 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1383 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1384 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1385 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1386 };
1387 };
0468b2d6 1388};
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