projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 0468b2d6 MD |
1 | /* |
| 2 | * Device Tree Source for the r8a7790 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public License | |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | |
| 8 | * kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 22a1f595 | 11 | #include <dt-bindings/clock/r8a7790-clock.h> |
| 5f75e73c LP |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 13 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 14 | ||
| 0468b2d6 MD |
15 | / { |
| 16 | compatible = "renesas,r8a7790"; | |
| 17 | interrupt-parent = <&gic>; | |
| 8585deb1 TY |
18 | #address-cells = <2>; |
| 19 | #size-cells = <2>; | |
| 0468b2d6 | 20 | |
| 6b1d7c68 WS |
21 | aliases { |
| 22 | i2c0 = &i2c0; | |
| 23 | i2c1 = &i2c1; | |
| 24 | i2c2 = &i2c2; | |
| 25 | i2c3 = &i2c3; | |
| 26 | }; | |
| 27 | ||
| 0468b2d6 MD |
28 | cpus { |
| 29 | #address-cells = <1>; | |
| 30 | #size-cells = <0>; | |
| 31 | ||
| 32 | cpu0: cpu@0 { | |
| 33 | device_type = "cpu"; | |
| 34 | compatible = "arm,cortex-a15"; | |
| 35 | reg = <0>; | |
| 36 | clock-frequency = <1300000000>; | |
| 37 | }; | |
| c1f95979 MD |
38 | |
| 39 | cpu1: cpu@1 { | |
| 40 | device_type = "cpu"; | |
| 41 | compatible = "arm,cortex-a15"; | |
| 42 | reg = <1>; | |
| 43 | clock-frequency = <1300000000>; | |
| 44 | }; | |
| 45 | ||
| 46 | cpu2: cpu@2 { | |
| 47 | device_type = "cpu"; | |
| 48 | compatible = "arm,cortex-a15"; | |
| 49 | reg = <2>; | |
| 50 | clock-frequency = <1300000000>; | |
| 51 | }; | |
| 52 | ||
| 53 | cpu3: cpu@3 { | |
| 54 | device_type = "cpu"; | |
| 55 | compatible = "arm,cortex-a15"; | |
| 56 | reg = <3>; | |
| 57 | clock-frequency = <1300000000>; | |
| 58 | }; | |
| 2007e74c MD |
59 | |
| 60 | cpu4: cpu@4 { | |
| 61 | device_type = "cpu"; | |
| 62 | compatible = "arm,cortex-a7"; | |
| 63 | reg = <0x100>; | |
| 64 | clock-frequency = <780000000>; | |
| 65 | }; | |
| 66 | ||
| 67 | cpu5: cpu@5 { | |
| 68 | device_type = "cpu"; | |
| 69 | compatible = "arm,cortex-a7"; | |
| 70 | reg = <0x101>; | |
| 71 | clock-frequency = <780000000>; | |
| 72 | }; | |
| 73 | ||
| 74 | cpu6: cpu@6 { | |
| 75 | device_type = "cpu"; | |
| 76 | compatible = "arm,cortex-a7"; | |
| 77 | reg = <0x102>; | |
| 78 | clock-frequency = <780000000>; | |
| 79 | }; | |
| 80 | ||
| 81 | cpu7: cpu@7 { | |
| 82 | device_type = "cpu"; | |
| 83 | compatible = "arm,cortex-a7"; | |
| 84 | reg = <0x103>; | |
| 85 | clock-frequency = <780000000>; | |
| 86 | }; | |
| 0468b2d6 MD |
87 | }; |
| 88 | ||
| 89 | gic: interrupt-controller@f1001000 { | |
| 90 | compatible = "arm,cortex-a15-gic"; | |
| 91 | #interrupt-cells = <3>; | |
| 92 | #address-cells = <0>; | |
| 93 | interrupt-controller; | |
| 8585deb1 TY |
94 | reg = <0 0xf1001000 0 0x1000>, |
| 95 | <0 0xf1002000 0 0x1000>, | |
| 96 | <0 0xf1004000 0 0x2000>, | |
| 97 | <0 0xf1006000 0 0x2000>; | |
| 5f75e73c | 98 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 0468b2d6 MD |
99 | }; |
| 100 | ||
| 23de2278 | 101 | gpio0: gpio@e6050000 { |
| f98e10c8 | 102 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 103 | reg = <0 0xe6050000 0 0x50>; |
| 5f75e73c | 104 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
105 | #gpio-cells = <2>; |
| 106 | gpio-controller; | |
| 107 | gpio-ranges = <&pfc 0 0 32>; | |
| 108 | #interrupt-cells = <2>; | |
| 109 | interrupt-controller; | |
| 110 | }; | |
| 111 | ||
| 23de2278 | 112 | gpio1: gpio@e6051000 { |
| f98e10c8 | 113 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 114 | reg = <0 0xe6051000 0 0x50>; |
| 5f75e73c | 115 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
116 | #gpio-cells = <2>; |
| 117 | gpio-controller; | |
| 118 | gpio-ranges = <&pfc 0 32 32>; | |
| 119 | #interrupt-cells = <2>; | |
| 120 | interrupt-controller; | |
| 121 | }; | |
| 122 | ||
| 23de2278 | 123 | gpio2: gpio@e6052000 { |
| f98e10c8 | 124 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 125 | reg = <0 0xe6052000 0 0x50>; |
| 5f75e73c | 126 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
127 | #gpio-cells = <2>; |
| 128 | gpio-controller; | |
| 129 | gpio-ranges = <&pfc 0 64 32>; | |
| 130 | #interrupt-cells = <2>; | |
| 131 | interrupt-controller; | |
| 132 | }; | |
| 133 | ||
| 23de2278 | 134 | gpio3: gpio@e6053000 { |
| f98e10c8 | 135 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 136 | reg = <0 0xe6053000 0 0x50>; |
| 5f75e73c | 137 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
138 | #gpio-cells = <2>; |
| 139 | gpio-controller; | |
| 140 | gpio-ranges = <&pfc 0 96 32>; | |
| 141 | #interrupt-cells = <2>; | |
| 142 | interrupt-controller; | |
| 143 | }; | |
| 144 | ||
| 23de2278 | 145 | gpio4: gpio@e6054000 { |
| f98e10c8 | 146 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 147 | reg = <0 0xe6054000 0 0x50>; |
| 5f75e73c | 148 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
149 | #gpio-cells = <2>; |
| 150 | gpio-controller; | |
| 151 | gpio-ranges = <&pfc 0 128 32>; | |
| 152 | #interrupt-cells = <2>; | |
| 153 | interrupt-controller; | |
| 154 | }; | |
| 155 | ||
| 23de2278 | 156 | gpio5: gpio@e6055000 { |
| f98e10c8 | 157 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 158 | reg = <0 0xe6055000 0 0x50>; |
| 5f75e73c | 159 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
160 | #gpio-cells = <2>; |
| 161 | gpio-controller; | |
| 162 | gpio-ranges = <&pfc 0 160 32>; | |
| 163 | #interrupt-cells = <2>; | |
| 164 | interrupt-controller; | |
| 165 | }; | |
| 166 | ||
| 03e2f56b MD |
167 | thermal@e61f0000 { |
| 168 | compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; | |
| 169 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | |
| 03e2f56b | 170 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
| d3a439db | 171 | clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; |
| 03e2f56b MD |
172 | }; |
| 173 | ||
| 0468b2d6 MD |
174 | timer { |
| 175 | compatible = "arm,armv7-timer"; | |
| 5f75e73c LP |
176 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 177 | <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 178 | <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 179 | <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| 0468b2d6 | 180 | }; |
| 8f5ec0a5 MD |
181 | |
| 182 | irqc0: interrupt-controller@e61c0000 { | |
| 220fc352 | 183 | compatible = "renesas,irqc-r8a7790", "renesas,irqc"; |
| 8f5ec0a5 MD |
184 | #interrupt-cells = <2>; |
| 185 | interrupt-controller; | |
| 8585deb1 | 186 | reg = <0 0xe61c0000 0 0x200>; |
| 5f75e73c LP |
187 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 188 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
| 189 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
| 190 | <0 3 IRQ_TYPE_LEVEL_HIGH>; | |
| 8f5ec0a5 | 191 | }; |
| 8c9b1aa4 | 192 | |
| edd2b9f4 GL |
193 | i2c0: i2c@e6508000 { |
| 194 | #address-cells = <1>; | |
| 195 | #size-cells = <0>; | |
| 196 | compatible = "renesas,i2c-r8a7790"; | |
| 197 | reg = <0 0xe6508000 0 0x40>; | |
| 5f75e73c | 198 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; |
| 2450badf | 199 | clocks = <&mstp9_clks R8A7790_CLK_I2C0>; |
| edd2b9f4 GL |
200 | status = "disabled"; |
| 201 | }; | |
| 202 | ||
| 203 | i2c1: i2c@e6518000 { | |
| 204 | #address-cells = <1>; | |
| 205 | #size-cells = <0>; | |
| 206 | compatible = "renesas,i2c-r8a7790"; | |
| 207 | reg = <0 0xe6518000 0 0x40>; | |
| 5f75e73c | 208 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; |
| 2450badf | 209 | clocks = <&mstp9_clks R8A7790_CLK_I2C1>; |
| edd2b9f4 GL |
210 | status = "disabled"; |
| 211 | }; | |
| 212 | ||
| 213 | i2c2: i2c@e6530000 { | |
| 214 | #address-cells = <1>; | |
| 215 | #size-cells = <0>; | |
| 216 | compatible = "renesas,i2c-r8a7790"; | |
| 217 | reg = <0 0xe6530000 0 0x40>; | |
| 5f75e73c | 218 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; |
| 2450badf | 219 | clocks = <&mstp9_clks R8A7790_CLK_I2C2>; |
| edd2b9f4 GL |
220 | status = "disabled"; |
| 221 | }; | |
| 222 | ||
| 223 | i2c3: i2c@e6540000 { | |
| 224 | #address-cells = <1>; | |
| 225 | #size-cells = <0>; | |
| 226 | compatible = "renesas,i2c-r8a7790"; | |
| 227 | reg = <0 0xe6540000 0 0x40>; | |
| 5f75e73c | 228 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; |
| 2450badf | 229 | clocks = <&mstp9_clks R8A7790_CLK_I2C3>; |
| edd2b9f4 GL |
230 | status = "disabled"; |
| 231 | }; | |
| 232 | ||
| 8c9b1aa4 | 233 | mmcif0: mmcif@ee200000 { |
| 063e8560 | 234 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
| 8c9b1aa4 | 235 | reg = <0 0xee200000 0 0x80>; |
| 5f75e73c | 236 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 237 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; |
| 8c9b1aa4 GL |
238 | reg-io-width = <4>; |
| 239 | status = "disabled"; | |
| 240 | }; | |
| 241 | ||
| b718aa44 | 242 | mmcif1: mmc@ee220000 { |
| 063e8560 | 243 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
| 8c9b1aa4 | 244 | reg = <0 0xee220000 0 0x80>; |
| 5f75e73c | 245 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 246 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; |
| 8c9b1aa4 GL |
247 | reg-io-width = <4>; |
| 248 | status = "disabled"; | |
| 249 | }; | |
| 250 | ||
| 9694c778 LP |
251 | pfc: pfc@e6060000 { |
| 252 | compatible = "renesas,pfc-r8a7790"; | |
| 253 | reg = <0 0xe6060000 0 0x250>; | |
| 254 | }; | |
| 55689bfa | 255 | |
| b718aa44 | 256 | sdhi0: sd@ee100000 { |
| df1d0584 | 257 | compatible = "renesas,sdhi-r8a7790"; |
| d721a15c | 258 | reg = <0 0xee100000 0 0x200>; |
| 5f75e73c | 259 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 260 | clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; |
| 8c9b1aa4 GL |
261 | cap-sd-highspeed; |
| 262 | status = "disabled"; | |
| 263 | }; | |
| 264 | ||
| b718aa44 | 265 | sdhi1: sd@ee120000 { |
| df1d0584 | 266 | compatible = "renesas,sdhi-r8a7790"; |
| d721a15c | 267 | reg = <0 0xee120000 0 0x200>; |
| 5f75e73c | 268 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 269 | clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; |
| 8c9b1aa4 GL |
270 | cap-sd-highspeed; |
| 271 | status = "disabled"; | |
| 272 | }; | |
| 273 | ||
| b718aa44 | 274 | sdhi2: sd@ee140000 { |
| df1d0584 | 275 | compatible = "renesas,sdhi-r8a7790"; |
| 8c9b1aa4 | 276 | reg = <0 0xee140000 0 0x100>; |
| 5f75e73c | 277 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 278 | clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; |
| 8c9b1aa4 GL |
279 | cap-sd-highspeed; |
| 280 | status = "disabled"; | |
| 281 | }; | |
| 282 | ||
| b718aa44 | 283 | sdhi3: sd@ee160000 { |
| df1d0584 | 284 | compatible = "renesas,sdhi-r8a7790"; |
| 8c9b1aa4 | 285 | reg = <0 0xee160000 0 0x100>; |
| 5f75e73c | 286 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 287 | clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; |
| 8c9b1aa4 GL |
288 | cap-sd-highspeed; |
| 289 | status = "disabled"; | |
| 290 | }; | |
| 22a1f595 | 291 | |
| 597af20f | 292 | scifa0: serial@e6c40000 { |
| 59d2b517 | 293 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
| 597af20f | 294 | reg = <0 0xe6c40000 0 64>; |
| 1f4c745b | 295 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
296 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; |
| 297 | clock-names = "sci_ick"; | |
| 298 | status = "disabled"; | |
| 299 | }; | |
| 300 | ||
| 301 | scifa1: serial@e6c50000 { | |
| 59d2b517 | 302 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
| 597af20f | 303 | reg = <0 0xe6c50000 0 64>; |
| 1f4c745b | 304 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
305 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; |
| 306 | clock-names = "sci_ick"; | |
| 307 | status = "disabled"; | |
| 308 | }; | |
| 309 | ||
| 310 | scifa2: serial@e6c60000 { | |
| 59d2b517 | 311 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
| 597af20f | 312 | reg = <0 0xe6c60000 0 64>; |
| 1f4c745b | 313 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
314 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; |
| 315 | clock-names = "sci_ick"; | |
| 316 | status = "disabled"; | |
| 317 | }; | |
| 318 | ||
| 319 | scifb0: serial@e6c20000 { | |
| 59d2b517 | 320 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
| 597af20f | 321 | reg = <0 0xe6c20000 0 64>; |
| 1f4c745b | 322 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
323 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; |
| 324 | clock-names = "sci_ick"; | |
| 325 | status = "disabled"; | |
| 326 | }; | |
| 327 | ||
| 328 | scifb1: serial@e6c30000 { | |
| 59d2b517 | 329 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
| 597af20f | 330 | reg = <0 0xe6c30000 0 64>; |
| 1f4c745b | 331 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
332 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; |
| 333 | clock-names = "sci_ick"; | |
| 334 | status = "disabled"; | |
| 335 | }; | |
| 336 | ||
| 337 | scifb2: serial@e6ce0000 { | |
| 59d2b517 | 338 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
| 597af20f | 339 | reg = <0 0xe6ce0000 0 64>; |
| 1f4c745b | 340 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
341 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; |
| 342 | clock-names = "sci_ick"; | |
| 343 | status = "disabled"; | |
| 344 | }; | |
| 345 | ||
| 346 | scif0: serial@e6e60000 { | |
| 59d2b517 | 347 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
| 597af20f | 348 | reg = <0 0xe6e60000 0 64>; |
| 1f4c745b | 349 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
350 | clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; |
| 351 | clock-names = "sci_ick"; | |
| 352 | status = "disabled"; | |
| 353 | }; | |
| 354 | ||
| 355 | scif1: serial@e6e68000 { | |
| 59d2b517 | 356 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
| 597af20f | 357 | reg = <0 0xe6e68000 0 64>; |
| 1f4c745b | 358 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
359 | clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; |
| 360 | clock-names = "sci_ick"; | |
| 361 | status = "disabled"; | |
| 362 | }; | |
| 363 | ||
| 364 | hscif0: serial@e62c0000 { | |
| 59d2b517 | 365 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
| 597af20f | 366 | reg = <0 0xe62c0000 0 96>; |
| 1f4c745b | 367 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
368 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; |
| 369 | clock-names = "sci_ick"; | |
| 370 | status = "disabled"; | |
| 371 | }; | |
| 372 | ||
| 373 | hscif1: serial@e62c8000 { | |
| 59d2b517 | 374 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
| 597af20f | 375 | reg = <0 0xe62c8000 0 96>; |
| 1f4c745b | 376 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
377 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; |
| 378 | clock-names = "sci_ick"; | |
| 379 | status = "disabled"; | |
| 380 | }; | |
| 381 | ||
| cde630f7 VB |
382 | sata0: sata@ee300000 { |
| 383 | compatible = "renesas,sata-r8a7790"; | |
| 384 | reg = <0 0xee300000 0 0x2000>; | |
| cde630f7 VB |
385 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
| 386 | clocks = <&mstp8_clks R8A7790_CLK_SATA0>; | |
| 387 | status = "disabled"; | |
| 388 | }; | |
| 389 | ||
| 390 | sata1: sata@ee500000 { | |
| 391 | compatible = "renesas,sata-r8a7790"; | |
| 392 | reg = <0 0xee500000 0 0x2000>; | |
| cde630f7 VB |
393 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
| 394 | clocks = <&mstp8_clks R8A7790_CLK_SATA1>; | |
| 395 | status = "disabled"; | |
| 396 | }; | |
| 397 | ||
| 22a1f595 LP |
398 | clocks { |
| 399 | #address-cells = <2>; | |
| 400 | #size-cells = <2>; | |
| 401 | ranges; | |
| 402 | ||
| 403 | /* External root clock */ | |
| 404 | extal_clk: extal_clk { | |
| 405 | compatible = "fixed-clock"; | |
| 406 | #clock-cells = <0>; | |
| 407 | /* This value must be overriden by the board. */ | |
| 408 | clock-frequency = <0>; | |
| 409 | clock-output-names = "extal"; | |
| 410 | }; | |
| 411 | ||
| 412 | /* Special CPG clocks */ | |
| 413 | cpg_clocks: cpg_clocks@e6150000 { | |
| 414 | compatible = "renesas,r8a7790-cpg-clocks", | |
| 415 | "renesas,rcar-gen2-cpg-clocks"; | |
| 416 | reg = <0 0xe6150000 0 0x1000>; | |
| 417 | clocks = <&extal_clk>; | |
| 418 | #clock-cells = <1>; | |
| 419 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
| 420 | "lb", "qspi", "sdh", "sd0", "sd1", | |
| 421 | "z"; | |
| 422 | }; | |
| 423 | ||
| 424 | /* Variable factor clocks */ | |
| 425 | sd2_clk: sd2_clk@e6150078 { | |
| 426 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
| 427 | reg = <0 0xe6150078 0 4>; | |
| 428 | clocks = <&pll1_div2_clk>; | |
| 429 | #clock-cells = <0>; | |
| 430 | clock-output-names = "sd2"; | |
| 431 | }; | |
| 432 | sd3_clk: sd3_clk@e615007c { | |
| 433 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
| 434 | reg = <0 0xe615007c 0 4>; | |
| 435 | clocks = <&pll1_div2_clk>; | |
| 436 | #clock-cells = <0>; | |
| 437 | clock-output-names = "sd3"; | |
| 438 | }; | |
| 439 | mmc0_clk: mmc0_clk@e6150240 { | |
| 440 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
| 441 | reg = <0 0xe6150240 0 4>; | |
| 442 | clocks = <&pll1_div2_clk>; | |
| 443 | #clock-cells = <0>; | |
| 444 | clock-output-names = "mmc0"; | |
| 445 | }; | |
| 446 | mmc1_clk: mmc1_clk@e6150244 { | |
| 447 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
| 448 | reg = <0 0xe6150244 0 4>; | |
| 449 | clocks = <&pll1_div2_clk>; | |
| 450 | #clock-cells = <0>; | |
| 451 | clock-output-names = "mmc1"; | |
| 452 | }; | |
| 453 | ssp_clk: ssp_clk@e6150248 { | |
| 454 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
| 455 | reg = <0 0xe6150248 0 4>; | |
| 456 | clocks = <&pll1_div2_clk>; | |
| 457 | #clock-cells = <0>; | |
| 458 | clock-output-names = "ssp"; | |
| 459 | }; | |
| 460 | ssprs_clk: ssprs_clk@e615024c { | |
| 461 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
| 462 | reg = <0 0xe615024c 0 4>; | |
| 463 | clocks = <&pll1_div2_clk>; | |
| 464 | #clock-cells = <0>; | |
| 465 | clock-output-names = "ssprs"; | |
| 466 | }; | |
| 467 | ||
| 468 | /* Fixed factor clocks */ | |
| 469 | pll1_div2_clk: pll1_div2_clk { | |
| 470 | compatible = "fixed-factor-clock"; | |
| 471 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 472 | #clock-cells = <0>; | |
| 473 | clock-div = <2>; | |
| 474 | clock-mult = <1>; | |
| 475 | clock-output-names = "pll1_div2"; | |
| 476 | }; | |
| 477 | z2_clk: z2_clk { | |
| 478 | compatible = "fixed-factor-clock"; | |
| 479 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 480 | #clock-cells = <0>; | |
| 481 | clock-div = <2>; | |
| 482 | clock-mult = <1>; | |
| 483 | clock-output-names = "z2"; | |
| 484 | }; | |
| 485 | zg_clk: zg_clk { | |
| 486 | compatible = "fixed-factor-clock"; | |
| 487 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 488 | #clock-cells = <0>; | |
| 489 | clock-div = <3>; | |
| 490 | clock-mult = <1>; | |
| 491 | clock-output-names = "zg"; | |
| 492 | }; | |
| 493 | zx_clk: zx_clk { | |
| 494 | compatible = "fixed-factor-clock"; | |
| 495 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 496 | #clock-cells = <0>; | |
| 497 | clock-div = <3>; | |
| 498 | clock-mult = <1>; | |
| 499 | clock-output-names = "zx"; | |
| 500 | }; | |
| 501 | zs_clk: zs_clk { | |
| 502 | compatible = "fixed-factor-clock"; | |
| 503 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 504 | #clock-cells = <0>; | |
| 505 | clock-div = <6>; | |
| 506 | clock-mult = <1>; | |
| 507 | clock-output-names = "zs"; | |
| 508 | }; | |
| 509 | hp_clk: hp_clk { | |
| 510 | compatible = "fixed-factor-clock"; | |
| 511 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 512 | #clock-cells = <0>; | |
| 513 | clock-div = <12>; | |
| 514 | clock-mult = <1>; | |
| 515 | clock-output-names = "hp"; | |
| 516 | }; | |
| 517 | i_clk: i_clk { | |
| 518 | compatible = "fixed-factor-clock"; | |
| 519 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 520 | #clock-cells = <0>; | |
| 521 | clock-div = <2>; | |
| 522 | clock-mult = <1>; | |
| 523 | clock-output-names = "i"; | |
| 524 | }; | |
| 525 | b_clk: b_clk { | |
| 526 | compatible = "fixed-factor-clock"; | |
| 527 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 528 | #clock-cells = <0>; | |
| 529 | clock-div = <12>; | |
| 530 | clock-mult = <1>; | |
| 531 | clock-output-names = "b"; | |
| 532 | }; | |
| 533 | p_clk: p_clk { | |
| 534 | compatible = "fixed-factor-clock"; | |
| 535 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 536 | #clock-cells = <0>; | |
| 537 | clock-div = <24>; | |
| 538 | clock-mult = <1>; | |
| 539 | clock-output-names = "p"; | |
| 540 | }; | |
| 541 | cl_clk: cl_clk { | |
| 542 | compatible = "fixed-factor-clock"; | |
| 543 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 544 | #clock-cells = <0>; | |
| 545 | clock-div = <48>; | |
| 546 | clock-mult = <1>; | |
| 547 | clock-output-names = "cl"; | |
| 548 | }; | |
| 549 | m2_clk: m2_clk { | |
| 550 | compatible = "fixed-factor-clock"; | |
| 551 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 552 | #clock-cells = <0>; | |
| 553 | clock-div = <8>; | |
| 554 | clock-mult = <1>; | |
| 555 | clock-output-names = "m2"; | |
| 556 | }; | |
| 557 | imp_clk: imp_clk { | |
| 558 | compatible = "fixed-factor-clock"; | |
| 559 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 560 | #clock-cells = <0>; | |
| 561 | clock-div = <4>; | |
| 562 | clock-mult = <1>; | |
| 563 | clock-output-names = "imp"; | |
| 564 | }; | |
| 565 | rclk_clk: rclk_clk { | |
| 566 | compatible = "fixed-factor-clock"; | |
| 567 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 568 | #clock-cells = <0>; | |
| 569 | clock-div = <(48 * 1024)>; | |
| 570 | clock-mult = <1>; | |
| 571 | clock-output-names = "rclk"; | |
| 572 | }; | |
| 573 | oscclk_clk: oscclk_clk { | |
| 574 | compatible = "fixed-factor-clock"; | |
| 575 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 576 | #clock-cells = <0>; | |
| 577 | clock-div = <(12 * 1024)>; | |
| 578 | clock-mult = <1>; | |
| 579 | clock-output-names = "oscclk"; | |
| 580 | }; | |
| 581 | zb3_clk: zb3_clk { | |
| 582 | compatible = "fixed-factor-clock"; | |
| 583 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
| 584 | #clock-cells = <0>; | |
| 585 | clock-div = <4>; | |
| 586 | clock-mult = <1>; | |
| 587 | clock-output-names = "zb3"; | |
| 588 | }; | |
| 589 | zb3d2_clk: zb3d2_clk { | |
| 590 | compatible = "fixed-factor-clock"; | |
| 591 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
| 592 | #clock-cells = <0>; | |
| 593 | clock-div = <8>; | |
| 594 | clock-mult = <1>; | |
| 595 | clock-output-names = "zb3d2"; | |
| 596 | }; | |
| 597 | ddr_clk: ddr_clk { | |
| 598 | compatible = "fixed-factor-clock"; | |
| 599 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
| 600 | #clock-cells = <0>; | |
| 601 | clock-div = <8>; | |
| 602 | clock-mult = <1>; | |
| 603 | clock-output-names = "ddr"; | |
| 604 | }; | |
| 605 | mp_clk: mp_clk { | |
| 606 | compatible = "fixed-factor-clock"; | |
| 607 | clocks = <&pll1_div2_clk>; | |
| 608 | #clock-cells = <0>; | |
| 609 | clock-div = <15>; | |
| 610 | clock-mult = <1>; | |
| 611 | clock-output-names = "mp"; | |
| 612 | }; | |
| 613 | cp_clk: cp_clk { | |
| 614 | compatible = "fixed-factor-clock"; | |
| 615 | clocks = <&extal_clk>; | |
| 616 | #clock-cells = <0>; | |
| 617 | clock-div = <2>; | |
| 618 | clock-mult = <1>; | |
| 619 | clock-output-names = "cp"; | |
| 620 | }; | |
| 621 | ||
| 622 | /* Gate clocks */ | |
| 9d90951a LP |
623 | mstp0_clks: mstp0_clks@e6150130 { |
| 624 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 625 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
| 626 | clocks = <&mp_clk>; | |
| 627 | #clock-cells = <1>; | |
| 628 | renesas,clock-indices = <R8A7790_CLK_MSIOF0>; | |
| 629 | clock-output-names = "msiof0"; | |
| 630 | }; | |
| 22a1f595 LP |
631 | mstp1_clks: mstp1_clks@e6150134 { |
| 632 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 633 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
| 634 | clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, | |
| 635 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, | |
| 636 | <&zs_clk>; | |
| 637 | #clock-cells = <1>; | |
| 638 | renesas,clock-indices = < | |
| 639 | R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 | |
| 640 | R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 | |
| 641 | R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY | |
| 642 | >; | |
| 643 | clock-output-names = | |
| 644 | "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", | |
| 645 | "vsp1-du0", "vsp1-rt", "vsp1-sy"; | |
| 646 | }; | |
| 647 | mstp2_clks: mstp2_clks@e6150138 { | |
| 648 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 649 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
| 650 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
| 9d90951a | 651 | <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; |
| 22a1f595 LP |
652 | #clock-cells = <1>; |
| 653 | renesas,clock-indices = < | |
| 654 | R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 | |
| 9d90951a LP |
655 | R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 |
| 656 | R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 | |
| 22a1f595 LP |
657 | >; |
| 658 | clock-output-names = | |
| 9d90951a LP |
659 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
| 660 | "scifb1", "msiof1", "msiof3", "scifb2"; | |
| 22a1f595 LP |
661 | }; |
| 662 | mstp3_clks: mstp3_clks@e615013c { | |
| 663 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 664 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
| 665 | clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, | |
| 666 | <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, | |
| 667 | <&mmc0_clk>, <&rclk_clk>; | |
| 668 | #clock-cells = <1>; | |
| 669 | renesas,clock-indices = < | |
| 670 | R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 | |
| 671 | R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 | |
| 672 | R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1 | |
| 673 | >; | |
| 674 | clock-output-names = | |
| 675 | "tpu0", "mmcif1", "sdhi3", "sdhi2", | |
| 676 | "sdhi1", "sdhi0", "mmcif0", "cmt1"; | |
| 677 | }; | |
| 678 | mstp5_clks: mstp5_clks@e6150144 { | |
| 679 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 680 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
| 681 | clocks = <&extal_clk>, <&p_clk>; | |
| 682 | #clock-cells = <1>; | |
| 683 | renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; | |
| 684 | clock-output-names = "thermal", "pwm"; | |
| 685 | }; | |
| 686 | mstp7_clks: mstp7_clks@e615014c { | |
| 687 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 688 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
| 689 | clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, | |
| 690 | <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, | |
| 691 | <&zx_clk>; | |
| 692 | #clock-cells = <1>; | |
| 693 | renesas,clock-indices = < | |
| 694 | R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 | |
| 695 | R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 | |
| 696 | R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 | |
| 697 | R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 | |
| 698 | >; | |
| 699 | clock-output-names = | |
| 700 | "ehci", "hsusb", "hscif1", "hscif0", "scif1", | |
| 701 | "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; | |
| 702 | }; | |
| 703 | mstp8_clks: mstp8_clks@e6150990 { | |
| 704 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 705 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
| bccccc3d LP |
706 | clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, |
| 707 | <&zs_clk>, <&zs_clk>; | |
| 22a1f595 | 708 | #clock-cells = <1>; |
| 3f2beaa9 LP |
709 | renesas,clock-indices = < |
| 710 | R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 | |
| bccccc3d LP |
711 | R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 |
| 712 | R8A7790_CLK_SATA0 | |
| 3f2beaa9 | 713 | >; |
| bccccc3d LP |
714 | clock-output-names = |
| 715 | "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; | |
| 22a1f595 LP |
716 | }; |
| 717 | mstp9_clks: mstp9_clks@e6150994 { | |
| 718 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 719 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
| 91b56ca1 LP |
720 | clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, |
| 721 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; | |
| 22a1f595 LP |
722 | #clock-cells = <1>; |
| 723 | renesas,clock-indices = < | |
| 91b56ca1 LP |
724 | R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD |
| 725 | R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 | |
| 726 | R8A7790_CLK_I2C0 | |
| 22a1f595 | 727 | >; |
| 91b56ca1 LP |
728 | clock-output-names = |
| 729 | "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; | |
| 22a1f595 LP |
730 | }; |
| 731 | }; | |
| 7053e134 GU |
732 | |
| 733 | spi: spi@e6b10000 { | |
| 734 | compatible = "renesas,qspi-r8a7790", "renesas,qspi"; | |
| 735 | reg = <0 0xe6b10000 0 0x2c>; | |
| 7053e134 GU |
736 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
| 737 | clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; | |
| 738 | num-cs = <1>; | |
| 739 | #address-cells = <1>; | |
| 740 | #size-cells = <0>; | |
| 741 | status = "disabled"; | |
| 742 | }; | |
| 0468b2d6 | 743 | }; |