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ARM: dts: r8a7791: use fallback jpu compatibility string
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / r8a7790.dtsi
CommitLineData
0468b2d6
MD		 1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
b621f6d4 4 * Copyright (C) 2015 Renesas Electronics Corporation
d8913c67
SS		 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
0468b2d6
MD		 7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
22a1f595 13#include <dt-bindings/clock/r8a7790-clock.h>
5f75e73c
LP		 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
0468b2d6
MD		 17/ {
18 compatible = "renesas,r8a7790";
19 interrupt-parent = <&gic>;
8585deb1
TY		 20 #address-cells = <2>;
21 #size-cells = <2>;
0468b2d6 22
6b1d7c68
WS		 23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
05f39916
WS		 28 i2c4 = &iic0;
29 i2c5 = &iic1;
30 i2c6 = &iic2;
31 i2c7 = &iic3;
fad6d45c 32 spi0 = &qspi;
ae8a6146
GU		 33 spi1 = &msiof0;
34 spi2 = &msiof1;
35 spi3 = &msiof2;
36 spi4 = &msiof3;
9f685bfc
BD		 37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
40 vin3 = &vin3;
6b1d7c68
WS		 41 };
42
0468b2d6
MD		 43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0>;
51 clock-frequency = <1300000000>;
b989e138
BC		 52 voltage-tolerance = <1>; /* 1% */
53 clocks = <&cpg_clocks R8A7790_CLK_Z>;
54 clock-latency = <300000>; /* 300 us */
fb1cecd4 55 next-level-cache = <&L2_CA15>;
b989e138
BC		 56
57 /* kHz - uV - OPPs unknown yet */
58 operating-points = <1400000 1000000>,
59 <1225000 1000000>,
60 <1050000 1000000>,
61 < 875000 1000000>,
62 < 700000 1000000>,
63 < 350000 1000000>;
0468b2d6 64 };
c1f95979
MD		 65
66 cpu1: cpu@1 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a15";
69 reg = <1>;
70 clock-frequency = <1300000000>;
fb1cecd4 71 next-level-cache = <&L2_CA15>;
c1f95979
MD		 72 };
73
74 cpu2: cpu@2 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a15";
77 reg = <2>;
78 clock-frequency = <1300000000>;
fb1cecd4 79 next-level-cache = <&L2_CA15>;
c1f95979
MD		 80 };
81
82 cpu3: cpu@3 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <3>;
86 clock-frequency = <1300000000>;
fb1cecd4 87 next-level-cache = <&L2_CA15>;
c1f95979 88 };
2007e74c
MD		 89
90 cpu4: cpu@4 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a7";
93 reg = <0x100>;
94 clock-frequency = <780000000>;
fb1cecd4 95 next-level-cache = <&L2_CA7>;
2007e74c
MD		 96 };
97
98 cpu5: cpu@5 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a7";
101 reg = <0x101>;
102 clock-frequency = <780000000>;
fb1cecd4 103 next-level-cache = <&L2_CA7>;
2007e74c
MD		 104 };
105
106 cpu6: cpu@6 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a7";
109 reg = <0x102>;
110 clock-frequency = <780000000>;
fb1cecd4 111 next-level-cache = <&L2_CA7>;
2007e74c
MD		 112 };
113
114 cpu7: cpu@7 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a7";
117 reg = <0x103>;
118 clock-frequency = <780000000>;
fb1cecd4 119 next-level-cache = <&L2_CA7>;
2007e74c 120 };
0468b2d6
MD		 121 };
122
a8b805f3
KM		 123 thermal-zones {
124 cpu_thermal: cpu-thermal {
125 polling-delay-passive = <0>;
126 polling-delay = <0>;
127
128 thermal-sensors = <&thermal>;
129
130 trips {
131 cpu-crit {
132 temperature = <115000>;
133 hysteresis = <0>;
134 type = "critical";
135 };
136 };
137 cooling-maps {
138 };
139 };
140 };
141
fb1cecd4
GU		 142 L2_CA15: cache-controller@0 {
143 compatible = "cache";
144 cache-unified;
145 cache-level = <2>;
146 };
147
148 L2_CA7: cache-controller@1 {
149 compatible = "cache";
150 cache-unified;
151 cache-level = <2>;
152 };
153
0468b2d6 154 gic: interrupt-controller@f1001000 {
e715e9c5 155 compatible = "arm,gic-400";
0468b2d6
MD		 156 #interrupt-cells = <3>;
157 #address-cells = <0>;
158 interrupt-controller;
8585deb1
TY		 159 reg = <0 0xf1001000 0 0x1000>,
160 <0 0xf1002000 0 0x1000>,
161 <0 0xf1004000 0 0x2000>,
162 <0 0xf1006000 0 0x2000>;
3abb4d5f 163 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0468b2d6
MD		 164 };
165
23de2278 166 gpio0: gpio@e6050000 {
f98e10c8 167 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 168 reg = <0 0xe6050000 0 0x50>;
3abb4d5f 169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 170 #gpio-cells = <2>;
171 gpio-controller;
172 gpio-ranges = <&pfc 0 0 32>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
81f6883f 175 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
484adb00 176 power-domains = <&cpg_clocks>;
f98e10c8
LP		 177 };
178
23de2278 179 gpio1: gpio@e6051000 {
f98e10c8 180 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 181 reg = <0 0xe6051000 0 0x50>;
3abb4d5f 182 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 183 #gpio-cells = <2>;
184 gpio-controller;
56a2182f 185 gpio-ranges = <&pfc 0 32 30>;
f98e10c8
LP		 186 #interrupt-cells = <2>;
187 interrupt-controller;
81f6883f 188 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
484adb00 189 power-domains = <&cpg_clocks>;
f98e10c8
LP		 190 };
191
23de2278 192 gpio2: gpio@e6052000 {
f98e10c8 193 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 194 reg = <0 0xe6052000 0 0x50>;
3abb4d5f 195 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 196 #gpio-cells = <2>;
197 gpio-controller;
56a2182f 198 gpio-ranges = <&pfc 0 64 30>;
f98e10c8
LP		 199 #interrupt-cells = <2>;
200 interrupt-controller;
81f6883f 201 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
484adb00 202 power-domains = <&cpg_clocks>;
f98e10c8
LP		 203 };
204
23de2278 205 gpio3: gpio@e6053000 {
f98e10c8 206 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 207 reg = <0 0xe6053000 0 0x50>;
3abb4d5f 208 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 209 #gpio-cells = <2>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 96 32>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
81f6883f 214 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
484adb00 215 power-domains = <&cpg_clocks>;
f98e10c8
LP		 216 };
217
23de2278 218 gpio4: gpio@e6054000 {
f98e10c8 219 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 220 reg = <0 0xe6054000 0 0x50>;
3abb4d5f 221 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 222 #gpio-cells = <2>;
223 gpio-controller;
224 gpio-ranges = <&pfc 0 128 32>;
225 #interrupt-cells = <2>;
226 interrupt-controller;
81f6883f 227 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
484adb00 228 power-domains = <&cpg_clocks>;
f98e10c8
LP		 229 };
230
23de2278 231 gpio5: gpio@e6055000 {
f98e10c8 232 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 233 reg = <0 0xe6055000 0 0x50>;
3abb4d5f 234 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 235 #gpio-cells = <2>;
236 gpio-controller;
237 gpio-ranges = <&pfc 0 160 32>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
81f6883f 240 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
484adb00 241 power-domains = <&cpg_clocks>;
f98e10c8
LP		 242 };
243
a8b805f3
KM		 244 thermal: thermal@e61f0000 {
245 compatible = "renesas,thermal-r8a7790",
246 "renesas,rcar-gen2-thermal",
247 "renesas,rcar-thermal";
03e2f56b 248 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
3abb4d5f 249 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
d3a439db 250 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
484adb00 251 power-domains = <&cpg_clocks>;
a8b805f3 252 #thermal-sensor-cells = <0>;
03e2f56b
MD		 253 };
254
0468b2d6
MD		 255 timer {
256 compatible = "arm,armv7-timer";
3abb4d5f
SH		 257 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
258 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
259 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
260 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0468b2d6 261 };
8f5ec0a5 262
39cf6d73 263 cmt0: timer@ffca0000 {
37757030 264 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
39cf6d73 265 reg = <0 0xffca0000 0 0x1004>;
3abb4d5f
SH		 266 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
39cf6d73
LP		 268 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
269 clock-names = "fck";
484adb00 270 power-domains = <&cpg_clocks>;
39cf6d73
LP		 271
272 renesas,channels-mask = <0x60>;
273
274 status = "disabled";
275 };
276
277 cmt1: timer@e6130000 {
37757030 278 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
39cf6d73 279 reg = <0 0xe6130000 0 0x1004>;
3abb4d5f
SH		 280 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
39cf6d73
LP		 288 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
289 clock-names = "fck";
484adb00 290 power-domains = <&cpg_clocks>;
39cf6d73
LP		 291
292 renesas,channels-mask = <0xff>;
293
294 status = "disabled";
295 };
296
8f5ec0a5 297 irqc0: interrupt-controller@e61c0000 {
220fc352 298 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
8f5ec0a5
MD		 299 #interrupt-cells = <2>;
300 interrupt-controller;
8585deb1 301 reg = <0 0xe61c0000 0 0x200>;
3abb4d5f
SH		 302 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
61624caf 306 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
484adb00 307 power-domains = <&cpg_clocks>;
8f5ec0a5 308 };
8c9b1aa4 309
b9fea49c 310 dmac0: dma-controller@e6700000 {
4af0a664 311 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
b9fea49c 312 reg = <0 0xe6700000 0 0x20000>;
3abb4d5f
SH		 313 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
b9fea49c
LP		 329 interrupt-names = "error",
330 "ch0", "ch1", "ch2", "ch3",
331 "ch4", "ch5", "ch6", "ch7",
332 "ch8", "ch9", "ch10", "ch11",
333 "ch12", "ch13", "ch14";
334 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
335 clock-names = "fck";
484adb00 336 power-domains = <&cpg_clocks>;
b9fea49c
LP		 337 #dma-cells = <1>;
338 dma-channels = <15>;
339 };
340
341 dmac1: dma-controller@e6720000 {
4af0a664 342 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
b9fea49c 343 reg = <0 0xe6720000 0 0x20000>;
3abb4d5f
SH		 344 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
b9fea49c
LP		 360 interrupt-names = "error",
361 "ch0", "ch1", "ch2", "ch3",
362 "ch4", "ch5", "ch6", "ch7",
363 "ch8", "ch9", "ch10", "ch11",
364 "ch12", "ch13", "ch14";
365 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
366 clock-names = "fck";
484adb00 367 power-domains = <&cpg_clocks>;
b9fea49c
LP		 368 #dma-cells = <1>;
369 dma-channels = <15>;
370 };
ba3240be
KM		 371
372 audma0: dma-controller@ec700000 {
4af0a664 373 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
ba3240be 374 reg = <0 0xec700000 0 0x10000>;
3abb4d5f
SH		 375 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
ba3240be
KM		 389 interrupt-names = "error",
390 "ch0", "ch1", "ch2", "ch3",
391 "ch4", "ch5", "ch6", "ch7",
392 "ch8", "ch9", "ch10", "ch11",
393 "ch12";
394 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
395 clock-names = "fck";
484adb00 396 power-domains = <&cpg_clocks>;
ba3240be
KM		 397 #dma-cells = <1>;
398 dma-channels = <13>;
399 };
400
401 audma1: dma-controller@ec720000 {
4af0a664 402 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
ba3240be 403 reg = <0 0xec720000 0 0x10000>;
3abb4d5f
SH		 404 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
405 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
406 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
407 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
408 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
409 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
410 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
412 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
413 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
415 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
ba3240be
KM		 418 interrupt-names = "error",
419 "ch0", "ch1", "ch2", "ch3",
420 "ch4", "ch5", "ch6", "ch7",
421 "ch8", "ch9", "ch10", "ch11",
422 "ch12";
423 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
424 clock-names = "fck";
484adb00 425 power-domains = <&cpg_clocks>;
ba3240be
KM		 426 #dma-cells = <1>;
427 dma-channels = <13>;
428 };
429
a3ff2090 430 usb_dmac0: dma-controller@e65a0000 {
d01c8bec 431 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
a3ff2090 432 reg = <0 0xe65a0000 0 0x100>;
3abb4d5f
SH		 433 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
434 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
a3ff2090
YS		 435 interrupt-names = "ch0", "ch1";
436 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
484adb00 437 power-domains = <&cpg_clocks>;
a3ff2090
YS		 438 #dma-cells = <1>;
439 dma-channels = <2>;
440 };
441
442 usb_dmac1: dma-controller@e65b0000 {
d01c8bec 443 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
a3ff2090 444 reg = <0 0xe65b0000 0 0x100>;
3abb4d5f
SH		 445 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
446 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
a3ff2090
YS		 447 interrupt-names = "ch0", "ch1";
448 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
484adb00 449 power-domains = <&cpg_clocks>;
a3ff2090
YS		 450 #dma-cells = <1>;
451 dma-channels = <2>;
452 };
453
edd2b9f4
GL		 454 i2c0: i2c@e6508000 {
455 #address-cells = <1>;
456 #size-cells = <0>;
457 compatible = "renesas,i2c-r8a7790";
458 reg = <0 0xe6508000 0 0x40>;
3abb4d5f 459 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2450badf 460 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
484adb00 461 power-domains = <&cpg_clocks>;
ac8e7f31 462 i2c-scl-internal-delay-ns = <110>;
edd2b9f4
GL		 463 status = "disabled";
464 };
465
466 i2c1: i2c@e6518000 {
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "renesas,i2c-r8a7790";
470 reg = <0 0xe6518000 0 0x40>;
3abb4d5f 471 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
2450badf 472 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
484adb00 473 power-domains = <&cpg_clocks>;
ac8e7f31 474 i2c-scl-internal-delay-ns = <6>;
edd2b9f4
GL		 475 status = "disabled";
476 };
477
478 i2c2: i2c@e6530000 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 compatible = "renesas,i2c-r8a7790";
482 reg = <0 0xe6530000 0 0x40>;
3abb4d5f 483 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
2450badf 484 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
484adb00 485 power-domains = <&cpg_clocks>;
ac8e7f31 486 i2c-scl-internal-delay-ns = <6>;
edd2b9f4
GL		 487 status = "disabled";
488 };
489
490 i2c3: i2c@e6540000 {
491 #address-cells = <1>;
492 #size-cells = <0>;
493 compatible = "renesas,i2c-r8a7790";
494 reg = <0 0xe6540000 0 0x40>;
3abb4d5f 495 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
2450badf 496 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
484adb00 497 power-domains = <&cpg_clocks>;
ac8e7f31 498 i2c-scl-internal-delay-ns = <110>;
edd2b9f4
GL		 499 status = "disabled";
500 };
501
05f39916
WS		 502 iic0: i2c@e6500000 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
506 reg = <0 0xe6500000 0 0x425>;
3abb4d5f 507 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
05f39916 508 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
0d73ca41
WS		 509 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
510 dma-names = "tx", "rx";
484adb00 511 power-domains = <&cpg_clocks>;
05f39916
WS		 512 status = "disabled";
513 };
514
515 iic1: i2c@e6510000 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
519 reg = <0 0xe6510000 0 0x425>;
3abb4d5f 520 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
05f39916 521 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
0d73ca41
WS		 522 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
523 dma-names = "tx", "rx";
484adb00 524 power-domains = <&cpg_clocks>;
05f39916
WS		 525 status = "disabled";
526 };
527
528 iic2: i2c@e6520000 {
529 #address-cells = <1>;
530 #size-cells = <0>;
531 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
532 reg = <0 0xe6520000 0 0x425>;
3abb4d5f 533 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
05f39916 534 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
0d73ca41
WS		 535 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
536 dma-names = "tx", "rx";
484adb00 537 power-domains = <&cpg_clocks>;
05f39916
WS		 538 status = "disabled";
539 };
540
541 iic3: i2c@e60b0000 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
545 reg = <0 0xe60b0000 0 0x425>;
3abb4d5f 546 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
05f39916 547 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
0d73ca41
WS		 548 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
549 dma-names = "tx", "rx";
484adb00 550 power-domains = <&cpg_clocks>;
05f39916
WS		 551 status = "disabled";
552 };
553
22c2b78d 554 mmcif0: mmc@ee200000 {
063e8560 555 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 556 reg = <0 0xee200000 0 0x80>;
3abb4d5f 557 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 558 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
108216c1
LP		 559 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
560 dma-names = "tx", "rx";
484adb00 561 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 562 reg-io-width = <4>;
563 status = "disabled";
96370057 564 max-frequency = <97500000>;
8c9b1aa4
GL		 565 };
566
b718aa44 567 mmcif1: mmc@ee220000 {
063e8560 568 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 569 reg = <0 0xee220000 0 0x80>;
3abb4d5f 570 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 571 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
108216c1
LP		 572 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
573 dma-names = "tx", "rx";
484adb00 574 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 575 reg-io-width = <4>;
576 status = "disabled";
96370057 577 max-frequency = <97500000>;
8c9b1aa4
GL		 578 };
579
9694c778
LP		 580 pfc: pfc@e6060000 {
581 compatible = "renesas,pfc-r8a7790";
582 reg = <0 0xe6060000 0 0x250>;
583 };
55689bfa 584
b718aa44 585 sdhi0: sd@ee100000 {
df1d0584 586 compatible = "renesas,sdhi-r8a7790";
66f47ed0 587 reg = <0 0xee100000 0 0x328>;
3abb4d5f 588 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 589 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
941fe36b
LP		 590 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
591 dma-names = "tx", "rx";
484adb00 592 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 593 status = "disabled";
594 };
595
b718aa44 596 sdhi1: sd@ee120000 {
df1d0584 597 compatible = "renesas,sdhi-r8a7790";
66f47ed0 598 reg = <0 0xee120000 0 0x328>;
3abb4d5f 599 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 600 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
941fe36b
LP		 601 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
602 dma-names = "tx", "rx";
484adb00 603 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 604 status = "disabled";
605 };
606
b718aa44 607 sdhi2: sd@ee140000 {
df1d0584 608 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 609 reg = <0 0xee140000 0 0x100>;
3abb4d5f 610 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 611 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
941fe36b
LP		 612 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
613 dma-names = "tx", "rx";
484adb00 614 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 615 status = "disabled";
616 };
617
b718aa44 618 sdhi3: sd@ee160000 {
df1d0584 619 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 620 reg = <0 0xee160000 0 0x100>;
3abb4d5f 621 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 622 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
941fe36b
LP		 623 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
624 dma-names = "tx", "rx";
484adb00 625 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 626 status = "disabled";
627 };
22a1f595 628
597af20f 629 scifa0: serial@e6c40000 {
a20dc9f2
GU		 630 compatible = "renesas,scifa-r8a7790",
631 "renesas,rcar-gen2-scifa", "renesas,scifa";
597af20f 632 reg = <0 0xe6c40000 0 64>;
3abb4d5f 633 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
597af20f 634 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
6c6e12a1 635 clock-names = "fck";
acea43fc
GU		 636 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
637 dma-names = "tx", "rx";
484adb00 638 power-domains = <&cpg_clocks>;
597af20f
LP		 639 status = "disabled";
640 };
641
642 scifa1: serial@e6c50000 {
a20dc9f2
GU		 643 compatible = "renesas,scifa-r8a7790",
644 "renesas,rcar-gen2-scifa", "renesas,scifa";
597af20f 645 reg = <0 0xe6c50000 0 64>;
3abb4d5f 646 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
597af20f 647 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
6c6e12a1 648 clock-names = "fck";
acea43fc
GU		 649 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
650 dma-names = "tx", "rx";
484adb00 651 power-domains = <&cpg_clocks>;
597af20f
LP		 652 status = "disabled";
653 };
654
655 scifa2: serial@e6c60000 {
a20dc9f2
GU		 656 compatible = "renesas,scifa-r8a7790",
657 "renesas,rcar-gen2-scifa", "renesas,scifa";
597af20f 658 reg = <0 0xe6c60000 0 64>;
3abb4d5f 659 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
597af20f 660 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
6c6e12a1 661 clock-names = "fck";
acea43fc
GU		 662 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
663 dma-names = "tx", "rx";
484adb00 664 power-domains = <&cpg_clocks>;
597af20f
LP		 665 status = "disabled";
666 };
667
668 scifb0: serial@e6c20000 {
a20dc9f2
GU		 669 compatible = "renesas,scifb-r8a7790",
670 "renesas,rcar-gen2-scifb", "renesas,scifb";
597af20f 671 reg = <0 0xe6c20000 0 64>;
3abb4d5f 672 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
597af20f 673 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
6c6e12a1 674 clock-names = "fck";
acea43fc
GU		 675 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
676 dma-names = "tx", "rx";
484adb00 677 power-domains = <&cpg_clocks>;
597af20f
LP		 678 status = "disabled";
679 };
680
681 scifb1: serial@e6c30000 {
a20dc9f2
GU		 682 compatible = "renesas,scifb-r8a7790",
683 "renesas,rcar-gen2-scifb", "renesas,scifb";
597af20f 684 reg = <0 0xe6c30000 0 64>;
3abb4d5f 685 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
597af20f 686 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
6c6e12a1 687 clock-names = "fck";
acea43fc
GU		 688 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
689 dma-names = "tx", "rx";
484adb00 690 power-domains = <&cpg_clocks>;
597af20f
LP		 691 status = "disabled";
692 };
693
694 scifb2: serial@e6ce0000 {
a20dc9f2
GU		 695 compatible = "renesas,scifb-r8a7790",
696 "renesas,rcar-gen2-scifb", "renesas,scifb";
597af20f 697 reg = <0 0xe6ce0000 0 64>;
3abb4d5f 698 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
597af20f 699 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
6c6e12a1 700 clock-names = "fck";
acea43fc
GU		 701 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
702 dma-names = "tx", "rx";
484adb00 703 power-domains = <&cpg_clocks>;
597af20f
LP		 704 status = "disabled";
705 };
706
707 scif0: serial@e6e60000 {
a20dc9f2
GU		 708 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
709 "renesas,scif";
597af20f 710 reg = <0 0xe6e60000 0 64>;
3abb4d5f 711 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
42af65e8
GU		 712 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
713 <&scif_clk>;
714 clock-names = "fck", "brg_int", "scif_clk";
acea43fc
GU		 715 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
716 dma-names = "tx", "rx";
484adb00 717 power-domains = <&cpg_clocks>;
597af20f
LP		 718 status = "disabled";
719 };
720
721 scif1: serial@e6e68000 {
a20dc9f2
GU		 722 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
723 "renesas,scif";
597af20f 724 reg = <0 0xe6e68000 0 64>;
3abb4d5f 725 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
42af65e8
GU		 726 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
727 <&scif_clk>;
728 clock-names = "fck", "brg_int", "scif_clk";
acea43fc
GU		 729 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
730 dma-names = "tx", "rx";
484adb00 731 power-domains = <&cpg_clocks>;
597af20f
LP		 732 status = "disabled";
733 };
734
735 hscif0: serial@e62c0000 {
a20dc9f2
GU		 736 compatible = "renesas,hscif-r8a7790",
737 "renesas,rcar-gen2-hscif", "renesas,hscif";
597af20f 738 reg = <0 0xe62c0000 0 96>;
3abb4d5f 739 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
42af65e8
GU		 740 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
741 <&scif_clk>;
742 clock-names = "fck", "brg_int", "scif_clk";
acea43fc
GU		 743 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
744 dma-names = "tx", "rx";
484adb00 745 power-domains = <&cpg_clocks>;
597af20f
LP		 746 status = "disabled";
747 };
748
749 hscif1: serial@e62c8000 {
a20dc9f2
GU		 750 compatible = "renesas,hscif-r8a7790",
751 "renesas,rcar-gen2-hscif", "renesas,hscif";
597af20f 752 reg = <0 0xe62c8000 0 96>;
3abb4d5f 753 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
42af65e8
GU		 754 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
755 <&scif_clk>;
756 clock-names = "fck", "brg_int", "scif_clk";
acea43fc
GU		 757 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
758 dma-names = "tx", "rx";
484adb00 759 power-domains = <&cpg_clocks>;
597af20f
LP		 760 status = "disabled";
761 };
762
d8913c67
SS		 763 ether: ethernet@ee700000 {
764 compatible = "renesas,ether-r8a7790";
765 reg = <0 0xee700000 0 0x400>;
3abb4d5f 766 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
d8913c67 767 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
484adb00 768 power-domains = <&cpg_clocks>;
d8913c67
SS		 769 phy-mode = "rmii";
770 #address-cells = <1>;
771 #size-cells = <0>;
772 status = "disabled";
773 };
774
f25d6b97 775 avb: ethernet@e6800000 {
d92df7e5
SH		 776 compatible = "renesas,etheravb-r8a7790",
777 "renesas,etheravb-rcar-gen2";
f25d6b97 778 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
3abb4d5f 779 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
f25d6b97 780 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
484adb00 781 power-domains = <&cpg_clocks>;
f25d6b97
SS		 782 #address-cells = <1>;
783 #size-cells = <0>;
784 status = "disabled";
785 };
786
cde630f7
VB		 787 sata0: sata@ee300000 {
788 compatible = "renesas,sata-r8a7790";
789 reg = <0 0xee300000 0 0x2000>;
3abb4d5f 790 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
cde630f7 791 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
484adb00 792 power-domains = <&cpg_clocks>;
cde630f7
VB		 793 status = "disabled";
794 };
795
796 sata1: sata@ee500000 {
797 compatible = "renesas,sata-r8a7790";
798 reg = <0 0xee500000 0 0x2000>;
3abb4d5f 799 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
cde630f7 800 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
484adb00 801 power-domains = <&cpg_clocks>;
cde630f7
VB		 802 status = "disabled";
803 };
804
ae0a555b 805 hsusb: usb@e6590000 {
d87ec94a 806 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
ae0a555b 807 reg = <0 0xe6590000 0 0x100>;
3abb4d5f 808 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
ae0a555b 809 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
e8295dc3
YS		 810 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
811 <&usb_dmac1 0>, <&usb_dmac1 1>;
812 dma-names = "ch0", "ch1", "ch2", "ch3";
484adb00
GU		 813 power-domains = <&cpg_clocks>;
814 renesas,buswait = <4>;
815 phys = <&usb0 1>;
816 phy-names = "usb";
ae0a555b
YS		 817 status = "disabled";
818 };
819
e089f657
SS		 820 usbphy: usb-phy@e6590100 {
821 compatible = "renesas,usb-phy-r8a7790";
822 reg = <0 0xe6590100 0 0x100>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
826 clock-names = "usbhs";
484adb00 827 power-domains = <&cpg_clocks>;
e089f657
SS		 828 status = "disabled";
829
830 usb0: usb-channel@0 {
831 reg = <0>;
832 #phy-cells = <1>;
833 };
834 usb2: usb-channel@2 {
835 reg = <2>;
836 #phy-cells = <1>;
837 };
838 };
839
9f685bfc
BD		 840 vin0: video@e6ef0000 {
841 compatible = "renesas,vin-r8a7790";
9f685bfc 842 reg = <0 0xe6ef0000 0 0x1000>;
3abb4d5f 843 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 844 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
845 power-domains = <&cpg_clocks>;
9f685bfc
BD		 846 status = "disabled";
847 };
848
849 vin1: video@e6ef1000 {
850 compatible = "renesas,vin-r8a7790";
9f685bfc 851 reg = <0 0xe6ef1000 0 0x1000>;
3abb4d5f 852 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 853 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
854 power-domains = <&cpg_clocks>;
9f685bfc
BD		 855 status = "disabled";
856 };
857
858 vin2: video@e6ef2000 {
859 compatible = "renesas,vin-r8a7790";
9f685bfc 860 reg = <0 0xe6ef2000 0 0x1000>;
3abb4d5f 861 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 862 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
863 power-domains = <&cpg_clocks>;
9f685bfc
BD		 864 status = "disabled";
865 };
866
867 vin3: video@e6ef3000 {
868 compatible = "renesas,vin-r8a7790";
9f685bfc 869 reg = <0 0xe6ef3000 0 0x1000>;
3abb4d5f 870 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 871 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
872 power-domains = <&cpg_clocks>;
9f685bfc
BD		 873 status = "disabled";
874 };
875
3ac6a83c
LP		 876 vsp1@fe920000 {
877 compatible = "renesas,vsp1";
878 reg = <0 0xfe920000 0 0x8000>;
3abb4d5f 879 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
3ac6a83c 880 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
484adb00 881 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 882
883 renesas,has-sru;
884 renesas,#rpf = <5>;
885 renesas,#uds = <1>;
886 renesas,#wpf = <4>;
887 };
888
889 vsp1@fe928000 {
890 compatible = "renesas,vsp1";
891 reg = <0 0xfe928000 0 0x8000>;
3abb4d5f 892 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
3ac6a83c 893 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
484adb00 894 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 895
896 renesas,has-lut;
897 renesas,has-sru;
898 renesas,#rpf = <5>;
899 renesas,#uds = <3>;
900 renesas,#wpf = <4>;
901 };
902
903 vsp1@fe930000 {
904 compatible = "renesas,vsp1";
905 reg = <0 0xfe930000 0 0x8000>;
3abb4d5f 906 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
3ac6a83c 907 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
484adb00 908 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 909
910 renesas,has-lif;
911 renesas,has-lut;
912 renesas,#rpf = <4>;
913 renesas,#uds = <1>;
914 renesas,#wpf = <4>;
915 };
916
917 vsp1@fe938000 {
918 compatible = "renesas,vsp1";
919 reg = <0 0xfe938000 0 0x8000>;
3abb4d5f 920 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
3ac6a83c 921 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
484adb00 922 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 923
924 renesas,has-lif;
925 renesas,has-lut;
926 renesas,#rpf = <4>;
927 renesas,#uds = <1>;
928 renesas,#wpf = <4>;
929 };
930
931 du: display@feb00000 {
932 compatible = "renesas,du-r8a7790";
933 reg = <0 0xfeb00000 0 0x70000>,
934 <0 0xfeb90000 0 0x1c>,
935 <0 0xfeb94000 0 0x1c>;
936 reg-names = "du", "lvds.0", "lvds.1";
3abb4d5f
SH		 937 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
3ac6a83c
LP		 940 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
941 <&mstp7_clks R8A7790_CLK_DU1>,
942 <&mstp7_clks R8A7790_CLK_DU2>,
943 <&mstp7_clks R8A7790_CLK_LVDS0>,
944 <&mstp7_clks R8A7790_CLK_LVDS1>;
945 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
946 status = "disabled";
947
948 ports {
949 #address-cells = <1>;
950 #size-cells = <0>;
951
952 port@0 {
953 reg = <0>;
954 du_out_rgb: endpoint {
955 };
956 };
957 port@1 {
958 reg = <1>;
959 du_out_lvds0: endpoint {
960 };
961 };
962 port@2 {
963 reg = <2>;
964 du_out_lvds1: endpoint {
965 };
966 };
967 };
968 };
969
6a7742b4
SS		 970 can0: can@e6e80000 {
971 compatible = "renesas,can-r8a7790";
972 reg = <0 0xe6e80000 0 0x1000>;
3abb4d5f 973 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
6a7742b4
SS		 974 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
975 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
976 clock-names = "clkp1", "clkp2", "can_clk";
484adb00 977 power-domains = <&cpg_clocks>;
6a7742b4
SS		 978 status = "disabled";
979 };
980
981 can1: can@e6e88000 {
982 compatible = "renesas,can-r8a7790";
983 reg = <0 0xe6e88000 0 0x1000>;
3abb4d5f 984 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
6a7742b4
SS		 985 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
986 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
987 clock-names = "clkp1", "clkp2", "can_clk";
484adb00 988 power-domains = <&cpg_clocks>;
6a7742b4
SS		 989 status = "disabled";
990 };
991
fb847575 992 jpu: jpeg-codec@fe980000 {
1c4b68fd 993 compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
fb847575 994 reg = <0 0xfe980000 0 0x10300>;
3abb4d5f 995 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
fb847575 996 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
484adb00 997 power-domains = <&cpg_clocks>;
fb847575
MU		 998 };
999
22a1f595
LP		 1000 clocks {
1001 #address-cells = <2>;
1002 #size-cells = <2>;
1003 ranges;
1004
1005 /* External root clock */
b19dd47b 1006 extal_clk: extal {
22a1f595
LP		 1007 compatible = "fixed-clock";
1008 #clock-cells = <0>;
1009 /* This value must be overriden by the board. */
1010 clock-frequency = <0>;
22a1f595
LP		 1011 };
1012
51d17918 1013 /* External PCIe clock - can be overridden by the board */
b19dd47b 1014 pcie_bus_clk: pcie_bus {
51d17918
PE		 1015 compatible = "fixed-clock";
1016 #clock-cells = <0>;
1017 clock-frequency = <100000000>;
51d17918
PE		 1018 status = "disabled";
1019 };
1020
c7c2ec3a
KM		 1021 /*
1022 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1023 * default. Boards that provide audio clocks should override them.
1024 */
1025 audio_clk_a: audio_clk_a {
1026 compatible = "fixed-clock";
1027 #clock-cells = <0>;
1028 clock-frequency = <0>;
c7c2ec3a
KM		 1029 };
1030 audio_clk_b: audio_clk_b {
1031 compatible = "fixed-clock";
1032 #clock-cells = <0>;
1033 clock-frequency = <0>;
c7c2ec3a
KM		 1034 };
1035 audio_clk_c: audio_clk_c {
1036 compatible = "fixed-clock";
1037 #clock-cells = <0>;
1038 clock-frequency = <0>;
c7c2ec3a
KM		 1039 };
1040
42af65e8
GU		 1041 /* External SCIF clock */
1042 scif_clk: scif {
1043 compatible = "fixed-clock";
1044 #clock-cells = <0>;
1045 /* This value must be overridden by the board. */
1046 clock-frequency = <0>;
1047 status = "disabled";
1048 };
1049
41650f40 1050 /* External USB clock - can be overridden by the board */
b19dd47b 1051 usb_extal_clk: usb_extal {
41650f40
SS		 1052 compatible = "fixed-clock";
1053 #clock-cells = <0>;
1054 clock-frequency = <48000000>;
41650f40
SS		 1055 };
1056
1057 /* External CAN clock */
1058 can_clk: can_clk {
1059 compatible = "fixed-clock";
1060 #clock-cells = <0>;
1061 /* This value must be overridden by the board. */
1062 clock-frequency = <0>;
41650f40
SS		 1063 status = "disabled";
1064 };
1065
22a1f595
LP		 1066 /* Special CPG clocks */
1067 cpg_clocks: cpg_clocks@e6150000 {
1068 compatible = "renesas,r8a7790-cpg-clocks",
1069 "renesas,rcar-gen2-cpg-clocks";
1070 reg = <0 0xe6150000 0 0x1000>;
41650f40 1071 clocks = <&extal_clk &usb_extal_clk>;
22a1f595
LP		 1072 #clock-cells = <1>;
1073 clock-output-names = "main", "pll0", "pll1", "pll3",
1074 "lb", "qspi", "sdh", "sd0", "sd1",
3453ca9e 1075 "z", "rcan", "adsp";
484adb00 1076 #power-domain-cells = <0>;
22a1f595
LP		 1077 };
1078
1079 /* Variable factor clocks */
b19dd47b 1080 sd2_clk: sd2@e6150078 {
22a1f595
LP		 1081 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1082 reg = <0 0xe6150078 0 4>;
1083 clocks = <&pll1_div2_clk>;
1084 #clock-cells = <0>;
22a1f595 1085 };
b19dd47b 1086 sd3_clk: sd3@e615026c {
22a1f595 1087 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
edd7b938 1088 reg = <0 0xe615026c 0 4>;
22a1f595
LP		 1089 clocks = <&pll1_div2_clk>;
1090 #clock-cells = <0>;
22a1f595 1091 };
b19dd47b 1092 mmc0_clk: mmc0@e6150240 {
22a1f595
LP		 1093 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1094 reg = <0 0xe6150240 0 4>;
1095 clocks = <&pll1_div2_clk>;
1096 #clock-cells = <0>;
22a1f595 1097 };
b19dd47b 1098 mmc1_clk: mmc1@e6150244 {
22a1f595
LP		 1099 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1100 reg = <0 0xe6150244 0 4>;
1101 clocks = <&pll1_div2_clk>;
1102 #clock-cells = <0>;
22a1f595 1103 };
b19dd47b 1104 ssp_clk: ssp@e6150248 {
22a1f595
LP		 1105 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1106 reg = <0 0xe6150248 0 4>;
1107 clocks = <&pll1_div2_clk>;
1108 #clock-cells = <0>;
22a1f595 1109 };
b19dd47b 1110 ssprs_clk: ssprs@e615024c {
22a1f595
LP		 1111 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1112 reg = <0 0xe615024c 0 4>;
1113 clocks = <&pll1_div2_clk>;
1114 #clock-cells = <0>;
22a1f595
LP		 1115 };
1116
1117 /* Fixed factor clocks */
b19dd47b 1118 pll1_div2_clk: pll1_div2 {
22a1f595
LP		 1119 compatible = "fixed-factor-clock";
1120 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1121 #clock-cells = <0>;
1122 clock-div = <2>;
1123 clock-mult = <1>;
22a1f595 1124 };
b19dd47b 1125 z2_clk: z2 {
22a1f595
LP		 1126 compatible = "fixed-factor-clock";
1127 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1128 #clock-cells = <0>;
1129 clock-div = <2>;
1130 clock-mult = <1>;
22a1f595 1131 };
b19dd47b 1132 zg_clk: zg {
22a1f595
LP		 1133 compatible = "fixed-factor-clock";
1134 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1135 #clock-cells = <0>;
1136 clock-div = <3>;
1137 clock-mult = <1>;
22a1f595 1138 };
b19dd47b 1139 zx_clk: zx {
22a1f595
LP		 1140 compatible = "fixed-factor-clock";
1141 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1142 #clock-cells = <0>;
1143 clock-div = <3>;
1144 clock-mult = <1>;
22a1f595 1145 };
b19dd47b 1146 zs_clk: zs {
22a1f595
LP		 1147 compatible = "fixed-factor-clock";
1148 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1149 #clock-cells = <0>;
1150 clock-div = <6>;
1151 clock-mult = <1>;
22a1f595 1152 };
b19dd47b 1153 hp_clk: hp {
22a1f595
LP		 1154 compatible = "fixed-factor-clock";
1155 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1156 #clock-cells = <0>;
1157 clock-div = <12>;
1158 clock-mult = <1>;
22a1f595 1159 };
b19dd47b 1160 i_clk: i {
22a1f595
LP		 1161 compatible = "fixed-factor-clock";
1162 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1163 #clock-cells = <0>;
1164 clock-div = <2>;
1165 clock-mult = <1>;
22a1f595 1166 };
b19dd47b 1167 b_clk: b {
22a1f595
LP		 1168 compatible = "fixed-factor-clock";
1169 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1170 #clock-cells = <0>;
1171 clock-div = <12>;
1172 clock-mult = <1>;
22a1f595 1173 };
b19dd47b 1174 p_clk: p {
22a1f595
LP		 1175 compatible = "fixed-factor-clock";
1176 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1177 #clock-cells = <0>;
1178 clock-div = <24>;
1179 clock-mult = <1>;
22a1f595 1180 };
b19dd47b 1181 cl_clk: cl {
22a1f595
LP		 1182 compatible = "fixed-factor-clock";
1183 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1184 #clock-cells = <0>;
1185 clock-div = <48>;
1186 clock-mult = <1>;
22a1f595 1187 };
b19dd47b 1188 m2_clk: m2 {
22a1f595
LP		 1189 compatible = "fixed-factor-clock";
1190 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1191 #clock-cells = <0>;
1192 clock-div = <8>;
1193 clock-mult = <1>;
22a1f595 1194 };
b19dd47b 1195 imp_clk: imp {
22a1f595
LP		 1196 compatible = "fixed-factor-clock";
1197 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1198 #clock-cells = <0>;
1199 clock-div = <4>;
1200 clock-mult = <1>;
22a1f595 1201 };
b19dd47b 1202 rclk_clk: rclk {
22a1f595
LP		 1203 compatible = "fixed-factor-clock";
1204 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1205 #clock-cells = <0>;
1206 clock-div = <(48 * 1024)>;
1207 clock-mult = <1>;
22a1f595 1208 };
b19dd47b 1209 oscclk_clk: oscclk {
22a1f595
LP		 1210 compatible = "fixed-factor-clock";
1211 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1212 #clock-cells = <0>;
1213 clock-div = <(12 * 1024)>;
1214 clock-mult = <1>;
22a1f595 1215 };
b19dd47b 1216 zb3_clk: zb3 {
22a1f595
LP		 1217 compatible = "fixed-factor-clock";
1218 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1219 #clock-cells = <0>;
1220 clock-div = <4>;
1221 clock-mult = <1>;
22a1f595 1222 };
b19dd47b 1223 zb3d2_clk: zb3d2 {
22a1f595
LP		 1224 compatible = "fixed-factor-clock";
1225 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1226 #clock-cells = <0>;
1227 clock-div = <8>;
1228 clock-mult = <1>;
22a1f595 1229 };
b19dd47b 1230 ddr_clk: ddr {
22a1f595
LP		 1231 compatible = "fixed-factor-clock";
1232 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1233 #clock-cells = <0>;
1234 clock-div = <8>;
1235 clock-mult = <1>;
22a1f595 1236 };
b19dd47b 1237 mp_clk: mp {
22a1f595
LP		 1238 compatible = "fixed-factor-clock";
1239 clocks = <&pll1_div2_clk>;
1240 #clock-cells = <0>;
1241 clock-div = <15>;
1242 clock-mult = <1>;
22a1f595 1243 };
b19dd47b 1244 cp_clk: cp {
22a1f595
LP		 1245 compatible = "fixed-factor-clock";
1246 clocks = <&extal_clk>;
1247 #clock-cells = <0>;
1248 clock-div = <2>;
1249 clock-mult = <1>;
22a1f595
LP		 1250 };
1251
1252 /* Gate clocks */
9d90951a
LP		 1253 mstp0_clks: mstp0_clks@e6150130 {
1254 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1255 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1256 clocks = <&mp_clk>;
1257 #clock-cells = <1>;
b54010af 1258 clock-indices = <R8A7790_CLK_MSIOF0>;
9d90951a
LP		 1259 clock-output-names = "msiof0";
1260 };
22a1f595
LP		 1261 mstp1_clks: mstp1_clks@e6150134 {
1262 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1263 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
4ba8f246
YH		 1264 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1265 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1266 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1267 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
22a1f595 1268 #clock-cells = <1>;
b54010af 1269 clock-indices = <
4ba8f246
YH		 1270 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1271 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1272 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1273 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1274 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1275 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1276 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
22a1f595
LP		 1277 >;
1278 clock-output-names =
4ba8f246
YH		 1279 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1280 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1281 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
2284ff5f 1282 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
22a1f595
LP		 1283 };
1284 mstp2_clks: mstp2_clks@e6150138 {
1285 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1286 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1287 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
c819acda
LP		 1288 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1289 <&zs_clk>;
22a1f595 1290 #clock-cells = <1>;
b54010af 1291 clock-indices = <
22a1f595 1292 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
9d90951a
LP		 1293 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1294 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
c819acda 1295 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
22a1f595
LP		 1296 >;
1297 clock-output-names =
9d90951a 1298 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
c819acda
LP		 1299 "scifb1", "msiof1", "msiof3", "scifb2",
1300 "sys-dmac1", "sys-dmac0";
22a1f595
LP		 1301 };
1302 mstp3_clks: mstp3_clks@e615013c {
1303 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1304 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
17465149
WS		 1305 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1306 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
b02ce79f
YS		 1307 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1308 <&hp_clk>, <&hp_clk>;
22a1f595 1309 #clock-cells = <1>;
b54010af 1310 clock-indices = <
17465149
WS		 1311 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1312 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
ecafea8c 1313 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
b02ce79f 1314 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
22a1f595
LP		 1315 >;
1316 clock-output-names =
17465149
WS		 1317 "iic2", "tpu0", "mmcif1", "sdhi3",
1318 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
b02ce79f
YS		 1319 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1320 "usbdmac0", "usbdmac1";
22a1f595 1321 };
61624caf
GU		 1322 mstp4_clks: mstp4_clks@e6150140 {
1323 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1324 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1325 clocks = <&cp_clk>;
1326 #clock-cells = <1>;
1327 clock-indices = <R8A7790_CLK_IRQC>;
1328 clock-output-names = "irqc";
1329 };
22a1f595
LP		 1330 mstp5_clks: mstp5_clks@e6150144 {
1331 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1332 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
3453ca9e
SS		 1333 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1334 <&extal_clk>, <&p_clk>;
22a1f595 1335 #clock-cells = <1>;
b54010af
BD		 1336 clock-indices = <
1337 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
3453ca9e
SS		 1338 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1339 R8A7790_CLK_PWM
b54010af 1340 >;
3453ca9e
SS		 1341 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1342 "thermal", "pwm";
22a1f595
LP		 1343 };
1344 mstp7_clks: mstp7_clks@e615014c {
1345 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1346 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
b621f6d4 1347 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
22a1f595
LP		 1348 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1349 <&zx_clk>;
1350 #clock-cells = <1>;
b54010af 1351 clock-indices = <
22a1f595
LP		 1352 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1353 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1354 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1355 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1356 >;
1357 clock-output-names =
1358 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1359 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1360 };
1361 mstp8_clks: mstp8_clks@e6150990 {
1362 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1363 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
f6b5dd40 1364 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
63d2d750
SS		 1365 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1366 <&zs_clk>;
22a1f595 1367 #clock-cells = <1>;
b54010af 1368 clock-indices = <
f6b5dd40 1369 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
63d2d750
SS		 1370 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1371 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
f6b5dd40 1372 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
3f2beaa9 1373 >;
bccccc3d 1374 clock-output-names =
63d2d750
SS		 1375 "mlb", "vin3", "vin2", "vin1", "vin0",
1376 "etheravb", "ether", "sata1", "sata0";
22a1f595
LP		 1377 };
1378 mstp9_clks: mstp9_clks@e6150994 {
1379 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1380 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
81f6883f
GU		 1381 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1382 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1383 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
3672b059 1384 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
22a1f595 1385 #clock-cells = <1>;
b54010af 1386 clock-indices = <
81f6883f
GU		 1387 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1388 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
17465149
WS		 1389 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1390 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
22a1f595 1391 >;
91b56ca1 1392 clock-output-names =
81f6883f 1393 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
17465149
WS		 1394 "rcan1", "rcan0", "qspi_mod", "iic3",
1395 "i2c3", "i2c2", "i2c1", "i2c0";
22a1f595 1396 };
bcde3722
KM		 1397 mstp10_clks: mstp10_clks@e6150998 {
1398 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1399 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1400 clocks = <&p_clk>,
1401 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1402 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1403 <&p_clk>,
1404 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1405 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1406 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1407 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1408 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
a7163784 1409 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
bcde3722
KM		 1410 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1411
1412 #clock-cells = <1>;
1413 clock-indices = <
1414 R8A7790_CLK_SSI_ALL
1415 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1416 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1417 R8A7790_CLK_SCU_ALL
1418 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
a7163784 1419 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
bcde3722
KM		 1420 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1421 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1422 >;
1423 clock-output-names =
1424 "ssi-all",
1425 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1426 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1427 "scu-all",
1428 "scu-dvc1", "scu-dvc0",
a7163784 1429 "scu-ctu1-mix1", "scu-ctu0-mix0",
bcde3722
KM		 1430 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1431 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1432 };
22a1f595 1433 };
7053e134 1434
fad6d45c 1435 qspi: spi@e6b10000 {
7053e134
GU		 1436 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1437 reg = <0 0xe6b10000 0 0x2c>;
3abb4d5f 1438 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
7053e134 1439 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
37cf3d61
GU		 1440 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1441 dma-names = "tx", "rx";
484adb00 1442 power-domains = <&cpg_clocks>;
7053e134
GU		 1443 num-cs = <1>;
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1446 status = "disabled";
1447 };
ae8a6146
GU		 1448
1449 msiof0: spi@e6e20000 {
1450 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1451 reg = <0 0xe6e20000 0 0x0064>;
3abb4d5f 1452 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
ae8a6146 1453 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
fbff6688
GU		 1454 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1455 dma-names = "tx", "rx";
484adb00 1456 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1457 #address-cells = <1>;
1458 #size-cells = <0>;
1459 status = "disabled";
1460 };
1461
1462 msiof1: spi@e6e10000 {
1463 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1464 reg = <0 0xe6e10000 0 0x0064>;
3abb4d5f 1465 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
ae8a6146 1466 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
fbff6688
GU		 1467 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1468 dma-names = "tx", "rx";
484adb00 1469 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1470 #address-cells = <1>;
1471 #size-cells = <0>;
1472 status = "disabled";
1473 };
1474
1475 msiof2: spi@e6e00000 {
1476 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1477 reg = <0 0xe6e00000 0 0x0064>;
3abb4d5f 1478 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
ae8a6146 1479 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
fbff6688
GU		 1480 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1481 dma-names = "tx", "rx";
484adb00 1482 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1483 #address-cells = <1>;
1484 #size-cells = <0>;
1485 status = "disabled";
1486 };
1487
1488 msiof3: spi@e6c90000 {
1489 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1490 reg = <0 0xe6c90000 0 0x0064>;
3abb4d5f 1491 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
ae8a6146 1492 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
fbff6688
GU		 1493 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1494 dma-names = "tx", "rx";
484adb00 1495 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1496 #address-cells = <1>;
1497 #size-cells = <0>;
1498 status = "disabled";
1499 };
7df2fd57 1500
157fcd8a
YS		 1501 xhci: usb@ee000000 {
1502 compatible = "renesas,xhci-r8a7790";
1503 reg = <0 0xee000000 0 0xc00>;
3abb4d5f 1504 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
157fcd8a 1505 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
484adb00 1506 power-domains = <&cpg_clocks>;
157fcd8a
YS		 1507 phys = <&usb2 1>;
1508 phy-names = "usb";
1509 status = "disabled";
1510 };
1511
ff4f3eb8 1512 pci0: pci@ee090000 {
2d82c144 1513 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
ff4f3eb8 1514 device_type = "pci";
ff4f3eb8
BD		 1515 reg = <0 0xee090000 0 0xc00>,
1516 <0 0xee080000 0 0x1100>;
3abb4d5f 1517 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 1518 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1519 power-domains = <&cpg_clocks>;
ff4f3eb8
BD		 1520 status = "disabled";
1521
1522 bus-range = <0 0>;
1523 #address-cells = <3>;
1524 #size-cells = <2>;
1525 #interrupt-cells = <1>;
1526 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1527 interrupt-map-mask = <0xff00 0 0 0x7>;
3abb4d5f
SH		 1528 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1529 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1530 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
538c40e5
SS		 1531
1532 usb@0,1 {
1533 reg = <0x800 0 0 0 0>;
1534 device_type = "pci";
1535 phys = <&usb0 0>;
1536 phy-names = "usb";
1537 };
1538
1539 usb@0,2 {
1540 reg = <0x1000 0 0 0 0>;
1541 device_type = "pci";
1542 phys = <&usb0 0>;
1543 phy-names = "usb";
1544 };
ff4f3eb8
BD		 1545 };
1546
1547 pci1: pci@ee0b0000 {
2d82c144 1548 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
ff4f3eb8 1549 device_type = "pci";
ff4f3eb8
BD		 1550 reg = <0 0xee0b0000 0 0xc00>,
1551 <0 0xee0a0000 0 0x1100>;
3abb4d5f 1552 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 1553 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1554 power-domains = <&cpg_clocks>;
ff4f3eb8
BD		 1555 status = "disabled";
1556
1557 bus-range = <1 1>;
1558 #address-cells = <3>;
1559 #size-cells = <2>;
1560 #interrupt-cells = <1>;
1561 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1562 interrupt-map-mask = <0xff00 0 0 0x7>;
3abb4d5f
SH		 1563 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1564 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1565 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
ff4f3eb8
BD		 1566 };
1567
1568 pci2: pci@ee0d0000 {
2d82c144 1569 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
ff4f3eb8
BD		 1570 device_type = "pci";
1571 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
484adb00 1572 power-domains = <&cpg_clocks>;
ff4f3eb8
BD		 1573 reg = <0 0xee0d0000 0 0xc00>,
1574 <0 0xee0c0000 0 0x1100>;
3abb4d5f 1575 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
ff4f3eb8
BD		 1576 status = "disabled";
1577
1578 bus-range = <2 2>;
1579 #address-cells = <3>;
1580 #size-cells = <2>;
1581 #interrupt-cells = <1>;
1582 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1583 interrupt-map-mask = <0xff00 0 0 0x7>;
3abb4d5f
SH		 1584 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1585 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1586 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
538c40e5
SS		 1587
1588 usb@0,1 {
1589 reg = <0x800 0 0 0 0>;
1590 device_type = "pci";
1591 phys = <&usb2 0>;
1592 phy-names = "usb";
1593 };
1594
1595 usb@0,2 {
1596 reg = <0x1000 0 0 0 0>;
1597 device_type = "pci";
1598 phys = <&usb2 0>;
1599 phy-names = "usb";
1600 };
ff4f3eb8
BD		 1601 };
1602
745329d2 1603 pciec: pcie@fe000000 {
e670be8d 1604 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
745329d2
PE		 1605 reg = <0 0xfe000000 0 0x80000>;
1606 #address-cells = <3>;
1607 #size-cells = <2>;
1608 bus-range = <0x00 0xff>;
1609 device_type = "pci";
1610 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1611 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1612 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1613 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1614 /* Map all possible DDR as inbound ranges */
1615 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1616 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
3abb4d5f
SH		 1617 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1618 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1619 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
745329d2
PE		 1620 #interrupt-cells = <1>;
1621 interrupt-map-mask = <0 0 0 0>;
3abb4d5f 1622 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
745329d2
PE		 1623 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1624 clock-names = "pcie", "pcie_bus";
484adb00 1625 power-domains = <&cpg_clocks>;
745329d2
PE		 1626 status = "disabled";
1627 };
1628
b694e380 1629 rcar_sound: sound@ec500000 {
ad63241c
KM		 1630 /*
1631 * #sound-dai-cells is required
1632 *
1633 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1634 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1635 */
31078ecd 1636 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
7df2fd57
KM		 1637 reg = <0 0xec500000 0 0x1000>, /* SCU */
1638 <0 0xec5a0000 0 0x100>, /* ADG */
1639 <0 0xec540000 0 0x1000>, /* SSIU */
4bc4a205 1640 <0 0xec541000 0 0x280>, /* SSI */
0c602677
KM		 1641 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1642 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
46a158f2 1643
7df2fd57
KM		 1644 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1645 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1646 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1647 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1648 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1649 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1650 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1651 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1652 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1653 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1654 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
a7163784 1655 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
fc67bf42 1656 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
334d69a2 1657 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
7df2fd57
KM		 1658 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1659 clock-names = "ssi-all",
1660 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1661 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1662 "src.9", "src.8", "src.7", "src.6", "src.5",
1663 "src.4", "src.3", "src.2", "src.1", "src.0",
a7163784 1664 "ctu.0", "ctu.1",
fc67bf42 1665 "mix.0", "mix.1",
334d69a2 1666 "dvc.0", "dvc.1",
7df2fd57 1667 "clk_a", "clk_b", "clk_c", "clk_i";
6507c4ef 1668 power-domains = <&cpg_clocks>;
7df2fd57
KM		 1669
1670 status = "disabled";
1671
334d69a2 1672 rcar_sound,dvc {
118a5093
KM		 1673 dvc0: dvc@0 {
1674 dmas = <&audma0 0xbc>;
1675 dma-names = "tx";
1676 };
1677 dvc1: dvc@1 {
1678 dmas = <&audma0 0xbe>;
1679 dma-names = "tx";
1680 };
334d69a2
KM		 1681 };
1682
fc67bf42
KM		 1683 rcar_sound,mix {
1684 mix0: mix@0 { };
1685 mix1: mix@1 { };
1686 };
1687
a7163784
KM		 1688 rcar_sound,ctu {
1689 ctu00: ctu@0 { };
1690 ctu01: ctu@1 { };
1691 ctu02: ctu@2 { };
1692 ctu03: ctu@3 { };
1693 ctu10: ctu@4 { };
1694 ctu11: ctu@5 { };
1695 ctu12: ctu@6 { };
1696 ctu13: ctu@7 { };
1697 };
1698
7df2fd57 1699 rcar_sound,src {
118a5093 1700 src0: src@0 {
3abb4d5f 1701 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1702 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1703 dma-names = "rx", "tx";
1704 };
1705 src1: src@1 {
3abb4d5f 1706 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1707 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1708 dma-names = "rx", "tx";
1709 };
1710 src2: src@2 {
3abb4d5f 1711 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1712 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1713 dma-names = "rx", "tx";
1714 };
1715 src3: src@3 {
3abb4d5f 1716 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1717 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1718 dma-names = "rx", "tx";
1719 };
1720 src4: src@4 {
3abb4d5f 1721 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1722 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1723 dma-names = "rx", "tx";
1724 };
1725 src5: src@5 {
3abb4d5f 1726 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1727 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1728 dma-names = "rx", "tx";
1729 };
1730 src6: src@6 {
3abb4d5f 1731 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1732 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1733 dma-names = "rx", "tx";
1734 };
1735 src7: src@7 {
3abb4d5f 1736 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1737 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1738 dma-names = "rx", "tx";
1739 };
1740 src8: src@8 {
3abb4d5f 1741 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1742 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1743 dma-names = "rx", "tx";
1744 };
1745 src9: src@9 {
3abb4d5f 1746 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1747 dmas = <&audma0 0x97>, <&audma1 0xba>;
1748 dma-names = "rx", "tx";
1749 };
7df2fd57
KM		 1750 };
1751
1752 rcar_sound,ssi {
118a5093 1753 ssi0: ssi@0 {
3abb4d5f 1754 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1755 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1756 dma-names = "rx", "tx", "rxu", "txu";
1757 };
1758 ssi1: ssi@1 {
3abb4d5f 1759 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1760 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1761 dma-names = "rx", "tx", "rxu", "txu";
1762 };
1763 ssi2: ssi@2 {
3abb4d5f 1764 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1765 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1766 dma-names = "rx", "tx", "rxu", "txu";
1767 };
1768 ssi3: ssi@3 {
3abb4d5f 1769 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1770 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1771 dma-names = "rx", "tx", "rxu", "txu";
1772 };
1773 ssi4: ssi@4 {
3abb4d5f 1774 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1775 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1776 dma-names = "rx", "tx", "rxu", "txu";
1777 };
1778 ssi5: ssi@5 {
3abb4d5f 1779 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1780 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1781 dma-names = "rx", "tx", "rxu", "txu";
1782 };
1783 ssi6: ssi@6 {
3abb4d5f 1784 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1785 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1786 dma-names = "rx", "tx", "rxu", "txu";
1787 };
1788 ssi7: ssi@7 {
3abb4d5f 1789 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1790 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1791 dma-names = "rx", "tx", "rxu", "txu";
1792 };
1793 ssi8: ssi@8 {
3abb4d5f 1794 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1795 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1796 dma-names = "rx", "tx", "rxu", "txu";
1797 };
1798 ssi9: ssi@9 {
3abb4d5f 1799 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1800 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1801 dma-names = "rx", "tx", "rxu", "txu";
1802 };
7df2fd57
KM		 1803 };
1804 };
70496727
LP		 1805
1806 ipmmu_sy0: mmu@e6280000 {
c8d6686e 1807 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1808 reg = <0 0xe6280000 0 0x1000>;
3abb4d5f
SH		 1809 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1810 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1811 #iommu-cells = <1>;
1812 status = "disabled";
1813 };
1814
1815 ipmmu_sy1: mmu@e6290000 {
c8d6686e 1816 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1817 reg = <0 0xe6290000 0 0x1000>;
3abb4d5f 1818 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1819 #iommu-cells = <1>;
1820 status = "disabled";
1821 };
1822
1823 ipmmu_ds: mmu@e6740000 {
c8d6686e 1824 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1825 reg = <0 0xe6740000 0 0x1000>;
3abb4d5f
SH		 1826 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1828 #iommu-cells = <1>;
1829 status = "disabled";
1830 };
1831
1832 ipmmu_mp: mmu@ec680000 {
c8d6686e 1833 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1834 reg = <0 0xec680000 0 0x1000>;
3abb4d5f 1835 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1836 #iommu-cells = <1>;
1837 status = "disabled";
1838 };
1839
1840 ipmmu_mx: mmu@fe951000 {
c8d6686e 1841 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1842 reg = <0 0xfe951000 0 0x1000>;
3abb4d5f
SH		 1843 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1844 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1845 #iommu-cells = <1>;
1846 status = "disabled";
1847 };
1848
1849 ipmmu_rt: mmu@ffc80000 {
c8d6686e 1850 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1851 reg = <0 0xffc80000 0 0x1000>;
3abb4d5f 1852 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1853 #iommu-cells = <1>;
1854 status = "disabled";
1855 };
0468b2d6 1856};
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