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Merge branch 'work.misc' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[mirror_ubuntu-jammy-kernel.git] / arch / arm / boot / dts / r8a7792.dtsi
CommitLineData
7c4163aa
SS		 1/*
2 * Device Tree Source for the r8a7792 SoC
3 *
4 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
762dbc44 11#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
7c4163aa
SS		 12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/power/r8a7792-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7792";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
78082700
SS		 21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
c9acea6e 28 spi0 = &qspi;
b0663cd4
SS		 29 spi1 = &msiof0;
30 spi2 = &msiof1;
a2d30b9c
SS		 31 vin0 = &vin0;
32 vin1 = &vin1;
33 vin2 = &vin2;
34 vin3 = &vin3;
35 vin4 = &vin4;
36 vin5 = &vin5;
d6f5fe84 37 };
78082700 38
7c4163aa
SS		 39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
8fd763c7 42 enable-method = "renesas,apmu";
7c4163aa
SS		 43
44 cpu0: cpu@0 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a15";
47 reg = <0>;
48 clock-frequency = <1000000000>;
762dbc44 49 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
7c4163aa
SS		 50 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
51 next-level-cache = <&L2_CA15>;
52 };
53
8fd763c7
SS		 54 cpu1: cpu@1 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a15";
57 reg = <1>;
58 clock-frequency = <1000000000>;
8684a24c 59 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
8fd763c7
SS		 60 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
61 next-level-cache = <&L2_CA15>;
62 };
63
a0504f08 64 L2_CA15: cache-controller-0 {
7c4163aa 65 compatible = "cache";
7c4163aa
SS		 66 cache-unified;
67 cache-level = <2>;
68 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
69 };
70 };
71
72 soc {
73 compatible = "simple-bus";
74 interrupt-parent = <&gic>;
75
76 #address-cells = <2>;
77 #size-cells = <2>;
78 ranges;
79
8fd763c7
SS		 80 apmu@e6152000 {
81 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
82 reg = <0 0xe6152000 0 0x188>;
83 cpus = <&cpu0 &cpu1>;
84 };
85
7c4163aa
SS		 86 gic: interrupt-controller@f1001000 {
87 compatible = "arm,gic-400";
88 #interrupt-cells = <3>;
89 interrupt-controller;
90 reg = <0 0xf1001000 0 0x1000>,
387720c9 91 <0 0xf1002000 0 0x2000>,
7c4163aa
SS		 92 <0 0xf1004000 0 0x2000>,
93 <0 0xf1006000 0 0x2000>;
94 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
95 IRQ_TYPE_LEVEL_HIGH)>;
762dbc44 96 clocks = <&cpg CPG_MOD 408>;
90dce542
GU		 97 clock-names = "clk";
98 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 99 resets = <&cpg 408>;
7c4163aa
SS		 100 };
101
56efdbe5
SS		 102 irqc: interrupt-controller@e61c0000 {
103 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
104 #interrupt-cells = <2>;
105 interrupt-controller;
106 reg = <0 0xe61c0000 0 0x200>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 111 clocks = <&cpg CPG_MOD 407>;
56efdbe5 112 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 113 resets = <&cpg 407>;
56efdbe5
SS		 114 };
115
7c4163aa
SS		 116 timer {
117 compatible = "arm,armv7-timer";
118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
119 IRQ_TYPE_LEVEL_LOW)>,
120 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
121 IRQ_TYPE_LEVEL_LOW)>,
122 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
123 IRQ_TYPE_LEVEL_LOW)>,
124 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
125 IRQ_TYPE_LEVEL_LOW)>;
126 };
127
d6f78ec4
GU		 128 rst: reset-controller@e6160000 {
129 compatible = "renesas,r8a7792-rst";
130 reg = <0 0xe6160000 0 0x0100>;
131 };
132
7cbae74e
GU		 133 prr: chipid@ff000044 {
134 compatible = "renesas,prr";
135 reg = <0 0xff000044 0 4>;
136 };
137
7c4163aa
SS		 138 sysc: system-controller@e6180000 {
139 compatible = "renesas,r8a7792-sysc";
140 reg = <0 0xe6180000 0 0x0200>;
141 #power-domain-cells = <1>;
142 };
143
02183a52
SS		 144 pfc: pin-controller@e6060000 {
145 compatible = "renesas,pfc-r8a7792";
146 reg = <0 0xe6060000 0 0x144>;
147 };
148
63359c2d
SS		 149 gpio0: gpio@e6050000 {
150 compatible = "renesas,gpio-r8a7792",
7f4a16c4 151 "renesas,rcar-gen2-gpio";
63359c2d
SS		 152 reg = <0 0xe6050000 0 0x50>;
153 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
154 #gpio-cells = <2>;
155 gpio-controller;
156 gpio-ranges = <&pfc 0 0 29>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
762dbc44 159 clocks = <&cpg CPG_MOD 912>;
63359c2d 160 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 161 resets = <&cpg 912>;
63359c2d
SS		 162 };
163
164 gpio1: gpio@e6051000 {
165 compatible = "renesas,gpio-r8a7792",
7f4a16c4 166 "renesas,rcar-gen2-gpio";
63359c2d
SS		 167 reg = <0 0xe6051000 0 0x50>;
168 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
169 #gpio-cells = <2>;
170 gpio-controller;
171 gpio-ranges = <&pfc 0 32 23>;
172 #interrupt-cells = <2>;
173 interrupt-controller;
762dbc44 174 clocks = <&cpg CPG_MOD 911>;
63359c2d 175 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 176 resets = <&cpg 911>;
63359c2d
SS		 177 };
178
179 gpio2: gpio@e6052000 {
180 compatible = "renesas,gpio-r8a7792",
7f4a16c4 181 "renesas,rcar-gen2-gpio";
63359c2d
SS		 182 reg = <0 0xe6052000 0 0x50>;
183 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
184 #gpio-cells = <2>;
185 gpio-controller;
186 gpio-ranges = <&pfc 0 64 32>;
187 #interrupt-cells = <2>;
188 interrupt-controller;
762dbc44 189 clocks = <&cpg CPG_MOD 910>;
63359c2d 190 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 191 resets = <&cpg 910>;
63359c2d
SS		 192 };
193
194 gpio3: gpio@e6053000 {
195 compatible = "renesas,gpio-r8a7792",
7f4a16c4 196 "renesas,rcar-gen2-gpio";
63359c2d
SS		 197 reg = <0 0xe6053000 0 0x50>;
198 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
199 #gpio-cells = <2>;
200 gpio-controller;
201 gpio-ranges = <&pfc 0 96 28>;
202 #interrupt-cells = <2>;
203 interrupt-controller;
762dbc44 204 clocks = <&cpg CPG_MOD 909>;
63359c2d 205 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 206 resets = <&cpg 909>;
63359c2d
SS		 207 };
208
209 gpio4: gpio@e6054000 {
210 compatible = "renesas,gpio-r8a7792",
7f4a16c4 211 "renesas,rcar-gen2-gpio";
63359c2d
SS		 212 reg = <0 0xe6054000 0 0x50>;
213 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
214 #gpio-cells = <2>;
215 gpio-controller;
216 gpio-ranges = <&pfc 0 128 17>;
217 #interrupt-cells = <2>;
218 interrupt-controller;
762dbc44 219 clocks = <&cpg CPG_MOD 908>;
63359c2d 220 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 221 resets = <&cpg 908>;
63359c2d
SS		 222 };
223
224 gpio5: gpio@e6055000 {
225 compatible = "renesas,gpio-r8a7792",
7f4a16c4 226 "renesas,rcar-gen2-gpio";
63359c2d
SS		 227 reg = <0 0xe6055000 0 0x50>;
228 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
229 #gpio-cells = <2>;
230 gpio-controller;
231 gpio-ranges = <&pfc 0 160 17>;
232 #interrupt-cells = <2>;
233 interrupt-controller;
762dbc44 234 clocks = <&cpg CPG_MOD 907>;
63359c2d 235 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 236 resets = <&cpg 907>;
63359c2d
SS		 237 };
238
239 gpio6: gpio@e6055100 {
240 compatible = "renesas,gpio-r8a7792",
7f4a16c4 241 "renesas,rcar-gen2-gpio";
63359c2d
SS		 242 reg = <0 0xe6055100 0 0x50>;
243 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
244 #gpio-cells = <2>;
245 gpio-controller;
246 gpio-ranges = <&pfc 0 192 17>;
247 #interrupt-cells = <2>;
248 interrupt-controller;
762dbc44 249 clocks = <&cpg CPG_MOD 905>;
63359c2d 250 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 251 resets = <&cpg 905>;
63359c2d
SS		 252 };
253
254 gpio7: gpio@e6055200 {
255 compatible = "renesas,gpio-r8a7792",
7f4a16c4 256 "renesas,rcar-gen2-gpio";
63359c2d
SS		 257 reg = <0 0xe6055200 0 0x50>;
258 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
259 #gpio-cells = <2>;
260 gpio-controller;
261 gpio-ranges = <&pfc 0 224 17>;
262 #interrupt-cells = <2>;
263 interrupt-controller;
762dbc44 264 clocks = <&cpg CPG_MOD 904>;
63359c2d 265 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 266 resets = <&cpg 904>;
63359c2d
SS		 267 };
268
269 gpio8: gpio@e6055300 {
270 compatible = "renesas,gpio-r8a7792",
7f4a16c4 271 "renesas,rcar-gen2-gpio";
63359c2d
SS		 272 reg = <0 0xe6055300 0 0x50>;
273 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
274 #gpio-cells = <2>;
275 gpio-controller;
276 gpio-ranges = <&pfc 0 256 17>;
277 #interrupt-cells = <2>;
278 interrupt-controller;
762dbc44 279 clocks = <&cpg CPG_MOD 921>;
63359c2d 280 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 281 resets = <&cpg 921>;
63359c2d
SS		 282 };
283
284 gpio9: gpio@e6055400 {
285 compatible = "renesas,gpio-r8a7792",
7f4a16c4 286 "renesas,rcar-gen2-gpio";
63359c2d
SS		 287 reg = <0 0xe6055400 0 0x50>;
288 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
289 #gpio-cells = <2>;
290 gpio-controller;
291 gpio-ranges = <&pfc 0 288 17>;
292 #interrupt-cells = <2>;
293 interrupt-controller;
762dbc44 294 clocks = <&cpg CPG_MOD 919>;
63359c2d 295 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 296 resets = <&cpg 919>;
63359c2d
SS		 297 };
298
299 gpio10: gpio@e6055500 {
300 compatible = "renesas,gpio-r8a7792",
7f4a16c4 301 "renesas,rcar-gen2-gpio";
63359c2d
SS		 302 reg = <0 0xe6055500 0 0x50>;
303 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
304 #gpio-cells = <2>;
305 gpio-controller;
306 gpio-ranges = <&pfc 0 320 32>;
307 #interrupt-cells = <2>;
308 interrupt-controller;
762dbc44 309 clocks = <&cpg CPG_MOD 914>;
63359c2d 310 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 311 resets = <&cpg 914>;
63359c2d
SS		 312 };
313
314 gpio11: gpio@e6055600 {
315 compatible = "renesas,gpio-r8a7792",
7f4a16c4 316 "renesas,rcar-gen2-gpio";
63359c2d
SS		 317 reg = <0 0xe6055600 0 0x50>;
318 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
319 #gpio-cells = <2>;
320 gpio-controller;
321 gpio-ranges = <&pfc 0 352 30>;
322 #interrupt-cells = <2>;
323 interrupt-controller;
762dbc44 324 clocks = <&cpg CPG_MOD 913>;
63359c2d 325 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 326 resets = <&cpg 913>;
63359c2d
SS		 327 };
328
fdf8ec0a
SS		 329 dmac0: dma-controller@e6700000 {
330 compatible = "renesas,dmac-r8a7792",
331 "renesas,rcar-dmac";
332 reg = <0 0xe6700000 0 0x20000>;
333 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
349 interrupt-names = "error",
350 "ch0", "ch1", "ch2", "ch3",
351 "ch4", "ch5", "ch6", "ch7",
352 "ch8", "ch9", "ch10", "ch11",
353 "ch12", "ch13", "ch14";
762dbc44 354 clocks = <&cpg CPG_MOD 219>;
fdf8ec0a
SS		 355 clock-names = "fck";
356 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 357 resets = <&cpg 219>;
fdf8ec0a
SS		 358 #dma-cells = <1>;
359 dma-channels = <15>;
360 };
361
362 dmac1: dma-controller@e6720000 {
363 compatible = "renesas,dmac-r8a7792",
364 "renesas,rcar-dmac";
365 reg = <0 0xe6720000 0 0x20000>;
366 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-names = "error",
383 "ch0", "ch1", "ch2", "ch3",
384 "ch4", "ch5", "ch6", "ch7",
385 "ch8", "ch9", "ch10", "ch11",
386 "ch12", "ch13", "ch14";
762dbc44 387 clocks = <&cpg CPG_MOD 218>;
fdf8ec0a
SS		 388 clock-names = "fck";
389 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 390 resets = <&cpg 218>;
fdf8ec0a
SS		 391 #dma-cells = <1>;
392 dma-channels = <15>;
393 };
394
e66796b9
SS		 395 scif0: serial@e6e60000 {
396 compatible = "renesas,scif-r8a7792",
397 "renesas,rcar-gen2-scif", "renesas,scif";
398 reg = <0 0xe6e60000 0 64>;
399 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 400 clocks = <&cpg CPG_MOD 721>,
401 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 402 clock-names = "fck", "brg_int", "scif_clk";
403 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
404 <&dmac1 0x29>, <&dmac1 0x2a>;
405 dma-names = "tx", "rx", "tx", "rx";
406 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 407 resets = <&cpg 721>;
e66796b9
SS		 408 status = "disabled";
409 };
410
411 scif1: serial@e6e68000 {
412 compatible = "renesas,scif-r8a7792",
413 "renesas,rcar-gen2-scif", "renesas,scif";
414 reg = <0 0xe6e68000 0 64>;
415 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 416 clocks = <&cpg CPG_MOD 720>,
417 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 418 clock-names = "fck", "brg_int", "scif_clk";
419 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
420 <&dmac1 0x2d>, <&dmac1 0x2e>;
421 dma-names = "tx", "rx", "tx", "rx";
422 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 423 resets = <&cpg 720>;
e66796b9
SS		 424 status = "disabled";
425 };
426
427 scif2: serial@e6e58000 {
428 compatible = "renesas,scif-r8a7792",
429 "renesas,rcar-gen2-scif", "renesas,scif";
430 reg = <0 0xe6e58000 0 64>;
431 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 432 clocks = <&cpg CPG_MOD 719>,
433 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 434 clock-names = "fck", "brg_int", "scif_clk";
435 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
436 <&dmac1 0x2b>, <&dmac1 0x2c>;
437 dma-names = "tx", "rx", "tx", "rx";
438 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 439 resets = <&cpg 719>;
e66796b9
SS		 440 status = "disabled";
441 };
442
443 scif3: serial@e6ea8000 {
444 compatible = "renesas,scif-r8a7792",
445 "renesas,rcar-gen2-scif", "renesas,scif";
446 reg = <0 0xe6ea8000 0 64>;
447 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 448 clocks = <&cpg CPG_MOD 718>,
449 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 450 clock-names = "fck", "brg_int", "scif_clk";
451 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
452 <&dmac1 0x2f>, <&dmac1 0x30>;
453 dma-names = "tx", "rx", "tx", "rx";
454 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 455 resets = <&cpg 718>;
e66796b9
SS		 456 status = "disabled";
457 };
458
459 hscif0: serial@e62c0000 {
460 compatible = "renesas,hscif-r8a7792",
461 "renesas,rcar-gen2-hscif", "renesas,hscif";
462 reg = <0 0xe62c0000 0 96>;
463 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 464 clocks = <&cpg CPG_MOD 717>,
465 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 466 clock-names = "fck", "brg_int", "scif_clk";
467 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
468 <&dmac1 0x39>, <&dmac1 0x3a>;
469 dma-names = "tx", "rx", "tx", "rx";
470 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 471 resets = <&cpg 717>;
e66796b9
SS		 472 status = "disabled";
473 };
474
475 hscif1: serial@e62c8000 {
476 compatible = "renesas,hscif-r8a7792",
477 "renesas,rcar-gen2-hscif", "renesas,hscif";
478 reg = <0 0xe62c8000 0 96>;
479 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 480 clocks = <&cpg CPG_MOD 716>,
481 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 482 clock-names = "fck", "brg_int", "scif_clk";
483 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
484 <&dmac1 0x4d>, <&dmac1 0x4e>;
485 dma-names = "tx", "rx", "tx", "rx";
486 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 487 resets = <&cpg 716>;
e66796b9
SS		 488 status = "disabled";
489 };
490
e63a6a48
GU		 491 icram0: sram@e63a0000 {
492 compatible = "mmio-sram";
493 reg = <0 0xe63a0000 0 0x12000>;
494 };
495
496 icram1: sram@e63c0000 {
497 compatible = "mmio-sram";
498 reg = <0 0xe63c0000 0 0x1000>;
a81597bf
GU		 499 #address-cells = <1>;
500 #size-cells = <1>;
501 ranges = <0 0 0xe63c0000 0x1000>;
502
503 smp-sram@0 {
504 compatible = "renesas,smp-sram";
505 reg = <0 0x10>;
506 };
e63a6a48
GU		 507 };
508
ce01b14e
SS		 509 sdhi0: sd@ee100000 {
510 compatible = "renesas,sdhi-r8a7792";
511 reg = <0 0xee100000 0 0x328>;
512 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
513 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
514 <&dmac1 0xcd>, <&dmac1 0xce>;
515 dma-names = "tx", "rx", "tx", "rx";
762dbc44 516 clocks = <&cpg CPG_MOD 314>;
ce01b14e 517 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 518 resets = <&cpg 314>;
ce01b14e
SS		 519 status = "disabled";
520 };
521
3e1839e9
SS		 522 jpu: jpeg-codec@fe980000 {
523 compatible = "renesas,jpu-r8a7792",
524 "renesas,rcar-gen2-jpu";
525 reg = <0 0xfe980000 0 0x10300>;
526 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 527 clocks = <&cpg CPG_MOD 106>;
3e1839e9 528 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 529 resets = <&cpg 106>;
3e1839e9
SS		 530 };
531
b12dcdcc
SS		 532 avb: ethernet@e6800000 {
533 compatible = "renesas,etheravb-r8a7792",
534 "renesas,etheravb-rcar-gen2";
535 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
536 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 537 clocks = <&cpg CPG_MOD 812>;
b12dcdcc 538 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 539 resets = <&cpg 812>;
b12dcdcc
SS		 540 #address-cells = <1>;
541 #size-cells = <0>;
542 status = "disabled";
543 };
544
78082700
SS		 545 /* I2C doesn't need pinmux */
546 i2c0: i2c@e6508000 {
cfcb93b3
SH		 547 compatible = "renesas,i2c-r8a7792",
548 "renesas,rcar-gen2-i2c";
78082700
SS		 549 reg = <0 0xe6508000 0 0x40>;
550 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 551 clocks = <&cpg CPG_MOD 931>;
78082700 552 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 553 resets = <&cpg 931>;
78082700
SS		 554 i2c-scl-internal-delay-ns = <6>;
555 #address-cells = <1>;
556 #size-cells = <0>;
557 status = "disabled";
558 };
559
560 i2c1: i2c@e6518000 {
cfcb93b3
SH		 561 compatible = "renesas,i2c-r8a7792",
562 "renesas,rcar-gen2-i2c";
78082700
SS		 563 reg = <0 0xe6518000 0 0x40>;
564 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 565 clocks = <&cpg CPG_MOD 930>;
78082700 566 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 567 resets = <&cpg 930>;
78082700
SS		 568 i2c-scl-internal-delay-ns = <6>;
569 #address-cells = <1>;
570 #size-cells = <0>;
571 status = "disabled";
572 };
573
574 i2c2: i2c@e6530000 {
cfcb93b3
SH		 575 compatible = "renesas,i2c-r8a7792",
576 "renesas,rcar-gen2-i2c";
78082700
SS		 577 reg = <0 0xe6530000 0 0x40>;
578 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 579 clocks = <&cpg CPG_MOD 929>;
78082700 580 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 581 resets = <&cpg 929>;
78082700
SS		 582 i2c-scl-internal-delay-ns = <6>;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 status = "disabled";
586 };
587
588 i2c3: i2c@e6540000 {
cfcb93b3
SH		 589 compatible = "renesas,i2c-r8a7792",
590 "renesas,rcar-gen2-i2c";
78082700
SS		 591 reg = <0 0xe6540000 0 0x40>;
592 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 593 clocks = <&cpg CPG_MOD 928>;
78082700 594 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 595 resets = <&cpg 928>;
78082700
SS		 596 i2c-scl-internal-delay-ns = <6>;
597 #address-cells = <1>;
598 #size-cells = <0>;
599 status = "disabled";
600 };
601
602 i2c4: i2c@e6520000 {
cfcb93b3
SH		 603 compatible = "renesas,i2c-r8a7792",
604 "renesas,rcar-gen2-i2c";
78082700
SS		 605 reg = <0 0xe6520000 0 0x40>;
606 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 607 clocks = <&cpg CPG_MOD 927>;
78082700 608 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 609 resets = <&cpg 927>;
78082700
SS		 610 i2c-scl-internal-delay-ns = <6>;
611 #address-cells = <1>;
612 #size-cells = <0>;
613 status = "disabled";
614 };
615
616 i2c5: i2c@e6528000 {
cfcb93b3
SH		 617 compatible = "renesas,i2c-r8a7792",
618 "renesas,rcar-gen2-i2c";
78082700
SS		 619 reg = <0 0xe6528000 0 0x40>;
620 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 621 clocks = <&cpg CPG_MOD 925>;
78082700 622 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 623 resets = <&cpg 925>;
78082700
SS		 624 i2c-scl-internal-delay-ns = <110>;
625 #address-cells = <1>;
c9acea6e
SS		 626 #size-cells = <0>;
627 status = "disabled";
628 };
629
630 qspi: spi@e6b10000 {
631 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
632 reg = <0 0xe6b10000 0 0x2c>;
633 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 634 clocks = <&cpg CPG_MOD 917>;
c9acea6e
SS		 635 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
636 <&dmac1 0x17>, <&dmac1 0x18>;
637 dma-names = "tx", "rx", "tx", "rx";
638 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 639 resets = <&cpg 917>;
c9acea6e
SS		 640 num-cs = <1>;
641 #address-cells = <1>;
78082700
SS		 642 #size-cells = <0>;
643 status = "disabled";
644 };
645
b0663cd4 646 msiof0: spi@e6e20000 {
50a15093
SH		 647 compatible = "renesas,msiof-r8a7792",
648 "renesas,rcar-gen2-msiof";
b0663cd4
SS		 649 reg = <0 0xe6e20000 0 0x0064>;
650 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 651 clocks = <&cpg CPG_MOD 000>;
b0663cd4
SS		 652 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
653 <&dmac1 0x51>, <&dmac1 0x52>;
654 dma-names = "tx", "rx", "tx", "rx";
655 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 656 resets = <&cpg 000>;
b0663cd4
SS		 657 #address-cells = <1>;
658 #size-cells = <0>;
659 status = "disabled";
660 };
661
662 msiof1: spi@e6e10000 {
50a15093
SH		 663 compatible = "renesas,msiof-r8a7792",
664 "renesas,rcar-gen2-msiof";
b0663cd4
SS		 665 reg = <0 0xe6e10000 0 0x0064>;
666 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 667 clocks = <&cpg CPG_MOD 208>;
b0663cd4
SS		 668 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
669 <&dmac1 0x55>, <&dmac1 0x56>;
670 dma-names = "tx", "rx", "tx", "rx";
671 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 672 resets = <&cpg 208>;
b0663cd4
SS		 673 #address-cells = <1>;
674 #size-cells = <0>;
675 status = "disabled";
676 };
677
8bec0842
SS		 678 du: display@feb00000 {
679 compatible = "renesas,du-r8a7792";
680 reg = <0 0xfeb00000 0 0x40000>;
681 reg-names = "du";
682 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 684 clocks = <&cpg CPG_MOD 724>,
685 <&cpg CPG_MOD 723>;
8bec0842
SS		 686 clock-names = "du.0", "du.1";
687 status = "disabled";
688
689 ports {
690 #address-cells = <1>;
691 #size-cells = <0>;
692
693 port@0 {
694 reg = <0>;
695 du_out_rgb0: endpoint {
696 };
697 };
698 port@1 {
699 reg = <1>;
700 du_out_rgb1: endpoint {
701 };
702 };
703 };
704 };
705
f947c02a
SS		 706 can0: can@e6e80000 {
707 compatible = "renesas,can-r8a7792",
708 "renesas,rcar-gen2-can";
709 reg = <0 0xe6e80000 0 0x1000>;
710 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 711 clocks = <&cpg CPG_MOD 916>,
712 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
f947c02a
SS		 713 clock-names = "clkp1", "clkp2", "can_clk";
714 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 715 resets = <&cpg 916>;
f947c02a
SS		 716 status = "disabled";
717 };
718
719 can1: can@e6e88000 {
720 compatible = "renesas,can-r8a7792",
721 "renesas,rcar-gen2-can";
722 reg = <0 0xe6e88000 0 0x1000>;
723 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 724 clocks = <&cpg CPG_MOD 915>,
725 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
f947c02a
SS		 726 clock-names = "clkp1", "clkp2", "can_clk";
727 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 728 resets = <&cpg 915>;
f947c02a
SS		 729 status = "disabled";
730 };
731
a2d30b9c
SS		 732 vin0: video@e6ef0000 {
733 compatible = "renesas,vin-r8a7792",
734 "renesas,rcar-gen2-vin";
735 reg = <0 0xe6ef0000 0 0x1000>;
736 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 737 clocks = <&cpg CPG_MOD 811>;
a2d30b9c 738 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 739 resets = <&cpg 811>;
a2d30b9c
SS		 740 status = "disabled";
741 };
742
743 vin1: video@e6ef1000 {
744 compatible = "renesas,vin-r8a7792",
745 "renesas,rcar-gen2-vin";
746 reg = <0 0xe6ef1000 0 0x1000>;
747 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 748 clocks = <&cpg CPG_MOD 810>;
a2d30b9c 749 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 750 resets = <&cpg 810>;
a2d30b9c
SS		 751 status = "disabled";
752 };
753
754 vin2: video@e6ef2000 {
755 compatible = "renesas,vin-r8a7792",
756 "renesas,rcar-gen2-vin";
757 reg = <0 0xe6ef2000 0 0x1000>;
758 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 759 clocks = <&cpg CPG_MOD 809>;
a2d30b9c 760 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 761 resets = <&cpg 809>;
a2d30b9c
SS		 762 status = "disabled";
763 };
764
765 vin3: video@e6ef3000 {
766 compatible = "renesas,vin-r8a7792",
767 "renesas,rcar-gen2-vin";
768 reg = <0 0xe6ef3000 0 0x1000>;
769 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 770 clocks = <&cpg CPG_MOD 808>;
a2d30b9c 771 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 772 resets = <&cpg 808>;
a2d30b9c
SS		 773 status = "disabled";
774 };
775
776 vin4: video@e6ef4000 {
777 compatible = "renesas,vin-r8a7792",
778 "renesas,rcar-gen2-vin";
779 reg = <0 0xe6ef4000 0 0x1000>;
780 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 781 clocks = <&cpg CPG_MOD 805>;
a2d30b9c 782 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 783 resets = <&cpg 805>;
a2d30b9c
SS		 784 status = "disabled";
785 };
786
787 vin5: video@e6ef5000 {
788 compatible = "renesas,vin-r8a7792",
789 "renesas,rcar-gen2-vin";
790 reg = <0 0xe6ef5000 0 0x1000>;
791 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 792 clocks = <&cpg CPG_MOD 804>;
a2d30b9c 793 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 794 resets = <&cpg 804>;
a2d30b9c
SS		 795 status = "disabled";
796 };
797
2ea2e06c 798 vsp@fe928000 {
9e1019c6
SS		 799 compatible = "renesas,vsp1";
800 reg = <0 0xfe928000 0 0x8000>;
801 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 802 clocks = <&cpg CPG_MOD 131>;
9e1019c6 803 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 804 resets = <&cpg 131>;
9e1019c6
SS		 805 };
806
2ea2e06c 807 vsp@fe930000 {
9e1019c6
SS		 808 compatible = "renesas,vsp1";
809 reg = <0 0xfe930000 0 0x8000>;
810 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 811 clocks = <&cpg CPG_MOD 128>;
9e1019c6 812 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 813 resets = <&cpg 128>;
9e1019c6
SS		 814 };
815
2ea2e06c 816 vsp@fe938000 {
9e1019c6
SS		 817 compatible = "renesas,vsp1";
818 reg = <0 0xfe938000 0 0x8000>;
819 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 820 clocks = <&cpg CPG_MOD 127>;
9e1019c6 821 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 822 resets = <&cpg 127>;
9e1019c6
SS		 823 };
824
762dbc44
GU		 825 cpg: clock-controller@e6150000 {
826 compatible = "renesas,r8a7792-cpg-mssr";
7c4163aa
SS		 827 reg = <0 0xe6150000 0 0x1000>;
828 clocks = <&extal_clk>;
762dbc44
GU		 829 clock-names = "extal";
830 #clock-cells = <2>;
7c4163aa 831 #power-domain-cells = <0>;
098f5305 832 #reset-cells = <1>;
7c4163aa 833 };
7c4163aa
SS		 834 };
835
836 /* External root clock */
837 extal_clk: extal {
838 compatible = "fixed-clock";
839 #clock-cells = <0>;
840 /* This value must be overridden by the board. */
841 clock-frequency = <0>;
842 };
843
844 /* External SCIF clock */
845 scif_clk: scif {
846 compatible = "fixed-clock";
847 #clock-cells = <0>;
848 /* This value must be overridden by the board. */
849 clock-frequency = <0>;
850 };
47db051c
SS		 851
852 /* External CAN clock */
853 can_clk: can {
854 compatible = "fixed-clock";
855 #clock-cells = <0>;
856 /* This value must be overridden by the board. */
857 clock-frequency = <0>;
858 };
7c4163aa 859};
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