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ARM: dts: r8a7792: add VIN clocks
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / r8a7792.dtsi
CommitLineData
7c4163aa
SS		 1/*
2 * Device Tree Source for the r8a7792 SoC
3 *
4 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7792-clock.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/power/r8a7792-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7792";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
78082700
SS		 21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
28};
29
7c4163aa
SS		 30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
8fd763c7 33 enable-method = "renesas,apmu";
7c4163aa
SS		 34
35 cpu0: cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a15";
38 reg = <0>;
39 clock-frequency = <1000000000>;
40 clocks = <&cpg_clocks R8A7792_CLK_Z>;
41 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
42 next-level-cache = <&L2_CA15>;
43 };
44
8fd763c7
SS		 45 cpu1: cpu@1 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a15";
48 reg = <1>;
49 clock-frequency = <1000000000>;
50 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
51 next-level-cache = <&L2_CA15>;
52 };
53
7c4163aa
SS		 54 L2_CA15: cache-controller@0 {
55 compatible = "cache";
56 reg = <0>;
57 cache-unified;
58 cache-level = <2>;
59 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
60 };
61 };
62
63 soc {
64 compatible = "simple-bus";
65 interrupt-parent = <&gic>;
66
67 #address-cells = <2>;
68 #size-cells = <2>;
69 ranges;
70
8fd763c7
SS		 71 apmu@e6152000 {
72 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
73 reg = <0 0xe6152000 0 0x188>;
74 cpus = <&cpu0 &cpu1>;
75 };
76
7c4163aa
SS		 77 gic: interrupt-controller@f1001000 {
78 compatible = "arm,gic-400";
79 #interrupt-cells = <3>;
80 interrupt-controller;
81 reg = <0 0xf1001000 0 0x1000>,
82 <0 0xf1002000 0 0x1000>,
83 <0 0xf1004000 0 0x2000>,
84 <0 0xf1006000 0 0x2000>;
85 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
86 IRQ_TYPE_LEVEL_HIGH)>;
87 };
88
56efdbe5
SS		 89 irqc: interrupt-controller@e61c0000 {
90 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
91 #interrupt-cells = <2>;
92 interrupt-controller;
93 reg = <0 0xe61c0000 0 0x200>;
94 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
99 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
100 };
101
7c4163aa
SS		 102 timer {
103 compatible = "arm,armv7-timer";
104 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
105 IRQ_TYPE_LEVEL_LOW)>,
106 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
107 IRQ_TYPE_LEVEL_LOW)>,
108 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
109 IRQ_TYPE_LEVEL_LOW)>,
110 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
111 IRQ_TYPE_LEVEL_LOW)>;
112 };
113
114 sysc: system-controller@e6180000 {
115 compatible = "renesas,r8a7792-sysc";
116 reg = <0 0xe6180000 0 0x0200>;
117 #power-domain-cells = <1>;
118 };
119
02183a52
SS		 120 pfc: pin-controller@e6060000 {
121 compatible = "renesas,pfc-r8a7792";
122 reg = <0 0xe6060000 0 0x144>;
123 };
124
63359c2d
SS		 125 gpio0: gpio@e6050000 {
126 compatible = "renesas,gpio-r8a7792",
127 "renesas,gpio-rcar";
128 reg = <0 0xe6050000 0 0x50>;
129 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
130 #gpio-cells = <2>;
131 gpio-controller;
132 gpio-ranges = <&pfc 0 0 29>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
135 clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
136 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
137 };
138
139 gpio1: gpio@e6051000 {
140 compatible = "renesas,gpio-r8a7792",
141 "renesas,gpio-rcar";
142 reg = <0 0xe6051000 0 0x50>;
143 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
144 #gpio-cells = <2>;
145 gpio-controller;
146 gpio-ranges = <&pfc 0 32 23>;
147 #interrupt-cells = <2>;
148 interrupt-controller;
149 clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
150 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
151 };
152
153 gpio2: gpio@e6052000 {
154 compatible = "renesas,gpio-r8a7792",
155 "renesas,gpio-rcar";
156 reg = <0 0xe6052000 0 0x50>;
157 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
158 #gpio-cells = <2>;
159 gpio-controller;
160 gpio-ranges = <&pfc 0 64 32>;
161 #interrupt-cells = <2>;
162 interrupt-controller;
163 clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
164 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
165 };
166
167 gpio3: gpio@e6053000 {
168 compatible = "renesas,gpio-r8a7792",
169 "renesas,gpio-rcar";
170 reg = <0 0xe6053000 0 0x50>;
171 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>;
173 gpio-controller;
174 gpio-ranges = <&pfc 0 96 28>;
175 #interrupt-cells = <2>;
176 interrupt-controller;
177 clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
178 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
179 };
180
181 gpio4: gpio@e6054000 {
182 compatible = "renesas,gpio-r8a7792",
183 "renesas,gpio-rcar";
184 reg = <0 0xe6054000 0 0x50>;
185 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
186 #gpio-cells = <2>;
187 gpio-controller;
188 gpio-ranges = <&pfc 0 128 17>;
189 #interrupt-cells = <2>;
190 interrupt-controller;
191 clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
192 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
193 };
194
195 gpio5: gpio@e6055000 {
196 compatible = "renesas,gpio-r8a7792",
197 "renesas,gpio-rcar";
198 reg = <0 0xe6055000 0 0x50>;
199 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
200 #gpio-cells = <2>;
201 gpio-controller;
202 gpio-ranges = <&pfc 0 160 17>;
203 #interrupt-cells = <2>;
204 interrupt-controller;
205 clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
206 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
207 };
208
209 gpio6: gpio@e6055100 {
210 compatible = "renesas,gpio-r8a7792",
211 "renesas,gpio-rcar";
212 reg = <0 0xe6055100 0 0x50>;
213 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
214 #gpio-cells = <2>;
215 gpio-controller;
216 gpio-ranges = <&pfc 0 192 17>;
217 #interrupt-cells = <2>;
218 interrupt-controller;
219 clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
220 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
221 };
222
223 gpio7: gpio@e6055200 {
224 compatible = "renesas,gpio-r8a7792",
225 "renesas,gpio-rcar";
226 reg = <0 0xe6055200 0 0x50>;
227 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
228 #gpio-cells = <2>;
229 gpio-controller;
230 gpio-ranges = <&pfc 0 224 17>;
231 #interrupt-cells = <2>;
232 interrupt-controller;
233 clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
234 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
235 };
236
237 gpio8: gpio@e6055300 {
238 compatible = "renesas,gpio-r8a7792",
239 "renesas,gpio-rcar";
240 reg = <0 0xe6055300 0 0x50>;
241 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
242 #gpio-cells = <2>;
243 gpio-controller;
244 gpio-ranges = <&pfc 0 256 17>;
245 #interrupt-cells = <2>;
246 interrupt-controller;
247 clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
248 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
249 };
250
251 gpio9: gpio@e6055400 {
252 compatible = "renesas,gpio-r8a7792",
253 "renesas,gpio-rcar";
254 reg = <0 0xe6055400 0 0x50>;
255 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
256 #gpio-cells = <2>;
257 gpio-controller;
258 gpio-ranges = <&pfc 0 288 17>;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
262 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
263 };
264
265 gpio10: gpio@e6055500 {
266 compatible = "renesas,gpio-r8a7792",
267 "renesas,gpio-rcar";
268 reg = <0 0xe6055500 0 0x50>;
269 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
270 #gpio-cells = <2>;
271 gpio-controller;
272 gpio-ranges = <&pfc 0 320 32>;
273 #interrupt-cells = <2>;
274 interrupt-controller;
275 clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
276 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
277 };
278
279 gpio11: gpio@e6055600 {
280 compatible = "renesas,gpio-r8a7792",
281 "renesas,gpio-rcar";
282 reg = <0 0xe6055600 0 0x50>;
283 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
284 #gpio-cells = <2>;
285 gpio-controller;
286 gpio-ranges = <&pfc 0 352 30>;
287 #interrupt-cells = <2>;
288 interrupt-controller;
289 clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
290 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
291 };
292
fdf8ec0a
SS		 293 dmac0: dma-controller@e6700000 {
294 compatible = "renesas,dmac-r8a7792",
295 "renesas,rcar-dmac";
296 reg = <0 0xe6700000 0 0x20000>;
297 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
298 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
299 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
305 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
306 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
307 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
308 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
309 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
310 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
311 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
312 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
313 interrupt-names = "error",
314 "ch0", "ch1", "ch2", "ch3",
315 "ch4", "ch5", "ch6", "ch7",
316 "ch8", "ch9", "ch10", "ch11",
317 "ch12", "ch13", "ch14";
318 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
319 clock-names = "fck";
320 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
321 #dma-cells = <1>;
322 dma-channels = <15>;
323 };
324
325 dmac1: dma-controller@e6720000 {
326 compatible = "renesas,dmac-r8a7792",
327 "renesas,rcar-dmac";
328 reg = <0 0xe6720000 0 0x20000>;
329 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
345 interrupt-names = "error",
346 "ch0", "ch1", "ch2", "ch3",
347 "ch4", "ch5", "ch6", "ch7",
348 "ch8", "ch9", "ch10", "ch11",
349 "ch12", "ch13", "ch14";
350 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
351 clock-names = "fck";
352 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
353 #dma-cells = <1>;
354 dma-channels = <15>;
355 };
356
e66796b9
SS		 357 scif0: serial@e6e60000 {
358 compatible = "renesas,scif-r8a7792",
359 "renesas,rcar-gen2-scif", "renesas,scif";
360 reg = <0 0xe6e60000 0 64>;
361 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
363 <&scif_clk>;
364 clock-names = "fck", "brg_int", "scif_clk";
365 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
366 <&dmac1 0x29>, <&dmac1 0x2a>;
367 dma-names = "tx", "rx", "tx", "rx";
368 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
369 status = "disabled";
370 };
371
372 scif1: serial@e6e68000 {
373 compatible = "renesas,scif-r8a7792",
374 "renesas,rcar-gen2-scif", "renesas,scif";
375 reg = <0 0xe6e68000 0 64>;
376 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
378 <&scif_clk>;
379 clock-names = "fck", "brg_int", "scif_clk";
380 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
381 <&dmac1 0x2d>, <&dmac1 0x2e>;
382 dma-names = "tx", "rx", "tx", "rx";
383 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
384 status = "disabled";
385 };
386
387 scif2: serial@e6e58000 {
388 compatible = "renesas,scif-r8a7792",
389 "renesas,rcar-gen2-scif", "renesas,scif";
390 reg = <0 0xe6e58000 0 64>;
391 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
393 <&scif_clk>;
394 clock-names = "fck", "brg_int", "scif_clk";
395 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
396 <&dmac1 0x2b>, <&dmac1 0x2c>;
397 dma-names = "tx", "rx", "tx", "rx";
398 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
399 status = "disabled";
400 };
401
402 scif3: serial@e6ea8000 {
403 compatible = "renesas,scif-r8a7792",
404 "renesas,rcar-gen2-scif", "renesas,scif";
405 reg = <0 0xe6ea8000 0 64>;
406 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
408 <&scif_clk>;
409 clock-names = "fck", "brg_int", "scif_clk";
410 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
411 <&dmac1 0x2f>, <&dmac1 0x30>;
412 dma-names = "tx", "rx", "tx", "rx";
413 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
414 status = "disabled";
415 };
416
417 hscif0: serial@e62c0000 {
418 compatible = "renesas,hscif-r8a7792",
419 "renesas,rcar-gen2-hscif", "renesas,hscif";
420 reg = <0 0xe62c0000 0 96>;
421 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
423 <&scif_clk>;
424 clock-names = "fck", "brg_int", "scif_clk";
425 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
426 <&dmac1 0x39>, <&dmac1 0x3a>;
427 dma-names = "tx", "rx", "tx", "rx";
428 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
429 status = "disabled";
430 };
431
432 hscif1: serial@e62c8000 {
433 compatible = "renesas,hscif-r8a7792",
434 "renesas,rcar-gen2-hscif", "renesas,hscif";
435 reg = <0 0xe62c8000 0 96>;
436 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
438 <&scif_clk>;
439 clock-names = "fck", "brg_int", "scif_clk";
440 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
441 <&dmac1 0x4d>, <&dmac1 0x4e>;
442 dma-names = "tx", "rx", "tx", "rx";
443 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
444 status = "disabled";
445 };
446
ce01b14e
SS		 447 sdhi0: sd@ee100000 {
448 compatible = "renesas,sdhi-r8a7792";
449 reg = <0 0xee100000 0 0x328>;
450 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
451 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
452 <&dmac1 0xcd>, <&dmac1 0xce>;
453 dma-names = "tx", "rx", "tx", "rx";
454 clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
455 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
456 status = "disabled";
457 };
458
3e1839e9
SS		 459 jpu: jpeg-codec@fe980000 {
460 compatible = "renesas,jpu-r8a7792",
461 "renesas,rcar-gen2-jpu";
462 reg = <0 0xfe980000 0 0x10300>;
463 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&mstp1_clks R8A7792_CLK_JPU>;
465 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
466 };
467
b12dcdcc
SS		 468 avb: ethernet@e6800000 {
469 compatible = "renesas,etheravb-r8a7792",
470 "renesas,etheravb-rcar-gen2";
471 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
472 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
474 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
475 #address-cells = <1>;
476 #size-cells = <0>;
477 status = "disabled";
478 };
479
78082700
SS		 480 /* I2C doesn't need pinmux */
481 i2c0: i2c@e6508000 {
482 compatible = "renesas,i2c-r8a7792";
483 reg = <0 0xe6508000 0 0x40>;
484 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
486 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
487 i2c-scl-internal-delay-ns = <6>;
488 #address-cells = <1>;
489 #size-cells = <0>;
490 status = "disabled";
491 };
492
493 i2c1: i2c@e6518000 {
494 compatible = "renesas,i2c-r8a7792";
495 reg = <0 0xe6518000 0 0x40>;
496 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
498 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
499 i2c-scl-internal-delay-ns = <6>;
500 #address-cells = <1>;
501 #size-cells = <0>;
502 status = "disabled";
503 };
504
505 i2c2: i2c@e6530000 {
506 compatible = "renesas,i2c-r8a7792";
507 reg = <0 0xe6530000 0 0x40>;
508 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
510 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
511 i2c-scl-internal-delay-ns = <6>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 status = "disabled";
515 };
516
517 i2c3: i2c@e6540000 {
518 compatible = "renesas,i2c-r8a7792";
519 reg = <0 0xe6540000 0 0x40>;
520 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
522 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
523 i2c-scl-internal-delay-ns = <6>;
524 #address-cells = <1>;
525 #size-cells = <0>;
526 status = "disabled";
527 };
528
529 i2c4: i2c@e6520000 {
530 compatible = "renesas,i2c-r8a7792";
531 reg = <0 0xe6520000 0 0x40>;
532 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
534 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
535 i2c-scl-internal-delay-ns = <6>;
536 #address-cells = <1>;
537 #size-cells = <0>;
538 status = "disabled";
539 };
540
541 i2c5: i2c@e6528000 {
542 compatible = "renesas,i2c-r8a7792";
543 reg = <0 0xe6528000 0 0x40>;
544 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
546 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
547 i2c-scl-internal-delay-ns = <110>;
548 #address-cells = <1>;
549 #size-cells = <0>;
550 status = "disabled";
551 };
552
f947c02a
SS		 553 can0: can@e6e80000 {
554 compatible = "renesas,can-r8a7792",
555 "renesas,rcar-gen2-can";
556 reg = <0 0xe6e80000 0 0x1000>;
557 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
559 <&rcan_clk>, <&can_clk>;
560 clock-names = "clkp1", "clkp2", "can_clk";
561 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
562 status = "disabled";
563 };
564
565 can1: can@e6e88000 {
566 compatible = "renesas,can-r8a7792",
567 "renesas,rcar-gen2-can";
568 reg = <0 0xe6e88000 0 0x1000>;
569 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
571 <&rcan_clk>, <&can_clk>;
572 clock-names = "clkp1", "clkp2", "can_clk";
573 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
574 status = "disabled";
575 };
576
7c4163aa
SS		 577 /* Special CPG clocks */
578 cpg_clocks: cpg_clocks@e6150000 {
579 compatible = "renesas,r8a7792-cpg-clocks",
580 "renesas,rcar-gen2-cpg-clocks";
581 reg = <0 0xe6150000 0 0x1000>;
582 clocks = <&extal_clk>;
583 #clock-cells = <1>;
584 clock-output-names = "main", "pll0", "pll1", "pll3",
e0c3f92a 585 "lb", "qspi", "z";
7c4163aa
SS		 586 #power-domain-cells = <0>;
587 };
588
589 /* Fixed factor clocks */
4b9b7b3a
SS		 590 pll1_div2_clk: pll1_div2 {
591 compatible = "fixed-factor-clock";
592 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
593 #clock-cells = <0>;
594 clock-div = <2>;
595 clock-mult = <1>;
596 };
7c4163aa
SS		 597 zs_clk: zs {
598 compatible = "fixed-factor-clock";
599 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
600 #clock-cells = <0>;
601 clock-div = <6>;
602 clock-mult = <1>;
603 };
08cafff6
SS		 604 hp_clk: hp {
605 compatible = "fixed-factor-clock";
606 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
607 #clock-cells = <0>;
608 clock-div = <12>;
609 clock-mult = <1>;
610 };
7c4163aa
SS		 611 p_clk: p {
612 compatible = "fixed-factor-clock";
613 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
614 #clock-cells = <0>;
615 clock-div = <24>;
616 clock-mult = <1>;
617 };
618 cp_clk: cp {
619 compatible = "fixed-factor-clock";
620 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
621 #clock-cells = <0>;
622 clock-div = <48>;
623 clock-mult = <1>;
624 };
eebc8e2c
SS		 625 m2_clk: m2 {
626 compatible = "fixed-factor-clock";
627 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
628 #clock-cells = <0>;
629 clock-div = <8>;
630 clock-mult = <1>;
631 };
fe683922
SS		 632 sd_clk: sd {
633 compatible = "fixed-factor-clock";
634 clocks = <&pll1_div2_clk>;
635 #clock-cells = <0>;
636 clock-div = <8>;
637 clock-mult = <1>;
638 };
47db051c
SS		 639 rcan_clk: rcan {
640 compatible = "fixed-factor-clock";
641 clocks = <&pll1_div2_clk>;
642 #clock-cells = <0>;
643 clock-div = <49>;
644 clock-mult = <1>;
645 };
62855bcf
SS		 646 zg_clk: zg {
647 compatible = "fixed-factor-clock";
648 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
649 #clock-cells = <0>;
650 clock-div = <5>;
651 clock-mult = <1>;
652 };
7c4163aa
SS		 653
654 /* Gate clocks */
eebc8e2c
SS		 655 mstp1_clks: mstp1_clks@e6150134 {
656 compatible = "renesas,r8a7792-mstp-clocks",
657 "renesas,cpg-mstp-clocks";
658 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
659 clocks = <&m2_clk>;
660 #clock-cells = <1>;
661 clock-indices = <R8A7792_CLK_JPU>;
662 clock-output-names = "jpu";
663 };
7c4163aa
SS		 664 mstp2_clks: mstp2_clks@e6150138 {
665 compatible = "renesas,r8a7792-mstp-clocks",
666 "renesas,cpg-mstp-clocks";
667 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
668 clocks = <&zs_clk>, <&zs_clk>;
669 #clock-cells = <1>;
670 clock-indices = <
671 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
672 >;
673 clock-output-names = "sys-dmac1", "sys-dmac0";
674 };
fe683922
SS		 675 mstp3_clks: mstp3_clks@e615013c {
676 compatible = "renesas,r8a7792-mstp-clocks",
677 "renesas,cpg-mstp-clocks";
678 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
679 clocks = <&sd_clk>;
680 #clock-cells = <1>;
681 renesas,clock-indices = <R8A7792_CLK_SDHI0>;
682 clock-output-names = "sdhi0";
683 };
7c4163aa
SS		 684 mstp4_clks: mstp4_clks@e6150140 {
685 compatible = "renesas,r8a7792-mstp-clocks",
686 "renesas,cpg-mstp-clocks";
687 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
688 clocks = <&cp_clk>;
689 #clock-cells = <1>;
690 clock-indices = <R8A7792_CLK_IRQC>;
691 clock-output-names = "irqc";
692 };
693 mstp7_clks: mstp7_clks@e615014c {
694 compatible = "renesas,r8a7792-mstp-clocks",
695 "renesas,cpg-mstp-clocks";
696 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
697 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
698 <&p_clk>, <&p_clk>;
699 #clock-cells = <1>;
700 clock-indices = <
701 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
702 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
703 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
704 >;
705 clock-output-names = "hscif1", "hscif0", "scif3",
706 "scif2", "scif1", "scif0";
707 };
08cafff6
SS		 708 mstp8_clks: mstp8_clks@e6150990 {
709 compatible = "renesas,r8a7792-mstp-clocks",
710 "renesas,cpg-mstp-clocks";
711 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
62855bcf
SS		 712 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
713 <&zg_clk>, <&zg_clk>, <&hp_clk>;
08cafff6 714 #clock-cells = <1>;
62855bcf
SS		 715 clock-indices = <
716 R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
717 R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
718 R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
719 R8A7792_CLK_ETHERAVB
720 >;
721 clock-output-names = "vin5", "vin4", "vin3", "vin2",
722 "vin1", "vin0", "etheravb";
08cafff6 723 };
4e2b4f66
SS		 724 mstp9_clks: mstp9_clks@e6150994 {
725 compatible = "renesas,r8a7792-mstp-clocks",
726 "renesas,cpg-mstp-clocks";
727 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
728 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
729 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
47db051c 730 <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
eedee25c
SS		 731 <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
732 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
4e2b4f66
SS		 733 #clock-cells = <1>;
734 clock-indices = <
735 R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
736 R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
737 R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
738 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
739 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
47db051c 740 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
4e2b4f66 741 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
eedee25c
SS		 742 R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
743 R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
744 R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
4e2b4f66
SS		 745 >;
746 clock-output-names =
747 "gpio7", "gpio6", "gpio5", "gpio4",
748 "gpio3", "gpio2", "gpio1", "gpio0",
47db051c 749 "gpio11", "gpio10", "can1", "can0",
eedee25c
SS		 750 "gpio9", "gpio8", "i2c5", "i2c4",
751 "i2c3", "i2c2", "i2c1", "i2c0";
4e2b4f66 752 };
7c4163aa
SS		 753 };
754
755 /* External root clock */
756 extal_clk: extal {
757 compatible = "fixed-clock";
758 #clock-cells = <0>;
759 /* This value must be overridden by the board. */
760 clock-frequency = <0>;
761 };
762
763 /* External SCIF clock */
764 scif_clk: scif {
765 compatible = "fixed-clock";
766 #clock-cells = <0>;
767 /* This value must be overridden by the board. */
768 clock-frequency = <0>;
769 };
47db051c
SS		 770
771 /* External CAN clock */
772 can_clk: can {
773 compatible = "fixed-clock";
774 #clock-cells = <0>;
775 /* This value must be overridden by the board. */
776 clock-frequency = <0>;
777 };
7c4163aa 778};
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