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ARM: dts: iwg22m: Add watchdog support to SoM dtsi
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / r8a7792.dtsi
CommitLineData
7c4163aa
SS		 1/*
2 * Device Tree Source for the r8a7792 SoC
3 *
4 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
762dbc44 11#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
7c4163aa
SS		 12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/power/r8a7792-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7792";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
78082700
SS		 21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
c9acea6e 28 spi0 = &qspi;
b0663cd4
SS		 29 spi1 = &msiof0;
30 spi2 = &msiof1;
a2d30b9c
SS		 31 vin0 = &vin0;
32 vin1 = &vin1;
33 vin2 = &vin2;
34 vin3 = &vin3;
35 vin4 = &vin4;
36 vin5 = &vin5;
d6f5fe84 37 };
78082700 38
c3d2c8d7
SH		 39 /* External CAN clock */
40 can_clk: can {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 /* This value must be overridden by the board. */
44 clock-frequency = <0>;
45 };
46
7c4163aa
SS		 47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
8fd763c7 50 enable-method = "renesas,apmu";
7c4163aa
SS		 51
52 cpu0: cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a15";
55 reg = <0>;
56 clock-frequency = <1000000000>;
762dbc44 57 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
7c4163aa
SS		 58 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
59 next-level-cache = <&L2_CA15>;
60 };
61
8fd763c7
SS		 62 cpu1: cpu@1 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a15";
65 reg = <1>;
66 clock-frequency = <1000000000>;
8684a24c 67 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
8fd763c7
SS		 68 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
69 next-level-cache = <&L2_CA15>;
70 };
71
a0504f08 72 L2_CA15: cache-controller-0 {
7c4163aa 73 compatible = "cache";
7c4163aa
SS		 74 cache-unified;
75 cache-level = <2>;
76 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
77 };
78 };
79
c3d2c8d7
SH		 80 /* External root clock */
81 extal_clk: extal {
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
84 /* This value must be overridden by the board. */
85 clock-frequency = <0>;
86 };
87
88 /* External SCIF clock */
89 scif_clk: scif {
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 /* This value must be overridden by the board. */
93 clock-frequency = <0>;
94 };
95
7c4163aa
SS		 96 soc {
97 compatible = "simple-bus";
98 interrupt-parent = <&gic>;
99
100 #address-cells = <2>;
101 #size-cells = <2>;
102 ranges;
103
63359c2d
SS		 104 gpio0: gpio@e6050000 {
105 compatible = "renesas,gpio-r8a7792",
7f4a16c4 106 "renesas,rcar-gen2-gpio";
63359c2d
SS		 107 reg = <0 0xe6050000 0 0x50>;
108 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
109 #gpio-cells = <2>;
110 gpio-controller;
111 gpio-ranges = <&pfc 0 0 29>;
112 #interrupt-cells = <2>;
113 interrupt-controller;
762dbc44 114 clocks = <&cpg CPG_MOD 912>;
63359c2d 115 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 116 resets = <&cpg 912>;
63359c2d
SS		 117 };
118
119 gpio1: gpio@e6051000 {
120 compatible = "renesas,gpio-r8a7792",
7f4a16c4 121 "renesas,rcar-gen2-gpio";
63359c2d
SS		 122 reg = <0 0xe6051000 0 0x50>;
123 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
124 #gpio-cells = <2>;
125 gpio-controller;
126 gpio-ranges = <&pfc 0 32 23>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
762dbc44 129 clocks = <&cpg CPG_MOD 911>;
63359c2d 130 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 131 resets = <&cpg 911>;
63359c2d
SS		 132 };
133
134 gpio2: gpio@e6052000 {
135 compatible = "renesas,gpio-r8a7792",
7f4a16c4 136 "renesas,rcar-gen2-gpio";
63359c2d
SS		 137 reg = <0 0xe6052000 0 0x50>;
138 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
139 #gpio-cells = <2>;
140 gpio-controller;
141 gpio-ranges = <&pfc 0 64 32>;
142 #interrupt-cells = <2>;
143 interrupt-controller;
762dbc44 144 clocks = <&cpg CPG_MOD 910>;
63359c2d 145 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 146 resets = <&cpg 910>;
63359c2d
SS		 147 };
148
149 gpio3: gpio@e6053000 {
150 compatible = "renesas,gpio-r8a7792",
7f4a16c4 151 "renesas,rcar-gen2-gpio";
63359c2d
SS		 152 reg = <0 0xe6053000 0 0x50>;
153 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
154 #gpio-cells = <2>;
155 gpio-controller;
156 gpio-ranges = <&pfc 0 96 28>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
762dbc44 159 clocks = <&cpg CPG_MOD 909>;
63359c2d 160 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 161 resets = <&cpg 909>;
63359c2d
SS		 162 };
163
164 gpio4: gpio@e6054000 {
165 compatible = "renesas,gpio-r8a7792",
7f4a16c4 166 "renesas,rcar-gen2-gpio";
63359c2d
SS		 167 reg = <0 0xe6054000 0 0x50>;
168 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
169 #gpio-cells = <2>;
170 gpio-controller;
171 gpio-ranges = <&pfc 0 128 17>;
172 #interrupt-cells = <2>;
173 interrupt-controller;
762dbc44 174 clocks = <&cpg CPG_MOD 908>;
63359c2d 175 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 176 resets = <&cpg 908>;
63359c2d
SS		 177 };
178
179 gpio5: gpio@e6055000 {
180 compatible = "renesas,gpio-r8a7792",
7f4a16c4 181 "renesas,rcar-gen2-gpio";
63359c2d
SS		 182 reg = <0 0xe6055000 0 0x50>;
183 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
184 #gpio-cells = <2>;
185 gpio-controller;
186 gpio-ranges = <&pfc 0 160 17>;
187 #interrupt-cells = <2>;
188 interrupt-controller;
762dbc44 189 clocks = <&cpg CPG_MOD 907>;
63359c2d 190 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 191 resets = <&cpg 907>;
63359c2d
SS		 192 };
193
194 gpio6: gpio@e6055100 {
195 compatible = "renesas,gpio-r8a7792",
7f4a16c4 196 "renesas,rcar-gen2-gpio";
63359c2d
SS		 197 reg = <0 0xe6055100 0 0x50>;
198 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
199 #gpio-cells = <2>;
200 gpio-controller;
201 gpio-ranges = <&pfc 0 192 17>;
202 #interrupt-cells = <2>;
203 interrupt-controller;
762dbc44 204 clocks = <&cpg CPG_MOD 905>;
63359c2d 205 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 206 resets = <&cpg 905>;
63359c2d
SS		 207 };
208
209 gpio7: gpio@e6055200 {
210 compatible = "renesas,gpio-r8a7792",
7f4a16c4 211 "renesas,rcar-gen2-gpio";
63359c2d
SS		 212 reg = <0 0xe6055200 0 0x50>;
213 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
214 #gpio-cells = <2>;
215 gpio-controller;
216 gpio-ranges = <&pfc 0 224 17>;
217 #interrupt-cells = <2>;
218 interrupt-controller;
762dbc44 219 clocks = <&cpg CPG_MOD 904>;
63359c2d 220 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 221 resets = <&cpg 904>;
63359c2d
SS		 222 };
223
224 gpio8: gpio@e6055300 {
225 compatible = "renesas,gpio-r8a7792",
7f4a16c4 226 "renesas,rcar-gen2-gpio";
63359c2d
SS		 227 reg = <0 0xe6055300 0 0x50>;
228 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
229 #gpio-cells = <2>;
230 gpio-controller;
231 gpio-ranges = <&pfc 0 256 17>;
232 #interrupt-cells = <2>;
233 interrupt-controller;
762dbc44 234 clocks = <&cpg CPG_MOD 921>;
63359c2d 235 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 236 resets = <&cpg 921>;
63359c2d
SS		 237 };
238
239 gpio9: gpio@e6055400 {
240 compatible = "renesas,gpio-r8a7792",
7f4a16c4 241 "renesas,rcar-gen2-gpio";
63359c2d
SS		 242 reg = <0 0xe6055400 0 0x50>;
243 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
244 #gpio-cells = <2>;
245 gpio-controller;
246 gpio-ranges = <&pfc 0 288 17>;
247 #interrupt-cells = <2>;
248 interrupt-controller;
762dbc44 249 clocks = <&cpg CPG_MOD 919>;
63359c2d 250 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 251 resets = <&cpg 919>;
63359c2d
SS		 252 };
253
254 gpio10: gpio@e6055500 {
255 compatible = "renesas,gpio-r8a7792",
7f4a16c4 256 "renesas,rcar-gen2-gpio";
63359c2d
SS		 257 reg = <0 0xe6055500 0 0x50>;
258 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
259 #gpio-cells = <2>;
260 gpio-controller;
261 gpio-ranges = <&pfc 0 320 32>;
262 #interrupt-cells = <2>;
263 interrupt-controller;
762dbc44 264 clocks = <&cpg CPG_MOD 914>;
63359c2d 265 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 266 resets = <&cpg 914>;
63359c2d
SS		 267 };
268
269 gpio11: gpio@e6055600 {
270 compatible = "renesas,gpio-r8a7792",
7f4a16c4 271 "renesas,rcar-gen2-gpio";
63359c2d
SS		 272 reg = <0 0xe6055600 0 0x50>;
273 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
274 #gpio-cells = <2>;
275 gpio-controller;
276 gpio-ranges = <&pfc 0 352 30>;
277 #interrupt-cells = <2>;
278 interrupt-controller;
762dbc44 279 clocks = <&cpg CPG_MOD 913>;
63359c2d 280 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 281 resets = <&cpg 913>;
63359c2d
SS		 282 };
283
3758e51b
SH		 284 pfc: pin-controller@e6060000 {
285 compatible = "renesas,pfc-r8a7792";
286 reg = <0 0xe6060000 0 0x144>;
287 };
288
289 cpg: clock-controller@e6150000 {
290 compatible = "renesas,r8a7792-cpg-mssr";
291 reg = <0 0xe6150000 0 0x1000>;
292 clocks = <&extal_clk>;
293 clock-names = "extal";
294 #clock-cells = <2>;
295 #power-domain-cells = <0>;
296 #reset-cells = <1>;
297 };
298
299 apmu@e6152000 {
300 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
301 reg = <0 0xe6152000 0 0x188>;
302 cpus = <&cpu0 &cpu1>;
303 };
304
305 rst: reset-controller@e6160000 {
306 compatible = "renesas,r8a7792-rst";
307 reg = <0 0xe6160000 0 0x0100>;
308 };
309
310 sysc: system-controller@e6180000 {
311 compatible = "renesas,r8a7792-sysc";
312 reg = <0 0xe6180000 0 0x0200>;
313 #power-domain-cells = <1>;
314 };
315
316 irqc: interrupt-controller@e61c0000 {
317 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
318 #interrupt-cells = <2>;
319 interrupt-controller;
320 reg = <0 0xe61c0000 0 0x200>;
321 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 407>;
326 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
327 resets = <&cpg 407>;
328 };
329
330 icram0: sram@e63a0000 {
331 compatible = "mmio-sram";
332 reg = <0 0xe63a0000 0 0x12000>;
333 };
334
335 icram1: sram@e63c0000 {
336 compatible = "mmio-sram";
337 reg = <0 0xe63c0000 0 0x1000>;
338 #address-cells = <1>;
339 #size-cells = <1>;
340 ranges = <0 0 0xe63c0000 0x1000>;
341
342 smp-sram@0 {
343 compatible = "renesas,smp-sram";
75f66650 344 reg = <0 0x100>;
3758e51b
SH		 345 };
346 };
347
348 /* I2C doesn't need pinmux */
349 i2c0: i2c@e6508000 {
350 compatible = "renesas,i2c-r8a7792",
351 "renesas,rcar-gen2-i2c";
352 reg = <0 0xe6508000 0 0x40>;
353 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&cpg CPG_MOD 931>;
355 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
356 resets = <&cpg 931>;
357 i2c-scl-internal-delay-ns = <6>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 status = "disabled";
361 };
362
363 i2c1: i2c@e6518000 {
364 compatible = "renesas,i2c-r8a7792",
365 "renesas,rcar-gen2-i2c";
366 reg = <0 0xe6518000 0 0x40>;
367 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&cpg CPG_MOD 930>;
369 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
370 resets = <&cpg 930>;
371 i2c-scl-internal-delay-ns = <6>;
372 #address-cells = <1>;
373 #size-cells = <0>;
374 status = "disabled";
375 };
376
377 i2c2: i2c@e6530000 {
378 compatible = "renesas,i2c-r8a7792",
379 "renesas,rcar-gen2-i2c";
380 reg = <0 0xe6530000 0 0x40>;
381 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&cpg CPG_MOD 929>;
383 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
384 resets = <&cpg 929>;
385 i2c-scl-internal-delay-ns = <6>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388 status = "disabled";
389 };
390
391 i2c3: i2c@e6540000 {
392 compatible = "renesas,i2c-r8a7792",
393 "renesas,rcar-gen2-i2c";
394 reg = <0 0xe6540000 0 0x40>;
395 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cpg CPG_MOD 928>;
397 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
398 resets = <&cpg 928>;
399 i2c-scl-internal-delay-ns = <6>;
400 #address-cells = <1>;
401 #size-cells = <0>;
402 status = "disabled";
403 };
404
405 i2c4: i2c@e6520000 {
406 compatible = "renesas,i2c-r8a7792",
407 "renesas,rcar-gen2-i2c";
408 reg = <0 0xe6520000 0 0x40>;
409 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&cpg CPG_MOD 927>;
411 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
412 resets = <&cpg 927>;
413 i2c-scl-internal-delay-ns = <6>;
414 #address-cells = <1>;
415 #size-cells = <0>;
416 status = "disabled";
417 };
418
419 i2c5: i2c@e6528000 {
420 compatible = "renesas,i2c-r8a7792",
421 "renesas,rcar-gen2-i2c";
422 reg = <0 0xe6528000 0 0x40>;
423 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&cpg CPG_MOD 925>;
425 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
426 resets = <&cpg 925>;
427 i2c-scl-internal-delay-ns = <110>;
428 #address-cells = <1>;
429 #size-cells = <0>;
430 status = "disabled";
431 };
432
fdf8ec0a
SS		 433 dmac0: dma-controller@e6700000 {
434 compatible = "renesas,dmac-r8a7792",
435 "renesas,rcar-dmac";
436 reg = <0 0xe6700000 0 0x20000>;
437 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
438 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
439 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
440 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
441 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
442 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
443 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
444 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
445 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
446 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
447 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
448 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
449 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
450 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
451 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
452 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
453 interrupt-names = "error",
454 "ch0", "ch1", "ch2", "ch3",
455 "ch4", "ch5", "ch6", "ch7",
456 "ch8", "ch9", "ch10", "ch11",
457 "ch12", "ch13", "ch14";
762dbc44 458 clocks = <&cpg CPG_MOD 219>;
fdf8ec0a
SS		 459 clock-names = "fck";
460 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 461 resets = <&cpg 219>;
fdf8ec0a
SS		 462 #dma-cells = <1>;
463 dma-channels = <15>;
464 };
465
466 dmac1: dma-controller@e6720000 {
467 compatible = "renesas,dmac-r8a7792",
468 "renesas,rcar-dmac";
469 reg = <0 0xe6720000 0 0x20000>;
470 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
471 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
472 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
473 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
474 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
475 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
476 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
477 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
478 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
479 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
480 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
481 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
482 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
483 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
484 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
485 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
486 interrupt-names = "error",
487 "ch0", "ch1", "ch2", "ch3",
488 "ch4", "ch5", "ch6", "ch7",
489 "ch8", "ch9", "ch10", "ch11",
490 "ch12", "ch13", "ch14";
762dbc44 491 clocks = <&cpg CPG_MOD 218>;
fdf8ec0a
SS		 492 clock-names = "fck";
493 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 494 resets = <&cpg 218>;
fdf8ec0a
SS		 495 #dma-cells = <1>;
496 dma-channels = <15>;
497 };
498
3758e51b
SH		 499 avb: ethernet@e6800000 {
500 compatible = "renesas,etheravb-r8a7792",
501 "renesas,etheravb-rcar-gen2";
502 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
503 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&cpg CPG_MOD 812>;
505 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
506 resets = <&cpg 812>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 status = "disabled";
510 };
511
512 qspi: spi@e6b10000 {
513 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
514 reg = <0 0xe6b10000 0 0x2c>;
515 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&cpg CPG_MOD 917>;
517 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
518 <&dmac1 0x17>, <&dmac1 0x18>;
519 dma-names = "tx", "rx", "tx", "rx";
520 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
521 resets = <&cpg 917>;
522 num-cs = <1>;
523 #address-cells = <1>;
524 #size-cells = <0>;
525 status = "disabled";
526 };
527
e66796b9
SS		 528 scif0: serial@e6e60000 {
529 compatible = "renesas,scif-r8a7792",
530 "renesas,rcar-gen2-scif", "renesas,scif";
531 reg = <0 0xe6e60000 0 64>;
532 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 533 clocks = <&cpg CPG_MOD 721>,
534 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 535 clock-names = "fck", "brg_int", "scif_clk";
536 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
537 <&dmac1 0x29>, <&dmac1 0x2a>;
538 dma-names = "tx", "rx", "tx", "rx";
539 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 540 resets = <&cpg 721>;
e66796b9
SS		 541 status = "disabled";
542 };
543
544 scif1: serial@e6e68000 {
545 compatible = "renesas,scif-r8a7792",
546 "renesas,rcar-gen2-scif", "renesas,scif";
547 reg = <0 0xe6e68000 0 64>;
548 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 549 clocks = <&cpg CPG_MOD 720>,
550 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 551 clock-names = "fck", "brg_int", "scif_clk";
552 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
553 <&dmac1 0x2d>, <&dmac1 0x2e>;
554 dma-names = "tx", "rx", "tx", "rx";
555 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 556 resets = <&cpg 720>;
e66796b9
SS		 557 status = "disabled";
558 };
559
560 scif2: serial@e6e58000 {
561 compatible = "renesas,scif-r8a7792",
562 "renesas,rcar-gen2-scif", "renesas,scif";
563 reg = <0 0xe6e58000 0 64>;
564 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 565 clocks = <&cpg CPG_MOD 719>,
566 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 567 clock-names = "fck", "brg_int", "scif_clk";
568 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
569 <&dmac1 0x2b>, <&dmac1 0x2c>;
570 dma-names = "tx", "rx", "tx", "rx";
571 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 572 resets = <&cpg 719>;
e66796b9
SS		 573 status = "disabled";
574 };
575
576 scif3: serial@e6ea8000 {
577 compatible = "renesas,scif-r8a7792",
578 "renesas,rcar-gen2-scif", "renesas,scif";
579 reg = <0 0xe6ea8000 0 64>;
580 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 581 clocks = <&cpg CPG_MOD 718>,
582 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 583 clock-names = "fck", "brg_int", "scif_clk";
584 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
585 <&dmac1 0x2f>, <&dmac1 0x30>;
586 dma-names = "tx", "rx", "tx", "rx";
587 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 588 resets = <&cpg 718>;
e66796b9
SS		 589 status = "disabled";
590 };
591
592 hscif0: serial@e62c0000 {
593 compatible = "renesas,hscif-r8a7792",
594 "renesas,rcar-gen2-hscif", "renesas,hscif";
595 reg = <0 0xe62c0000 0 96>;
596 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 597 clocks = <&cpg CPG_MOD 717>,
598 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 599 clock-names = "fck", "brg_int", "scif_clk";
600 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
601 <&dmac1 0x39>, <&dmac1 0x3a>;
602 dma-names = "tx", "rx", "tx", "rx";
603 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 604 resets = <&cpg 717>;
e66796b9
SS		 605 status = "disabled";
606 };
607
608 hscif1: serial@e62c8000 {
609 compatible = "renesas,hscif-r8a7792",
610 "renesas,rcar-gen2-hscif", "renesas,hscif";
611 reg = <0 0xe62c8000 0 96>;
612 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 613 clocks = <&cpg CPG_MOD 716>,
614 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
e66796b9
SS		 615 clock-names = "fck", "brg_int", "scif_clk";
616 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
617 <&dmac1 0x4d>, <&dmac1 0x4e>;
618 dma-names = "tx", "rx", "tx", "rx";
619 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 620 resets = <&cpg 716>;
e66796b9
SS		 621 status = "disabled";
622 };
623
b0663cd4 624 msiof0: spi@e6e20000 {
50a15093
SH		 625 compatible = "renesas,msiof-r8a7792",
626 "renesas,rcar-gen2-msiof";
b0663cd4
SS		 627 reg = <0 0xe6e20000 0 0x0064>;
628 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 629 clocks = <&cpg CPG_MOD 000>;
b0663cd4
SS		 630 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
631 <&dmac1 0x51>, <&dmac1 0x52>;
632 dma-names = "tx", "rx", "tx", "rx";
633 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 634 resets = <&cpg 000>;
b0663cd4
SS		 635 #address-cells = <1>;
636 #size-cells = <0>;
637 status = "disabled";
638 };
639
640 msiof1: spi@e6e10000 {
50a15093
SH		 641 compatible = "renesas,msiof-r8a7792",
642 "renesas,rcar-gen2-msiof";
b0663cd4
SS		 643 reg = <0 0xe6e10000 0 0x0064>;
644 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 645 clocks = <&cpg CPG_MOD 208>;
b0663cd4
SS		 646 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
647 <&dmac1 0x55>, <&dmac1 0x56>;
648 dma-names = "tx", "rx", "tx", "rx";
649 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 650 resets = <&cpg 208>;
b0663cd4
SS		 651 #address-cells = <1>;
652 #size-cells = <0>;
653 status = "disabled";
654 };
655
f947c02a
SS		 656 can0: can@e6e80000 {
657 compatible = "renesas,can-r8a7792",
658 "renesas,rcar-gen2-can";
659 reg = <0 0xe6e80000 0 0x1000>;
660 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 661 clocks = <&cpg CPG_MOD 916>,
662 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
f947c02a
SS		 663 clock-names = "clkp1", "clkp2", "can_clk";
664 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 665 resets = <&cpg 916>;
f947c02a
SS		 666 status = "disabled";
667 };
668
669 can1: can@e6e88000 {
670 compatible = "renesas,can-r8a7792",
671 "renesas,rcar-gen2-can";
672 reg = <0 0xe6e88000 0 0x1000>;
673 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
762dbc44
GU		 674 clocks = <&cpg CPG_MOD 915>,
675 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
f947c02a
SS		 676 clock-names = "clkp1", "clkp2", "can_clk";
677 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 678 resets = <&cpg 915>;
f947c02a
SS		 679 status = "disabled";
680 };
681
a2d30b9c
SS		 682 vin0: video@e6ef0000 {
683 compatible = "renesas,vin-r8a7792",
684 "renesas,rcar-gen2-vin";
685 reg = <0 0xe6ef0000 0 0x1000>;
686 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 687 clocks = <&cpg CPG_MOD 811>;
a2d30b9c 688 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 689 resets = <&cpg 811>;
a2d30b9c
SS		 690 status = "disabled";
691 };
692
693 vin1: video@e6ef1000 {
694 compatible = "renesas,vin-r8a7792",
695 "renesas,rcar-gen2-vin";
696 reg = <0 0xe6ef1000 0 0x1000>;
697 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 698 clocks = <&cpg CPG_MOD 810>;
a2d30b9c 699 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 700 resets = <&cpg 810>;
a2d30b9c
SS		 701 status = "disabled";
702 };
703
704 vin2: video@e6ef2000 {
705 compatible = "renesas,vin-r8a7792",
706 "renesas,rcar-gen2-vin";
707 reg = <0 0xe6ef2000 0 0x1000>;
708 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 709 clocks = <&cpg CPG_MOD 809>;
a2d30b9c 710 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 711 resets = <&cpg 809>;
a2d30b9c
SS		 712 status = "disabled";
713 };
714
715 vin3: video@e6ef3000 {
716 compatible = "renesas,vin-r8a7792",
717 "renesas,rcar-gen2-vin";
718 reg = <0 0xe6ef3000 0 0x1000>;
719 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 720 clocks = <&cpg CPG_MOD 808>;
a2d30b9c 721 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 722 resets = <&cpg 808>;
a2d30b9c
SS		 723 status = "disabled";
724 };
725
726 vin4: video@e6ef4000 {
727 compatible = "renesas,vin-r8a7792",
728 "renesas,rcar-gen2-vin";
729 reg = <0 0xe6ef4000 0 0x1000>;
730 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 731 clocks = <&cpg CPG_MOD 805>;
a2d30b9c 732 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 733 resets = <&cpg 805>;
a2d30b9c
SS		 734 status = "disabled";
735 };
736
737 vin5: video@e6ef5000 {
738 compatible = "renesas,vin-r8a7792",
739 "renesas,rcar-gen2-vin";
740 reg = <0 0xe6ef5000 0 0x1000>;
741 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 742 clocks = <&cpg CPG_MOD 804>;
a2d30b9c 743 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 744 resets = <&cpg 804>;
a2d30b9c
SS		 745 status = "disabled";
746 };
747
3758e51b
SH		 748 sdhi0: sd@ee100000 {
749 compatible = "renesas,sdhi-r8a7792",
750 "renesas,rcar-gen2-sdhi";
751 reg = <0 0xee100000 0 0x328>;
752 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
753 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
754 <&dmac1 0xcd>, <&dmac1 0xce>;
755 dma-names = "tx", "rx", "tx", "rx";
756 clocks = <&cpg CPG_MOD 314>;
757 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
758 resets = <&cpg 314>;
759 status = "disabled";
760 };
761
762 gic: interrupt-controller@f1001000 {
763 compatible = "arm,gic-400";
764 #interrupt-cells = <3>;
765 interrupt-controller;
766 reg = <0 0xf1001000 0 0x1000>,
767 <0 0xf1002000 0 0x2000>,
768 <0 0xf1004000 0 0x2000>,
769 <0 0xf1006000 0 0x2000>;
770 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
771 IRQ_TYPE_LEVEL_HIGH)>;
772 clocks = <&cpg CPG_MOD 408>;
773 clock-names = "clk";
774 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
775 resets = <&cpg 408>;
776 };
777
2ea2e06c 778 vsp@fe928000 {
9e1019c6
SS		 779 compatible = "renesas,vsp1";
780 reg = <0 0xfe928000 0 0x8000>;
781 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 782 clocks = <&cpg CPG_MOD 131>;
9e1019c6 783 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 784 resets = <&cpg 131>;
9e1019c6
SS		 785 };
786
2ea2e06c 787 vsp@fe930000 {
9e1019c6
SS		 788 compatible = "renesas,vsp1";
789 reg = <0 0xfe930000 0 0x8000>;
790 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 791 clocks = <&cpg CPG_MOD 128>;
9e1019c6 792 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 793 resets = <&cpg 128>;
9e1019c6
SS		 794 };
795
2ea2e06c 796 vsp@fe938000 {
9e1019c6
SS		 797 compatible = "renesas,vsp1";
798 reg = <0 0xfe938000 0 0x8000>;
799 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
762dbc44 800 clocks = <&cpg CPG_MOD 127>;
9e1019c6 801 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
6e11a322 802 resets = <&cpg 127>;
9e1019c6
SS		 803 };
804
3758e51b
SH		 805 jpu: jpeg-codec@fe980000 {
806 compatible = "renesas,jpu-r8a7792",
807 "renesas,rcar-gen2-jpu";
808 reg = <0 0xfe980000 0 0x10300>;
809 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&cpg CPG_MOD 106>;
811 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
812 resets = <&cpg 106>;
813 };
814
815 du: display@feb00000 {
816 compatible = "renesas,du-r8a7792";
817 reg = <0 0xfeb00000 0 0x40000>;
818 reg-names = "du";
819 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&cpg CPG_MOD 724>,
822 <&cpg CPG_MOD 723>;
823 clock-names = "du.0", "du.1";
824 status = "disabled";
825
826 ports {
827 #address-cells = <1>;
828 #size-cells = <0>;
829
830 port@0 {
831 reg = <0>;
832 du_out_rgb0: endpoint {
833 };
834 };
835 port@1 {
836 reg = <1>;
837 du_out_rgb1: endpoint {
838 };
839 };
840 };
841 };
842
843 prr: chipid@ff000044 {
844 compatible = "renesas,prr";
845 reg = <0 0xff000044 0 4>;
7c4163aa 846 };
7c4163aa
SS		 847 };
848
3da25909
SH		 849 timer {
850 compatible = "arm,armv7-timer";
851 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
852 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
853 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
854 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
47db051c 855 };
7c4163aa 856};
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