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ARM: dts: r8a7791: Use R-Car Gen 2 fallback binding for msiof nodes
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / r8a7792.dtsi
CommitLineData
7c4163aa
SS		 1/*
2 * Device Tree Source for the r8a7792 SoC
3 *
4 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7792-clock.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/power/r8a7792-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7792";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
78082700
SS		 21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
c9acea6e 28 spi0 = &qspi;
b0663cd4
SS		 29 spi1 = &msiof0;
30 spi2 = &msiof1;
a2d30b9c
SS		 31 vin0 = &vin0;
32 vin1 = &vin1;
33 vin2 = &vin2;
34 vin3 = &vin3;
35 vin4 = &vin4;
36 vin5 = &vin5;
d6f5fe84 37 };
78082700 38
7c4163aa
SS		 39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
8fd763c7 42 enable-method = "renesas,apmu";
7c4163aa
SS		 43
44 cpu0: cpu@0 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a15";
47 reg = <0>;
48 clock-frequency = <1000000000>;
49 clocks = <&cpg_clocks R8A7792_CLK_Z>;
50 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
51 next-level-cache = <&L2_CA15>;
52 };
53
8fd763c7
SS		 54 cpu1: cpu@1 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a15";
57 reg = <1>;
58 clock-frequency = <1000000000>;
59 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
60 next-level-cache = <&L2_CA15>;
61 };
62
7c4163aa
SS		 63 L2_CA15: cache-controller@0 {
64 compatible = "cache";
65 reg = <0>;
66 cache-unified;
67 cache-level = <2>;
68 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
69 };
70 };
71
72 soc {
73 compatible = "simple-bus";
74 interrupt-parent = <&gic>;
75
76 #address-cells = <2>;
77 #size-cells = <2>;
78 ranges;
79
8fd763c7
SS		 80 apmu@e6152000 {
81 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
82 reg = <0 0xe6152000 0 0x188>;
83 cpus = <&cpu0 &cpu1>;
84 };
85
7c4163aa
SS		 86 gic: interrupt-controller@f1001000 {
87 compatible = "arm,gic-400";
88 #interrupt-cells = <3>;
89 interrupt-controller;
90 reg = <0 0xf1001000 0 0x1000>,
91 <0 0xf1002000 0 0x1000>,
92 <0 0xf1004000 0 0x2000>,
93 <0 0xf1006000 0 0x2000>;
94 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
95 IRQ_TYPE_LEVEL_HIGH)>;
96 };
97
56efdbe5
SS		 98 irqc: interrupt-controller@e61c0000 {
99 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
100 #interrupt-cells = <2>;
101 interrupt-controller;
102 reg = <0 0xe61c0000 0 0x200>;
103 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
108 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
109 };
110
7c4163aa
SS		 111 timer {
112 compatible = "arm,armv7-timer";
113 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
114 IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
116 IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
118 IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
120 IRQ_TYPE_LEVEL_LOW)>;
121 };
122
d6f78ec4
GU		 123 rst: reset-controller@e6160000 {
124 compatible = "renesas,r8a7792-rst";
125 reg = <0 0xe6160000 0 0x0100>;
126 };
127
7cbae74e
GU		 128 prr: chipid@ff000044 {
129 compatible = "renesas,prr";
130 reg = <0 0xff000044 0 4>;
131 };
132
7c4163aa
SS		 133 sysc: system-controller@e6180000 {
134 compatible = "renesas,r8a7792-sysc";
135 reg = <0 0xe6180000 0 0x0200>;
136 #power-domain-cells = <1>;
137 };
138
02183a52
SS		 139 pfc: pin-controller@e6060000 {
140 compatible = "renesas,pfc-r8a7792";
141 reg = <0 0xe6060000 0 0x144>;
142 };
143
63359c2d
SS		 144 gpio0: gpio@e6050000 {
145 compatible = "renesas,gpio-r8a7792",
146 "renesas,gpio-rcar";
147 reg = <0 0xe6050000 0 0x50>;
148 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
149 #gpio-cells = <2>;
150 gpio-controller;
151 gpio-ranges = <&pfc 0 0 29>;
152 #interrupt-cells = <2>;
153 interrupt-controller;
154 clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
155 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
156 };
157
158 gpio1: gpio@e6051000 {
159 compatible = "renesas,gpio-r8a7792",
160 "renesas,gpio-rcar";
161 reg = <0 0xe6051000 0 0x50>;
162 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
163 #gpio-cells = <2>;
164 gpio-controller;
165 gpio-ranges = <&pfc 0 32 23>;
166 #interrupt-cells = <2>;
167 interrupt-controller;
168 clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
169 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
170 };
171
172 gpio2: gpio@e6052000 {
173 compatible = "renesas,gpio-r8a7792",
174 "renesas,gpio-rcar";
175 reg = <0 0xe6052000 0 0x50>;
176 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
177 #gpio-cells = <2>;
178 gpio-controller;
179 gpio-ranges = <&pfc 0 64 32>;
180 #interrupt-cells = <2>;
181 interrupt-controller;
182 clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
183 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
184 };
185
186 gpio3: gpio@e6053000 {
187 compatible = "renesas,gpio-r8a7792",
188 "renesas,gpio-rcar";
189 reg = <0 0xe6053000 0 0x50>;
190 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
191 #gpio-cells = <2>;
192 gpio-controller;
193 gpio-ranges = <&pfc 0 96 28>;
194 #interrupt-cells = <2>;
195 interrupt-controller;
196 clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
197 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
198 };
199
200 gpio4: gpio@e6054000 {
201 compatible = "renesas,gpio-r8a7792",
202 "renesas,gpio-rcar";
203 reg = <0 0xe6054000 0 0x50>;
204 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
205 #gpio-cells = <2>;
206 gpio-controller;
207 gpio-ranges = <&pfc 0 128 17>;
208 #interrupt-cells = <2>;
209 interrupt-controller;
210 clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
211 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
212 };
213
214 gpio5: gpio@e6055000 {
215 compatible = "renesas,gpio-r8a7792",
216 "renesas,gpio-rcar";
217 reg = <0 0xe6055000 0 0x50>;
218 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
219 #gpio-cells = <2>;
220 gpio-controller;
221 gpio-ranges = <&pfc 0 160 17>;
222 #interrupt-cells = <2>;
223 interrupt-controller;
224 clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
225 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
226 };
227
228 gpio6: gpio@e6055100 {
229 compatible = "renesas,gpio-r8a7792",
230 "renesas,gpio-rcar";
231 reg = <0 0xe6055100 0 0x50>;
232 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
233 #gpio-cells = <2>;
234 gpio-controller;
235 gpio-ranges = <&pfc 0 192 17>;
236 #interrupt-cells = <2>;
237 interrupt-controller;
238 clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
239 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
240 };
241
242 gpio7: gpio@e6055200 {
243 compatible = "renesas,gpio-r8a7792",
244 "renesas,gpio-rcar";
245 reg = <0 0xe6055200 0 0x50>;
246 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>;
248 gpio-controller;
249 gpio-ranges = <&pfc 0 224 17>;
250 #interrupt-cells = <2>;
251 interrupt-controller;
252 clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
253 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
254 };
255
256 gpio8: gpio@e6055300 {
257 compatible = "renesas,gpio-r8a7792",
258 "renesas,gpio-rcar";
259 reg = <0 0xe6055300 0 0x50>;
260 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
261 #gpio-cells = <2>;
262 gpio-controller;
263 gpio-ranges = <&pfc 0 256 17>;
264 #interrupt-cells = <2>;
265 interrupt-controller;
266 clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
267 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
268 };
269
270 gpio9: gpio@e6055400 {
271 compatible = "renesas,gpio-r8a7792",
272 "renesas,gpio-rcar";
273 reg = <0 0xe6055400 0 0x50>;
274 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
275 #gpio-cells = <2>;
276 gpio-controller;
277 gpio-ranges = <&pfc 0 288 17>;
278 #interrupt-cells = <2>;
279 interrupt-controller;
280 clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
281 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
282 };
283
284 gpio10: gpio@e6055500 {
285 compatible = "renesas,gpio-r8a7792",
286 "renesas,gpio-rcar";
287 reg = <0 0xe6055500 0 0x50>;
288 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
289 #gpio-cells = <2>;
290 gpio-controller;
291 gpio-ranges = <&pfc 0 320 32>;
292 #interrupt-cells = <2>;
293 interrupt-controller;
294 clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
295 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
296 };
297
298 gpio11: gpio@e6055600 {
299 compatible = "renesas,gpio-r8a7792",
300 "renesas,gpio-rcar";
301 reg = <0 0xe6055600 0 0x50>;
302 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
303 #gpio-cells = <2>;
304 gpio-controller;
305 gpio-ranges = <&pfc 0 352 30>;
306 #interrupt-cells = <2>;
307 interrupt-controller;
308 clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
309 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
310 };
311
fdf8ec0a
SS		 312 dmac0: dma-controller@e6700000 {
313 compatible = "renesas,dmac-r8a7792",
314 "renesas,rcar-dmac";
315 reg = <0 0xe6700000 0 0x20000>;
316 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-names = "error",
333 "ch0", "ch1", "ch2", "ch3",
334 "ch4", "ch5", "ch6", "ch7",
335 "ch8", "ch9", "ch10", "ch11",
336 "ch12", "ch13", "ch14";
337 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
338 clock-names = "fck";
339 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
340 #dma-cells = <1>;
341 dma-channels = <15>;
342 };
343
344 dmac1: dma-controller@e6720000 {
345 compatible = "renesas,dmac-r8a7792",
346 "renesas,rcar-dmac";
347 reg = <0 0xe6720000 0 0x20000>;
348 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
361 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
362 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
363 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
364 interrupt-names = "error",
365 "ch0", "ch1", "ch2", "ch3",
366 "ch4", "ch5", "ch6", "ch7",
367 "ch8", "ch9", "ch10", "ch11",
368 "ch12", "ch13", "ch14";
369 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
370 clock-names = "fck";
371 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
372 #dma-cells = <1>;
373 dma-channels = <15>;
374 };
375
e66796b9
SS		 376 scif0: serial@e6e60000 {
377 compatible = "renesas,scif-r8a7792",
378 "renesas,rcar-gen2-scif", "renesas,scif";
379 reg = <0 0xe6e60000 0 64>;
380 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
382 <&scif_clk>;
383 clock-names = "fck", "brg_int", "scif_clk";
384 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
385 <&dmac1 0x29>, <&dmac1 0x2a>;
386 dma-names = "tx", "rx", "tx", "rx";
387 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
388 status = "disabled";
389 };
390
391 scif1: serial@e6e68000 {
392 compatible = "renesas,scif-r8a7792",
393 "renesas,rcar-gen2-scif", "renesas,scif";
394 reg = <0 0xe6e68000 0 64>;
395 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
397 <&scif_clk>;
398 clock-names = "fck", "brg_int", "scif_clk";
399 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
400 <&dmac1 0x2d>, <&dmac1 0x2e>;
401 dma-names = "tx", "rx", "tx", "rx";
402 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
403 status = "disabled";
404 };
405
406 scif2: serial@e6e58000 {
407 compatible = "renesas,scif-r8a7792",
408 "renesas,rcar-gen2-scif", "renesas,scif";
409 reg = <0 0xe6e58000 0 64>;
410 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
412 <&scif_clk>;
413 clock-names = "fck", "brg_int", "scif_clk";
414 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
415 <&dmac1 0x2b>, <&dmac1 0x2c>;
416 dma-names = "tx", "rx", "tx", "rx";
417 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
418 status = "disabled";
419 };
420
421 scif3: serial@e6ea8000 {
422 compatible = "renesas,scif-r8a7792",
423 "renesas,rcar-gen2-scif", "renesas,scif";
424 reg = <0 0xe6ea8000 0 64>;
425 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
427 <&scif_clk>;
428 clock-names = "fck", "brg_int", "scif_clk";
429 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
430 <&dmac1 0x2f>, <&dmac1 0x30>;
431 dma-names = "tx", "rx", "tx", "rx";
432 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
433 status = "disabled";
434 };
435
436 hscif0: serial@e62c0000 {
437 compatible = "renesas,hscif-r8a7792",
438 "renesas,rcar-gen2-hscif", "renesas,hscif";
439 reg = <0 0xe62c0000 0 96>;
440 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
442 <&scif_clk>;
443 clock-names = "fck", "brg_int", "scif_clk";
444 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
445 <&dmac1 0x39>, <&dmac1 0x3a>;
446 dma-names = "tx", "rx", "tx", "rx";
447 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
448 status = "disabled";
449 };
450
451 hscif1: serial@e62c8000 {
452 compatible = "renesas,hscif-r8a7792",
453 "renesas,rcar-gen2-hscif", "renesas,hscif";
454 reg = <0 0xe62c8000 0 96>;
455 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
457 <&scif_clk>;
458 clock-names = "fck", "brg_int", "scif_clk";
459 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
460 <&dmac1 0x4d>, <&dmac1 0x4e>;
461 dma-names = "tx", "rx", "tx", "rx";
462 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
463 status = "disabled";
464 };
465
ce01b14e
SS		 466 sdhi0: sd@ee100000 {
467 compatible = "renesas,sdhi-r8a7792";
468 reg = <0 0xee100000 0 0x328>;
469 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
470 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
471 <&dmac1 0xcd>, <&dmac1 0xce>;
472 dma-names = "tx", "rx", "tx", "rx";
473 clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
474 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
475 status = "disabled";
476 };
477
3e1839e9
SS		 478 jpu: jpeg-codec@fe980000 {
479 compatible = "renesas,jpu-r8a7792",
480 "renesas,rcar-gen2-jpu";
481 reg = <0 0xfe980000 0 0x10300>;
482 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&mstp1_clks R8A7792_CLK_JPU>;
484 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
485 };
486
b12dcdcc
SS		 487 avb: ethernet@e6800000 {
488 compatible = "renesas,etheravb-r8a7792",
489 "renesas,etheravb-rcar-gen2";
490 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
491 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
493 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
494 #address-cells = <1>;
495 #size-cells = <0>;
496 status = "disabled";
497 };
498
78082700
SS		 499 /* I2C doesn't need pinmux */
500 i2c0: i2c@e6508000 {
cfcb93b3
SH		 501 compatible = "renesas,i2c-r8a7792",
502 "renesas,rcar-gen2-i2c";
78082700
SS		 503 reg = <0 0xe6508000 0 0x40>;
504 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
506 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
507 i2c-scl-internal-delay-ns = <6>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 status = "disabled";
511 };
512
513 i2c1: i2c@e6518000 {
cfcb93b3
SH		 514 compatible = "renesas,i2c-r8a7792",
515 "renesas,rcar-gen2-i2c";
78082700
SS		 516 reg = <0 0xe6518000 0 0x40>;
517 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
519 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
520 i2c-scl-internal-delay-ns = <6>;
521 #address-cells = <1>;
522 #size-cells = <0>;
523 status = "disabled";
524 };
525
526 i2c2: i2c@e6530000 {
cfcb93b3
SH		 527 compatible = "renesas,i2c-r8a7792",
528 "renesas,rcar-gen2-i2c";
78082700
SS		 529 reg = <0 0xe6530000 0 0x40>;
530 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
532 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
533 i2c-scl-internal-delay-ns = <6>;
534 #address-cells = <1>;
535 #size-cells = <0>;
536 status = "disabled";
537 };
538
539 i2c3: i2c@e6540000 {
cfcb93b3
SH		 540 compatible = "renesas,i2c-r8a7792",
541 "renesas,rcar-gen2-i2c";
78082700
SS		 542 reg = <0 0xe6540000 0 0x40>;
543 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
545 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
546 i2c-scl-internal-delay-ns = <6>;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 status = "disabled";
550 };
551
552 i2c4: i2c@e6520000 {
cfcb93b3
SH		 553 compatible = "renesas,i2c-r8a7792",
554 "renesas,rcar-gen2-i2c";
78082700
SS		 555 reg = <0 0xe6520000 0 0x40>;
556 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
558 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
559 i2c-scl-internal-delay-ns = <6>;
560 #address-cells = <1>;
561 #size-cells = <0>;
562 status = "disabled";
563 };
564
565 i2c5: i2c@e6528000 {
cfcb93b3
SH		 566 compatible = "renesas,i2c-r8a7792",
567 "renesas,rcar-gen2-i2c";
78082700
SS		 568 reg = <0 0xe6528000 0 0x40>;
569 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
571 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
572 i2c-scl-internal-delay-ns = <110>;
573 #address-cells = <1>;
c9acea6e
SS		 574 #size-cells = <0>;
575 status = "disabled";
576 };
577
578 qspi: spi@e6b10000 {
579 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
580 reg = <0 0xe6b10000 0 0x2c>;
581 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>;
583 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
584 <&dmac1 0x17>, <&dmac1 0x18>;
585 dma-names = "tx", "rx", "tx", "rx";
586 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
587 num-cs = <1>;
588 #address-cells = <1>;
78082700
SS		 589 #size-cells = <0>;
590 status = "disabled";
591 };
592
b0663cd4
SS		 593 msiof0: spi@e6e20000 {
594 compatible = "renesas,msiof-r8a7792";
595 reg = <0 0xe6e20000 0 0x0064>;
596 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>;
598 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
599 <&dmac1 0x51>, <&dmac1 0x52>;
600 dma-names = "tx", "rx", "tx", "rx";
601 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
602 #address-cells = <1>;
603 #size-cells = <0>;
604 status = "disabled";
605 };
606
607 msiof1: spi@e6e10000 {
608 compatible = "renesas,msiof-r8a7792";
609 reg = <0 0xe6e10000 0 0x0064>;
610 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>;
612 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
613 <&dmac1 0x55>, <&dmac1 0x56>;
614 dma-names = "tx", "rx", "tx", "rx";
615 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
616 #address-cells = <1>;
617 #size-cells = <0>;
618 status = "disabled";
619 };
620
8bec0842
SS		 621 du: display@feb00000 {
622 compatible = "renesas,du-r8a7792";
623 reg = <0 0xfeb00000 0 0x40000>;
624 reg-names = "du";
625 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&mstp7_clks R8A7792_CLK_DU0>,
628 <&mstp7_clks R8A7792_CLK_DU1>;
629 clock-names = "du.0", "du.1";
630 status = "disabled";
631
632 ports {
633 #address-cells = <1>;
634 #size-cells = <0>;
635
636 port@0 {
637 reg = <0>;
638 du_out_rgb0: endpoint {
639 };
640 };
641 port@1 {
642 reg = <1>;
643 du_out_rgb1: endpoint {
644 };
645 };
646 };
647 };
648
f947c02a
SS		 649 can0: can@e6e80000 {
650 compatible = "renesas,can-r8a7792",
651 "renesas,rcar-gen2-can";
652 reg = <0 0xe6e80000 0 0x1000>;
653 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
655 <&rcan_clk>, <&can_clk>;
656 clock-names = "clkp1", "clkp2", "can_clk";
657 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
658 status = "disabled";
659 };
660
661 can1: can@e6e88000 {
662 compatible = "renesas,can-r8a7792",
663 "renesas,rcar-gen2-can";
664 reg = <0 0xe6e88000 0 0x1000>;
665 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
667 <&rcan_clk>, <&can_clk>;
668 clock-names = "clkp1", "clkp2", "can_clk";
669 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
670 status = "disabled";
671 };
672
a2d30b9c
SS		 673 vin0: video@e6ef0000 {
674 compatible = "renesas,vin-r8a7792",
675 "renesas,rcar-gen2-vin";
676 reg = <0 0xe6ef0000 0 0x1000>;
677 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&mstp8_clks R8A7792_CLK_VIN0>;
679 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
680 status = "disabled";
681 };
682
683 vin1: video@e6ef1000 {
684 compatible = "renesas,vin-r8a7792",
685 "renesas,rcar-gen2-vin";
686 reg = <0 0xe6ef1000 0 0x1000>;
687 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&mstp8_clks R8A7792_CLK_VIN1>;
689 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
690 status = "disabled";
691 };
692
693 vin2: video@e6ef2000 {
694 compatible = "renesas,vin-r8a7792",
695 "renesas,rcar-gen2-vin";
696 reg = <0 0xe6ef2000 0 0x1000>;
697 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&mstp8_clks R8A7792_CLK_VIN2>;
699 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
700 status = "disabled";
701 };
702
703 vin3: video@e6ef3000 {
704 compatible = "renesas,vin-r8a7792",
705 "renesas,rcar-gen2-vin";
706 reg = <0 0xe6ef3000 0 0x1000>;
707 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&mstp8_clks R8A7792_CLK_VIN3>;
709 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
710 status = "disabled";
711 };
712
713 vin4: video@e6ef4000 {
714 compatible = "renesas,vin-r8a7792",
715 "renesas,rcar-gen2-vin";
716 reg = <0 0xe6ef4000 0 0x1000>;
717 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&mstp8_clks R8A7792_CLK_VIN4>;
719 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
720 status = "disabled";
721 };
722
723 vin5: video@e6ef5000 {
724 compatible = "renesas,vin-r8a7792",
725 "renesas,rcar-gen2-vin";
726 reg = <0 0xe6ef5000 0 0x1000>;
727 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&mstp8_clks R8A7792_CLK_VIN5>;
729 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
730 status = "disabled";
731 };
732
9e1019c6
SS		 733 vsp1@fe928000 {
734 compatible = "renesas,vsp1";
735 reg = <0 0xfe928000 0 0x8000>;
736 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>;
738 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
739 };
740
741 vsp1@fe930000 {
742 compatible = "renesas,vsp1";
743 reg = <0 0xfe930000 0 0x8000>;
744 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>;
746 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
747 };
748
749 vsp1@fe938000 {
750 compatible = "renesas,vsp1";
751 reg = <0 0xfe938000 0 0x8000>;
752 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>;
754 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
755 };
756
7c4163aa
SS		 757 /* Special CPG clocks */
758 cpg_clocks: cpg_clocks@e6150000 {
759 compatible = "renesas,r8a7792-cpg-clocks",
760 "renesas,rcar-gen2-cpg-clocks";
761 reg = <0 0xe6150000 0 0x1000>;
762 clocks = <&extal_clk>;
763 #clock-cells = <1>;
764 clock-output-names = "main", "pll0", "pll1", "pll3",
e0c3f92a 765 "lb", "qspi", "z";
7c4163aa
SS		 766 #power-domain-cells = <0>;
767 };
768
769 /* Fixed factor clocks */
4b9b7b3a
SS		 770 pll1_div2_clk: pll1_div2 {
771 compatible = "fixed-factor-clock";
772 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
773 #clock-cells = <0>;
774 clock-div = <2>;
775 clock-mult = <1>;
776 };
3b0211af
SS		 777 zx_clk: zx {
778 compatible = "fixed-factor-clock";
779 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
780 #clock-cells = <0>;
781 clock-div = <3>;
782 clock-mult = <1>;
783 };
7c4163aa
SS		 784 zs_clk: zs {
785 compatible = "fixed-factor-clock";
786 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
787 #clock-cells = <0>;
788 clock-div = <6>;
789 clock-mult = <1>;
790 };
08cafff6
SS		 791 hp_clk: hp {
792 compatible = "fixed-factor-clock";
793 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
794 #clock-cells = <0>;
795 clock-div = <12>;
796 clock-mult = <1>;
797 };
7c4163aa
SS		 798 p_clk: p {
799 compatible = "fixed-factor-clock";
800 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
801 #clock-cells = <0>;
802 clock-div = <24>;
803 clock-mult = <1>;
804 };
805 cp_clk: cp {
806 compatible = "fixed-factor-clock";
807 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
808 #clock-cells = <0>;
809 clock-div = <48>;
810 clock-mult = <1>;
811 };
5cef452b
SS		 812 mp_clk: mp {
813 compatible = "fixed-factor-clock";
814 clocks = <&pll1_div2_clk>;
815 #clock-cells = <0>;
816 clock-div = <15>;
817 clock-mult = <1>;
818 };
eebc8e2c
SS		 819 m2_clk: m2 {
820 compatible = "fixed-factor-clock";
821 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
822 #clock-cells = <0>;
823 clock-div = <8>;
824 clock-mult = <1>;
825 };
fe683922
SS		 826 sd_clk: sd {
827 compatible = "fixed-factor-clock";
828 clocks = <&pll1_div2_clk>;
829 #clock-cells = <0>;
830 clock-div = <8>;
831 clock-mult = <1>;
832 };
47db051c
SS		 833 rcan_clk: rcan {
834 compatible = "fixed-factor-clock";
835 clocks = <&pll1_div2_clk>;
836 #clock-cells = <0>;
837 clock-div = <49>;
838 clock-mult = <1>;
839 };
62855bcf
SS		 840 zg_clk: zg {
841 compatible = "fixed-factor-clock";
842 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
843 #clock-cells = <0>;
844 clock-div = <5>;
845 clock-mult = <1>;
846 };
7c4163aa
SS		 847
848 /* Gate clocks */
5cef452b
SS		 849 mstp0_clks: mstp0_clks@e6150130 {
850 compatible = "renesas,r8a7792-mstp-clocks",
851 "renesas,cpg-mstp-clocks";
852 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
853 clocks = <&mp_clk>;
854 #clock-cells = <1>;
855 clock-indices = <R8A7792_CLK_MSIOF0>;
856 clock-output-names = "msiof0";
857 };
eebc8e2c
SS		 858 mstp1_clks: mstp1_clks@e6150134 {
859 compatible = "renesas,r8a7792-mstp-clocks",
860 "renesas,cpg-mstp-clocks";
861 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
5c2312ba 862 clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
eebc8e2c 863 #clock-cells = <1>;
5c2312ba
SS		 864 clock-indices = <
865 R8A7792_CLK_JPU
866 R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0
867 R8A7792_CLK_VSP1_SY
868 >;
869 clock-output-names = "jpu", "vsp1du1", "vsp1du0",
870 "vsp1-sy";
eebc8e2c 871 };
7c4163aa
SS		 872 mstp2_clks: mstp2_clks@e6150138 {
873 compatible = "renesas,r8a7792-mstp-clocks",
874 "renesas,cpg-mstp-clocks";
875 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
5cef452b 876 clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>;
7c4163aa
SS		 877 #clock-cells = <1>;
878 clock-indices = <
5cef452b 879 R8A7792_CLK_MSIOF1
7c4163aa
SS		 880 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
881 >;
5cef452b 882 clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0";
7c4163aa 883 };
fe683922
SS		 884 mstp3_clks: mstp3_clks@e615013c {
885 compatible = "renesas,r8a7792-mstp-clocks",
886 "renesas,cpg-mstp-clocks";
887 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
888 clocks = <&sd_clk>;
889 #clock-cells = <1>;
890 renesas,clock-indices = <R8A7792_CLK_SDHI0>;
891 clock-output-names = "sdhi0";
892 };
7c4163aa
SS		 893 mstp4_clks: mstp4_clks@e6150140 {
894 compatible = "renesas,r8a7792-mstp-clocks",
895 "renesas,cpg-mstp-clocks";
896 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
897 clocks = <&cp_clk>;
898 #clock-cells = <1>;
899 clock-indices = <R8A7792_CLK_IRQC>;
900 clock-output-names = "irqc";
901 };
902 mstp7_clks: mstp7_clks@e615014c {
903 compatible = "renesas,r8a7792-mstp-clocks",
904 "renesas,cpg-mstp-clocks";
905 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
906 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
3b0211af 907 <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
7c4163aa
SS		 908 #clock-cells = <1>;
909 clock-indices = <
910 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
911 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
912 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
3b0211af 913 R8A7792_CLK_DU1 R8A7792_CLK_DU0
7c4163aa
SS		 914 >;
915 clock-output-names = "hscif1", "hscif0", "scif3",
3b0211af
SS		 916 "scif2", "scif1", "scif0",
917 "du1", "du0";
7c4163aa 918 };
08cafff6
SS		 919 mstp8_clks: mstp8_clks@e6150990 {
920 compatible = "renesas,r8a7792-mstp-clocks",
921 "renesas,cpg-mstp-clocks";
922 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
62855bcf
SS		 923 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
924 <&zg_clk>, <&zg_clk>, <&hp_clk>;
08cafff6 925 #clock-cells = <1>;
62855bcf
SS		 926 clock-indices = <
927 R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
928 R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
929 R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
930 R8A7792_CLK_ETHERAVB
931 >;
932 clock-output-names = "vin5", "vin4", "vin3", "vin2",
933 "vin1", "vin0", "etheravb";
08cafff6 934 };
4e2b4f66
SS		 935 mstp9_clks: mstp9_clks@e6150994 {
936 compatible = "renesas,r8a7792-mstp-clocks",
937 "renesas,cpg-mstp-clocks";
938 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
939 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
940 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
47db051c 941 <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
4719d8f9 942 <&cpg_clocks R8A7792_CLK_QSPI>,
eedee25c
SS		 943 <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
944 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
4e2b4f66
SS		 945 #clock-cells = <1>;
946 clock-indices = <
947 R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
948 R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
949 R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
950 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
951 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
47db051c 952 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
4719d8f9 953 R8A7792_CLK_QSPI_MOD
4e2b4f66 954 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
eedee25c
SS		 955 R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
956 R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
957 R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
4e2b4f66
SS		 958 >;
959 clock-output-names =
960 "gpio7", "gpio6", "gpio5", "gpio4",
961 "gpio3", "gpio2", "gpio1", "gpio0",
47db051c 962 "gpio11", "gpio10", "can1", "can0",
4719d8f9
SS		 963 "qspi_mod", "gpio9", "gpio8",
964 "i2c5", "i2c4", "i2c3", "i2c2",
965 "i2c1", "i2c0";
4e2b4f66 966 };
7c4163aa
SS		 967 };
968
969 /* External root clock */
970 extal_clk: extal {
971 compatible = "fixed-clock";
972 #clock-cells = <0>;
973 /* This value must be overridden by the board. */
974 clock-frequency = <0>;
975 };
976
977 /* External SCIF clock */
978 scif_clk: scif {
979 compatible = "fixed-clock";
980 #clock-cells = <0>;
981 /* This value must be overridden by the board. */
982 clock-frequency = <0>;
983 };
47db051c
SS		 984
985 /* External CAN clock */
986 can_clk: can {
987 compatible = "fixed-clock";
988 #clock-cells = <0>;
989 /* This value must be overridden by the board. */
990 clock-frequency = <0>;
991 };
7c4163aa 992};
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