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0dce5454 UH |
1 | /* |
2 | * Device Tree Source for the r8a7794 SoC | |
3 | * | |
4 | * Copyright (C) 2014 Renesas Electronics Corporation | |
5 | * Copyright (C) 2014 Ulrich Hecht | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <dt-bindings/clock/r8a7794-clock.h> | |
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
14 | #include <dt-bindings/interrupt-controller/irq.h> | |
15 | ||
16 | / { | |
17 | compatible = "renesas,r8a7794"; | |
18 | interrupt-parent = <&gic>; | |
19 | #address-cells = <2>; | |
20 | #size-cells = <2>; | |
21 | ||
740b4a9f | 22 | aliases { |
5428521b SS |
23 | i2c0 = &i2c0; |
24 | i2c1 = &i2c1; | |
25 | i2c2 = &i2c2; | |
26 | i2c3 = &i2c3; | |
27 | i2c4 = &i2c4; | |
28 | i2c5 = &i2c5; | |
740b4a9f | 29 | spi0 = &qspi; |
1afe77ca SS |
30 | vin0 = &vin0; |
31 | vin1 = &vin1; | |
740b4a9f SS |
32 | }; |
33 | ||
0dce5454 UH |
34 | cpus { |
35 | #address-cells = <1>; | |
36 | #size-cells = <0>; | |
37 | ||
38 | cpu0: cpu@0 { | |
39 | device_type = "cpu"; | |
40 | compatible = "arm,cortex-a7"; | |
41 | reg = <0>; | |
42 | clock-frequency = <1000000000>; | |
d12a384a | 43 | next-level-cache = <&L2_CA7>; |
0dce5454 UH |
44 | }; |
45 | ||
46 | cpu1: cpu@1 { | |
47 | device_type = "cpu"; | |
48 | compatible = "arm,cortex-a7"; | |
49 | reg = <1>; | |
50 | clock-frequency = <1000000000>; | |
d12a384a | 51 | next-level-cache = <&L2_CA7>; |
0dce5454 UH |
52 | }; |
53 | }; | |
54 | ||
d12a384a GU |
55 | L2_CA7: cache-controller@1 { |
56 | compatible = "cache"; | |
57 | cache-unified; | |
58 | cache-level = <2>; | |
59 | }; | |
60 | ||
0dce5454 | 61 | gic: interrupt-controller@f1001000 { |
c73ddf42 | 62 | compatible = "arm,gic-400"; |
0dce5454 UH |
63 | #interrupt-cells = <3>; |
64 | #address-cells = <0>; | |
65 | interrupt-controller; | |
66 | reg = <0 0xf1001000 0 0x1000>, | |
67 | <0 0xf1002000 0 0x1000>, | |
68 | <0 0xf1004000 0 0x2000>, | |
69 | <0 0xf1006000 0 0x2000>; | |
8d47e6af | 70 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
0dce5454 UH |
71 | }; |
72 | ||
e8f5de3b SS |
73 | gpio0: gpio@e6050000 { |
74 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
75 | reg = <0 0xe6050000 0 0x50>; | |
8d47e6af | 76 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
e8f5de3b SS |
77 | #gpio-cells = <2>; |
78 | gpio-controller; | |
79 | gpio-ranges = <&pfc 0 0 32>; | |
80 | #interrupt-cells = <2>; | |
81 | interrupt-controller; | |
82 | clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; | |
83 | power-domains = <&cpg_clocks>; | |
84 | }; | |
85 | ||
86 | gpio1: gpio@e6051000 { | |
87 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
88 | reg = <0 0xe6051000 0 0x50>; | |
8d47e6af | 89 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
e8f5de3b SS |
90 | #gpio-cells = <2>; |
91 | gpio-controller; | |
92 | gpio-ranges = <&pfc 0 32 26>; | |
93 | #interrupt-cells = <2>; | |
94 | interrupt-controller; | |
95 | clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; | |
96 | power-domains = <&cpg_clocks>; | |
97 | }; | |
98 | ||
99 | gpio2: gpio@e6052000 { | |
100 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
101 | reg = <0 0xe6052000 0 0x50>; | |
8d47e6af | 102 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
e8f5de3b SS |
103 | #gpio-cells = <2>; |
104 | gpio-controller; | |
105 | gpio-ranges = <&pfc 0 64 32>; | |
106 | #interrupt-cells = <2>; | |
107 | interrupt-controller; | |
108 | clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; | |
109 | power-domains = <&cpg_clocks>; | |
110 | }; | |
111 | ||
112 | gpio3: gpio@e6053000 { | |
113 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
114 | reg = <0 0xe6053000 0 0x50>; | |
8d47e6af | 115 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
e8f5de3b SS |
116 | #gpio-cells = <2>; |
117 | gpio-controller; | |
118 | gpio-ranges = <&pfc 0 96 32>; | |
119 | #interrupt-cells = <2>; | |
120 | interrupt-controller; | |
121 | clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; | |
122 | power-domains = <&cpg_clocks>; | |
123 | }; | |
124 | ||
125 | gpio4: gpio@e6054000 { | |
126 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
127 | reg = <0 0xe6054000 0 0x50>; | |
8d47e6af | 128 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
e8f5de3b SS |
129 | #gpio-cells = <2>; |
130 | gpio-controller; | |
131 | gpio-ranges = <&pfc 0 128 32>; | |
132 | #interrupt-cells = <2>; | |
133 | interrupt-controller; | |
134 | clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; | |
135 | power-domains = <&cpg_clocks>; | |
136 | }; | |
137 | ||
138 | gpio5: gpio@e6055000 { | |
139 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
140 | reg = <0 0xe6055000 0 0x50>; | |
8d47e6af | 141 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
e8f5de3b SS |
142 | #gpio-cells = <2>; |
143 | gpio-controller; | |
144 | gpio-ranges = <&pfc 0 160 28>; | |
145 | #interrupt-cells = <2>; | |
146 | interrupt-controller; | |
147 | clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; | |
148 | power-domains = <&cpg_clocks>; | |
149 | }; | |
150 | ||
151 | gpio6: gpio@e6055400 { | |
152 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
153 | reg = <0 0xe6055400 0 0x50>; | |
8d47e6af | 154 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
e8f5de3b SS |
155 | #gpio-cells = <2>; |
156 | gpio-controller; | |
157 | gpio-ranges = <&pfc 0 192 26>; | |
158 | #interrupt-cells = <2>; | |
159 | interrupt-controller; | |
160 | clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; | |
161 | power-domains = <&cpg_clocks>; | |
162 | }; | |
163 | ||
0dce5454 UH |
164 | cmt0: timer@ffca0000 { |
165 | compatible = "renesas,cmt-48-gen2"; | |
166 | reg = <0 0xffca0000 0 0x1004>; | |
8d47e6af SH |
167 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
168 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
0dce5454 UH |
169 | clocks = <&mstp1_clks R8A7794_CLK_CMT0>; |
170 | clock-names = "fck"; | |
60c0745a | 171 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
172 | |
173 | renesas,channels-mask = <0x60>; | |
174 | ||
175 | status = "disabled"; | |
176 | }; | |
177 | ||
178 | cmt1: timer@e6130000 { | |
179 | compatible = "renesas,cmt-48-gen2"; | |
180 | reg = <0 0xe6130000 0 0x1004>; | |
8d47e6af SH |
181 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
182 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
183 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
184 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
185 | <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, | |
186 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, | |
187 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, | |
188 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
0dce5454 UH |
189 | clocks = <&mstp3_clks R8A7794_CLK_CMT1>; |
190 | clock-names = "fck"; | |
60c0745a | 191 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
192 | |
193 | renesas,channels-mask = <0xff>; | |
194 | ||
195 | status = "disabled"; | |
196 | }; | |
197 | ||
da33648c HN |
198 | timer { |
199 | compatible = "arm,armv7-timer"; | |
8d47e6af SH |
200 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
201 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
202 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
203 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
da33648c HN |
204 | }; |
205 | ||
0dce5454 UH |
206 | irqc0: interrupt-controller@e61c0000 { |
207 | compatible = "renesas,irqc-r8a7794", "renesas,irqc"; | |
208 | #interrupt-cells = <2>; | |
209 | interrupt-controller; | |
210 | reg = <0 0xe61c0000 0 0x200>; | |
8d47e6af SH |
211 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
212 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
213 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
214 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
215 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
216 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
217 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
218 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | |
219 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | |
220 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
1c5ca5db | 221 | clocks = <&mstp4_clks R8A7794_CLK_IRQC>; |
60c0745a | 222 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
223 | }; |
224 | ||
fd1683c1 SS |
225 | pfc: pin-controller@e6060000 { |
226 | compatible = "renesas,pfc-r8a7794"; | |
227 | reg = <0 0xe6060000 0 0x11c>; | |
fd1683c1 SS |
228 | }; |
229 | ||
bd847485 | 230 | dmac0: dma-controller@e6700000 { |
0a3d058b | 231 | compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; |
bd847485 | 232 | reg = <0 0xe6700000 0 0x20000>; |
8d47e6af SH |
233 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH |
234 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH | |
235 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH | |
236 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH | |
237 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH | |
238 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH | |
239 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH | |
240 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH | |
241 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH | |
242 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH | |
243 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH | |
244 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH | |
245 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH | |
246 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH | |
247 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH | |
248 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; | |
bd847485 LP |
249 | interrupt-names = "error", |
250 | "ch0", "ch1", "ch2", "ch3", | |
251 | "ch4", "ch5", "ch6", "ch7", | |
252 | "ch8", "ch9", "ch10", "ch11", | |
253 | "ch12", "ch13", "ch14"; | |
254 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; | |
255 | clock-names = "fck"; | |
60c0745a | 256 | power-domains = <&cpg_clocks>; |
bd847485 LP |
257 | #dma-cells = <1>; |
258 | dma-channels = <15>; | |
259 | }; | |
260 | ||
261 | dmac1: dma-controller@e6720000 { | |
0a3d058b | 262 | compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; |
bd847485 | 263 | reg = <0 0xe6720000 0 0x20000>; |
8d47e6af SH |
264 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
265 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH | |
266 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH | |
267 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH | |
268 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH | |
269 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH | |
270 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH | |
271 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH | |
272 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH | |
273 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH | |
274 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH | |
275 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH | |
276 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH | |
277 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH | |
278 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH | |
279 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; | |
bd847485 LP |
280 | interrupt-names = "error", |
281 | "ch0", "ch1", "ch2", "ch3", | |
282 | "ch4", "ch5", "ch6", "ch7", | |
283 | "ch8", "ch9", "ch10", "ch11", | |
284 | "ch12", "ch13", "ch14"; | |
285 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; | |
286 | clock-names = "fck"; | |
60c0745a | 287 | power-domains = <&cpg_clocks>; |
bd847485 LP |
288 | #dma-cells = <1>; |
289 | dma-channels = <15>; | |
290 | }; | |
291 | ||
0dce5454 | 292 | scifa0: serial@e6c40000 { |
06930a1f GU |
293 | compatible = "renesas,scifa-r8a7794", |
294 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
0dce5454 | 295 | reg = <0 0xe6c40000 0 64>; |
8d47e6af | 296 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
0dce5454 | 297 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; |
1b463bd5 | 298 | clock-names = "fck"; |
8233a0de GU |
299 | dmas = <&dmac0 0x21>, <&dmac0 0x22>; |
300 | dma-names = "tx", "rx"; | |
60c0745a | 301 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
302 | status = "disabled"; |
303 | }; | |
304 | ||
305 | scifa1: serial@e6c50000 { | |
06930a1f GU |
306 | compatible = "renesas,scifa-r8a7794", |
307 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
0dce5454 | 308 | reg = <0 0xe6c50000 0 64>; |
8d47e6af | 309 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
0dce5454 | 310 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; |
1b463bd5 | 311 | clock-names = "fck"; |
8233a0de GU |
312 | dmas = <&dmac0 0x25>, <&dmac0 0x26>; |
313 | dma-names = "tx", "rx"; | |
60c0745a | 314 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
315 | status = "disabled"; |
316 | }; | |
317 | ||
318 | scifa2: serial@e6c60000 { | |
06930a1f GU |
319 | compatible = "renesas,scifa-r8a7794", |
320 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
0dce5454 | 321 | reg = <0 0xe6c60000 0 64>; |
8d47e6af | 322 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; |
0dce5454 | 323 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; |
1b463bd5 | 324 | clock-names = "fck"; |
8233a0de GU |
325 | dmas = <&dmac0 0x27>, <&dmac0 0x28>; |
326 | dma-names = "tx", "rx"; | |
60c0745a | 327 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
328 | status = "disabled"; |
329 | }; | |
330 | ||
331 | scifa3: serial@e6c70000 { | |
06930a1f GU |
332 | compatible = "renesas,scifa-r8a7794", |
333 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
0dce5454 | 334 | reg = <0 0xe6c70000 0 64>; |
8d47e6af | 335 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
0dce5454 | 336 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; |
1b463bd5 | 337 | clock-names = "fck"; |
8233a0de GU |
338 | dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; |
339 | dma-names = "tx", "rx"; | |
60c0745a | 340 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
341 | status = "disabled"; |
342 | }; | |
343 | ||
344 | scifa4: serial@e6c78000 { | |
06930a1f GU |
345 | compatible = "renesas,scifa-r8a7794", |
346 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
0dce5454 | 347 | reg = <0 0xe6c78000 0 64>; |
8d47e6af | 348 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
0dce5454 | 349 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; |
1b463bd5 | 350 | clock-names = "fck"; |
8233a0de GU |
351 | dmas = <&dmac0 0x1f>, <&dmac0 0x20>; |
352 | dma-names = "tx", "rx"; | |
60c0745a | 353 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
354 | status = "disabled"; |
355 | }; | |
356 | ||
357 | scifa5: serial@e6c80000 { | |
06930a1f GU |
358 | compatible = "renesas,scifa-r8a7794", |
359 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
0dce5454 | 360 | reg = <0 0xe6c80000 0 64>; |
8d47e6af | 361 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
0dce5454 | 362 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; |
1b463bd5 | 363 | clock-names = "fck"; |
8233a0de GU |
364 | dmas = <&dmac0 0x23>, <&dmac0 0x24>; |
365 | dma-names = "tx", "rx"; | |
60c0745a | 366 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
367 | status = "disabled"; |
368 | }; | |
369 | ||
370 | scifb0: serial@e6c20000 { | |
06930a1f GU |
371 | compatible = "renesas,scifb-r8a7794", |
372 | "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
0dce5454 | 373 | reg = <0 0xe6c20000 0 64>; |
8d47e6af | 374 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
0dce5454 | 375 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; |
1b463bd5 | 376 | clock-names = "fck"; |
8233a0de GU |
377 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; |
378 | dma-names = "tx", "rx"; | |
60c0745a | 379 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
380 | status = "disabled"; |
381 | }; | |
382 | ||
383 | scifb1: serial@e6c30000 { | |
06930a1f GU |
384 | compatible = "renesas,scifb-r8a7794", |
385 | "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
0dce5454 | 386 | reg = <0 0xe6c30000 0 64>; |
8d47e6af | 387 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
0dce5454 | 388 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; |
1b463bd5 | 389 | clock-names = "fck"; |
8233a0de GU |
390 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>; |
391 | dma-names = "tx", "rx"; | |
60c0745a | 392 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
393 | status = "disabled"; |
394 | }; | |
395 | ||
396 | scifb2: serial@e6ce0000 { | |
06930a1f GU |
397 | compatible = "renesas,scifb-r8a7794", |
398 | "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
0dce5454 | 399 | reg = <0 0xe6ce0000 0 64>; |
8d47e6af | 400 | interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; |
0dce5454 | 401 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; |
1b463bd5 | 402 | clock-names = "fck"; |
8233a0de GU |
403 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; |
404 | dma-names = "tx", "rx"; | |
60c0745a | 405 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
406 | status = "disabled"; |
407 | }; | |
408 | ||
409 | scif0: serial@e6e60000 { | |
06930a1f GU |
410 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
411 | "renesas,scif"; | |
0dce5454 | 412 | reg = <0 0xe6e60000 0 64>; |
8d47e6af | 413 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
a864446f GU |
414 | clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>, |
415 | <&scif_clk>; | |
416 | clock-names = "fck", "brg_int", "scif_clk"; | |
8233a0de GU |
417 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>; |
418 | dma-names = "tx", "rx"; | |
60c0745a | 419 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
420 | status = "disabled"; |
421 | }; | |
422 | ||
423 | scif1: serial@e6e68000 { | |
06930a1f GU |
424 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
425 | "renesas,scif"; | |
0dce5454 | 426 | reg = <0 0xe6e68000 0 64>; |
8d47e6af | 427 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
a864446f GU |
428 | clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>, |
429 | <&scif_clk>; | |
430 | clock-names = "fck", "brg_int", "scif_clk"; | |
8233a0de GU |
431 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; |
432 | dma-names = "tx", "rx"; | |
60c0745a | 433 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
434 | status = "disabled"; |
435 | }; | |
436 | ||
437 | scif2: serial@e6e58000 { | |
06930a1f GU |
438 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
439 | "renesas,scif"; | |
0dce5454 | 440 | reg = <0 0xe6e58000 0 64>; |
8d47e6af | 441 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
a864446f GU |
442 | clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>, |
443 | <&scif_clk>; | |
444 | clock-names = "fck", "brg_int", "scif_clk"; | |
8233a0de GU |
445 | dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; |
446 | dma-names = "tx", "rx"; | |
60c0745a | 447 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
448 | status = "disabled"; |
449 | }; | |
450 | ||
451 | scif3: serial@e6ea8000 { | |
06930a1f GU |
452 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
453 | "renesas,scif"; | |
0dce5454 | 454 | reg = <0 0xe6ea8000 0 64>; |
8d47e6af | 455 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
a864446f GU |
456 | clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>, |
457 | <&scif_clk>; | |
458 | clock-names = "fck", "brg_int", "scif_clk"; | |
8233a0de GU |
459 | dmas = <&dmac0 0x2f>, <&dmac0 0x30>; |
460 | dma-names = "tx", "rx"; | |
60c0745a | 461 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
462 | status = "disabled"; |
463 | }; | |
464 | ||
465 | scif4: serial@e6ee0000 { | |
06930a1f GU |
466 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
467 | "renesas,scif"; | |
0dce5454 | 468 | reg = <0 0xe6ee0000 0 64>; |
8d47e6af | 469 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
a864446f GU |
470 | clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>, |
471 | <&scif_clk>; | |
472 | clock-names = "fck", "brg_int", "scif_clk"; | |
8233a0de GU |
473 | dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; |
474 | dma-names = "tx", "rx"; | |
60c0745a | 475 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
476 | status = "disabled"; |
477 | }; | |
478 | ||
479 | scif5: serial@e6ee8000 { | |
06930a1f GU |
480 | compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", |
481 | "renesas,scif"; | |
0dce5454 | 482 | reg = <0 0xe6ee8000 0 64>; |
8d47e6af | 483 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
a864446f GU |
484 | clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>, |
485 | <&scif_clk>; | |
486 | clock-names = "fck", "brg_int", "scif_clk"; | |
8233a0de GU |
487 | dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; |
488 | dma-names = "tx", "rx"; | |
60c0745a | 489 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
490 | status = "disabled"; |
491 | }; | |
492 | ||
493 | hscif0: serial@e62c0000 { | |
06930a1f GU |
494 | compatible = "renesas,hscif-r8a7794", |
495 | "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
0dce5454 | 496 | reg = <0 0xe62c0000 0 96>; |
8d47e6af | 497 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
a864446f GU |
498 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>, |
499 | <&scif_clk>; | |
500 | clock-names = "fck", "brg_int", "scif_clk"; | |
8233a0de GU |
501 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>; |
502 | dma-names = "tx", "rx"; | |
60c0745a | 503 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
504 | status = "disabled"; |
505 | }; | |
506 | ||
507 | hscif1: serial@e62c8000 { | |
06930a1f GU |
508 | compatible = "renesas,hscif-r8a7794", |
509 | "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
0dce5454 | 510 | reg = <0 0xe62c8000 0 96>; |
8d47e6af | 511 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
a864446f GU |
512 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>, |
513 | <&scif_clk>; | |
514 | clock-names = "fck", "brg_int", "scif_clk"; | |
8233a0de GU |
515 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; |
516 | dma-names = "tx", "rx"; | |
60c0745a | 517 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
518 | status = "disabled"; |
519 | }; | |
520 | ||
521 | hscif2: serial@e62d0000 { | |
06930a1f GU |
522 | compatible = "renesas,hscif-r8a7794", |
523 | "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
0dce5454 | 524 | reg = <0 0xe62d0000 0 96>; |
8d47e6af | 525 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
a864446f GU |
526 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>, |
527 | <&scif_clk>; | |
528 | clock-names = "fck", "brg_int", "scif_clk"; | |
8233a0de GU |
529 | dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; |
530 | dma-names = "tx", "rx"; | |
60c0745a | 531 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
532 | status = "disabled"; |
533 | }; | |
534 | ||
82818d34 LP |
535 | ether: ethernet@ee700000 { |
536 | compatible = "renesas,ether-r8a7794"; | |
537 | reg = <0 0xee700000 0 0x400>; | |
8d47e6af | 538 | interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; |
82818d34 | 539 | clocks = <&mstp8_clks R8A7794_CLK_ETHER>; |
60c0745a | 540 | power-domains = <&cpg_clocks>; |
82818d34 LP |
541 | phy-mode = "rmii"; |
542 | #address-cells = <1>; | |
543 | #size-cells = <0>; | |
544 | status = "disabled"; | |
545 | }; | |
546 | ||
89aac8af SS |
547 | avb: ethernet@e6800000 { |
548 | compatible = "renesas,etheravb-r8a7794", | |
549 | "renesas,etheravb-rcar-gen2"; | |
550 | reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; | |
551 | interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; | |
552 | clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>; | |
553 | power-domains = <&cpg_clocks>; | |
554 | #address-cells = <1>; | |
555 | #size-cells = <0>; | |
556 | status = "disabled"; | |
557 | }; | |
558 | ||
5428521b SS |
559 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
560 | i2c0: i2c@e6508000 { | |
561 | compatible = "renesas,i2c-r8a7794"; | |
562 | reg = <0 0xe6508000 0 0x40>; | |
8d47e6af | 563 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
5428521b SS |
564 | clocks = <&mstp9_clks R8A7794_CLK_I2C0>; |
565 | power-domains = <&cpg_clocks>; | |
566 | #address-cells = <1>; | |
567 | #size-cells = <0>; | |
691cd0a6 | 568 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
569 | status = "disabled"; |
570 | }; | |
571 | ||
572 | i2c1: i2c@e6518000 { | |
573 | compatible = "renesas,i2c-r8a7794"; | |
574 | reg = <0 0xe6518000 0 0x40>; | |
8d47e6af | 575 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
5428521b SS |
576 | clocks = <&mstp9_clks R8A7794_CLK_I2C1>; |
577 | power-domains = <&cpg_clocks>; | |
578 | #address-cells = <1>; | |
579 | #size-cells = <0>; | |
691cd0a6 | 580 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
581 | status = "disabled"; |
582 | }; | |
583 | ||
584 | i2c2: i2c@e6530000 { | |
585 | compatible = "renesas,i2c-r8a7794"; | |
586 | reg = <0 0xe6530000 0 0x40>; | |
8d47e6af | 587 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
5428521b SS |
588 | clocks = <&mstp9_clks R8A7794_CLK_I2C2>; |
589 | power-domains = <&cpg_clocks>; | |
590 | #address-cells = <1>; | |
591 | #size-cells = <0>; | |
691cd0a6 | 592 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
593 | status = "disabled"; |
594 | }; | |
595 | ||
596 | i2c3: i2c@e6540000 { | |
597 | compatible = "renesas,i2c-r8a7794"; | |
598 | reg = <0 0xe6540000 0 0x40>; | |
8d47e6af | 599 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
5428521b SS |
600 | clocks = <&mstp9_clks R8A7794_CLK_I2C3>; |
601 | power-domains = <&cpg_clocks>; | |
602 | #address-cells = <1>; | |
603 | #size-cells = <0>; | |
691cd0a6 | 604 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
605 | status = "disabled"; |
606 | }; | |
607 | ||
608 | i2c4: i2c@e6520000 { | |
609 | compatible = "renesas,i2c-r8a7794"; | |
610 | reg = <0 0xe6520000 0 0x40>; | |
8d47e6af | 611 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
5428521b SS |
612 | clocks = <&mstp9_clks R8A7794_CLK_I2C4>; |
613 | power-domains = <&cpg_clocks>; | |
614 | #address-cells = <1>; | |
615 | #size-cells = <0>; | |
691cd0a6 | 616 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
617 | status = "disabled"; |
618 | }; | |
619 | ||
620 | i2c5: i2c@e6528000 { | |
621 | compatible = "renesas,i2c-r8a7794"; | |
622 | reg = <0 0xe6528000 0 0x40>; | |
8d47e6af | 623 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
5428521b SS |
624 | clocks = <&mstp9_clks R8A7794_CLK_I2C5>; |
625 | power-domains = <&cpg_clocks>; | |
626 | #address-cells = <1>; | |
627 | #size-cells = <0>; | |
691cd0a6 | 628 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
629 | status = "disabled"; |
630 | }; | |
631 | ||
6cdf6ba1 SS |
632 | mmcif0: mmc@ee200000 { |
633 | compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; | |
634 | reg = <0 0xee200000 0 0x80>; | |
8d47e6af | 635 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
6cdf6ba1 SS |
636 | clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; |
637 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; | |
638 | dma-names = "tx", "rx"; | |
60c0745a | 639 | power-domains = <&cpg_clocks>; |
6cdf6ba1 SS |
640 | reg-io-width = <4>; |
641 | status = "disabled"; | |
642 | }; | |
643 | ||
b8e8ea12 SS |
644 | sdhi0: sd@ee100000 { |
645 | compatible = "renesas,sdhi-r8a7794"; | |
646 | reg = <0 0xee100000 0 0x200>; | |
8d47e6af | 647 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
b8e8ea12 | 648 | clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; |
60c0745a | 649 | power-domains = <&cpg_clocks>; |
b8e8ea12 SS |
650 | status = "disabled"; |
651 | }; | |
652 | ||
653 | sdhi1: sd@ee140000 { | |
654 | compatible = "renesas,sdhi-r8a7794"; | |
655 | reg = <0 0xee140000 0 0x100>; | |
8d47e6af | 656 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
b8e8ea12 | 657 | clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; |
60c0745a | 658 | power-domains = <&cpg_clocks>; |
b8e8ea12 SS |
659 | status = "disabled"; |
660 | }; | |
661 | ||
662 | sdhi2: sd@ee160000 { | |
663 | compatible = "renesas,sdhi-r8a7794"; | |
664 | reg = <0 0xee160000 0 0x100>; | |
8d47e6af | 665 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
b8e8ea12 | 666 | clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; |
60c0745a | 667 | power-domains = <&cpg_clocks>; |
b8e8ea12 SS |
668 | status = "disabled"; |
669 | }; | |
670 | ||
740b4a9f SS |
671 | qspi: spi@e6b10000 { |
672 | compatible = "renesas,qspi-r8a7794", "renesas,qspi"; | |
673 | reg = <0 0xe6b10000 0 0x2c>; | |
8d47e6af | 674 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
740b4a9f SS |
675 | clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; |
676 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; | |
677 | dma-names = "tx", "rx"; | |
678 | power-domains = <&cpg_clocks>; | |
679 | num-cs = <1>; | |
680 | #address-cells = <1>; | |
681 | #size-cells = <0>; | |
682 | status = "disabled"; | |
683 | }; | |
684 | ||
1afe77ca SS |
685 | vin0: video@e6ef0000 { |
686 | compatible = "renesas,vin-r8a7794"; | |
687 | reg = <0 0xe6ef0000 0 0x1000>; | |
8d47e6af | 688 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
1afe77ca SS |
689 | clocks = <&mstp8_clks R8A7794_CLK_VIN0>; |
690 | power-domains = <&cpg_clocks>; | |
691 | status = "disabled"; | |
692 | }; | |
693 | ||
694 | vin1: video@e6ef1000 { | |
695 | compatible = "renesas,vin-r8a7794"; | |
696 | reg = <0 0xe6ef1000 0 0x1000>; | |
8d47e6af | 697 | interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; |
1afe77ca SS |
698 | clocks = <&mstp8_clks R8A7794_CLK_VIN1>; |
699 | power-domains = <&cpg_clocks>; | |
700 | status = "disabled"; | |
701 | }; | |
702 | ||
a6a130b3 | 703 | pci0: pci@ee090000 { |
c99fbe64 | 704 | compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; |
a6a130b3 SS |
705 | device_type = "pci"; |
706 | reg = <0 0xee090000 0 0xc00>, | |
707 | <0 0xee080000 0 0x1100>; | |
8d47e6af | 708 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
a6a130b3 SS |
709 | clocks = <&mstp7_clks R8A7794_CLK_EHCI>; |
710 | power-domains = <&cpg_clocks>; | |
711 | status = "disabled"; | |
712 | ||
713 | bus-range = <0 0>; | |
714 | #address-cells = <3>; | |
715 | #size-cells = <2>; | |
716 | #interrupt-cells = <1>; | |
717 | ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; | |
718 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
8d47e6af SH |
719 | interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH |
720 | 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH | |
721 | 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
45cb0bd7 SS |
722 | |
723 | usb@0,1 { | |
724 | reg = <0x800 0 0 0 0>; | |
725 | device_type = "pci"; | |
726 | phys = <&usb0 0>; | |
727 | phy-names = "usb"; | |
728 | }; | |
729 | ||
730 | usb@0,2 { | |
731 | reg = <0x1000 0 0 0 0>; | |
732 | device_type = "pci"; | |
733 | phys = <&usb0 0>; | |
734 | phy-names = "usb"; | |
735 | }; | |
a6a130b3 SS |
736 | }; |
737 | ||
738 | pci1: pci@ee0d0000 { | |
c99fbe64 | 739 | compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; |
a6a130b3 SS |
740 | device_type = "pci"; |
741 | reg = <0 0xee0d0000 0 0xc00>, | |
742 | <0 0xee0c0000 0 0x1100>; | |
8d47e6af | 743 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
a6a130b3 SS |
744 | clocks = <&mstp7_clks R8A7794_CLK_EHCI>; |
745 | power-domains = <&cpg_clocks>; | |
746 | status = "disabled"; | |
747 | ||
748 | bus-range = <1 1>; | |
749 | #address-cells = <3>; | |
750 | #size-cells = <2>; | |
751 | #interrupt-cells = <1>; | |
752 | ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; | |
753 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
8d47e6af SH |
754 | interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH |
755 | 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH | |
756 | 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
45cb0bd7 SS |
757 | |
758 | usb@0,1 { | |
759 | reg = <0x800 0 0 0 0>; | |
760 | device_type = "pci"; | |
761 | phys = <&usb2 0>; | |
762 | phy-names = "usb"; | |
763 | }; | |
764 | ||
765 | usb@0,2 { | |
766 | reg = <0x1000 0 0 0 0>; | |
767 | device_type = "pci"; | |
768 | phys = <&usb2 0>; | |
769 | phy-names = "usb"; | |
770 | }; | |
a6a130b3 SS |
771 | }; |
772 | ||
2f33b9f7 | 773 | hsusb: usb@e6590000 { |
1472ffa8 | 774 | compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs"; |
2f33b9f7 | 775 | reg = <0 0xe6590000 0 0x100>; |
8d47e6af | 776 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
2f33b9f7 SS |
777 | clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; |
778 | power-domains = <&cpg_clocks>; | |
779 | renesas,buswait = <4>; | |
780 | phys = <&usb0 1>; | |
781 | phy-names = "usb"; | |
782 | status = "disabled"; | |
783 | }; | |
784 | ||
74ef4572 SS |
785 | usbphy: usb-phy@e6590100 { |
786 | compatible = "renesas,usb-phy-r8a7794"; | |
787 | reg = <0 0xe6590100 0 0x100>; | |
788 | #address-cells = <1>; | |
789 | #size-cells = <0>; | |
790 | clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; | |
791 | clock-names = "usbhs"; | |
792 | power-domains = <&cpg_clocks>; | |
793 | status = "disabled"; | |
794 | ||
795 | usb0: usb-channel@0 { | |
796 | reg = <0>; | |
797 | #phy-cells = <1>; | |
798 | }; | |
799 | usb2: usb-channel@2 { | |
800 | reg = <2>; | |
801 | #phy-cells = <1>; | |
802 | }; | |
803 | }; | |
804 | ||
46c4f13d LP |
805 | du: display@feb00000 { |
806 | compatible = "renesas,du-r8a7794"; | |
807 | reg = <0 0xfeb00000 0 0x40000>; | |
808 | reg-names = "du"; | |
8d47e6af SH |
809 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
810 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; | |
46c4f13d LP |
811 | clocks = <&mstp7_clks R8A7794_CLK_DU0>, |
812 | <&mstp7_clks R8A7794_CLK_DU0>; | |
813 | clock-names = "du.0", "du.1"; | |
814 | status = "disabled"; | |
815 | ||
816 | ports { | |
817 | #address-cells = <1>; | |
818 | #size-cells = <0>; | |
819 | ||
820 | port@0 { | |
821 | reg = <0>; | |
822 | du_out_rgb0: endpoint { | |
823 | }; | |
824 | }; | |
825 | port@1 { | |
826 | reg = <1>; | |
827 | du_out_rgb1: endpoint { | |
828 | }; | |
829 | }; | |
830 | }; | |
831 | }; | |
832 | ||
9f1c1a2c SH |
833 | can0: can@e6e80000 { |
834 | compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; | |
835 | reg = <0 0xe6e80000 0 0x1000>; | |
836 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; | |
837 | clocks = <&mstp9_clks R8A7794_CLK_RCAN0>, | |
838 | <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; | |
839 | clock-names = "clkp1", "clkp2", "can_clk"; | |
840 | power-domains = <&cpg_clocks>; | |
841 | status = "disabled"; | |
842 | }; | |
843 | ||
844 | can1: can@e6e88000 { | |
845 | compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; | |
846 | reg = <0 0xe6e88000 0 0x1000>; | |
847 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
848 | clocks = <&mstp9_clks R8A7794_CLK_RCAN1>, | |
849 | <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; | |
850 | clock-names = "clkp1", "clkp2", "can_clk"; | |
851 | power-domains = <&cpg_clocks>; | |
852 | status = "disabled"; | |
853 | }; | |
854 | ||
0dce5454 UH |
855 | clocks { |
856 | #address-cells = <2>; | |
857 | #size-cells = <2>; | |
858 | ranges; | |
859 | ||
860 | /* External root clock */ | |
337f6bef | 861 | extal_clk: extal { |
0dce5454 UH |
862 | compatible = "fixed-clock"; |
863 | #clock-cells = <0>; | |
864 | /* This value must be overriden by the board. */ | |
865 | clock-frequency = <0>; | |
0dce5454 UH |
866 | }; |
867 | ||
e980f941 SH |
868 | /* External USB clock - can be overridden by the board */ |
869 | usb_extal_clk: usb_extal { | |
870 | compatible = "fixed-clock"; | |
871 | #clock-cells = <0>; | |
872 | clock-frequency = <48000000>; | |
873 | }; | |
874 | ||
875 | /* External CAN clock */ | |
876 | can_clk: can { | |
877 | compatible = "fixed-clock"; | |
878 | #clock-cells = <0>; | |
879 | /* This value must be overridden by the board. */ | |
880 | clock-frequency = <0>; | |
881 | status = "disabled"; | |
882 | }; | |
883 | ||
a864446f GU |
884 | /* External SCIF clock */ |
885 | scif_clk: scif { | |
886 | compatible = "fixed-clock"; | |
887 | #clock-cells = <0>; | |
888 | /* This value must be overridden by the board. */ | |
889 | clock-frequency = <0>; | |
890 | status = "disabled"; | |
891 | }; | |
892 | ||
0dce5454 UH |
893 | /* Special CPG clocks */ |
894 | cpg_clocks: cpg_clocks@e6150000 { | |
895 | compatible = "renesas,r8a7794-cpg-clocks", | |
896 | "renesas,rcar-gen2-cpg-clocks"; | |
897 | reg = <0 0xe6150000 0 0x1000>; | |
e980f941 | 898 | clocks = <&extal_clk &usb_extal_clk>; |
0dce5454 UH |
899 | #clock-cells = <1>; |
900 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
e980f941 SH |
901 | "lb", "qspi", "sdh", "sd0", "z", |
902 | "rcan"; | |
60c0745a | 903 | #power-domain-cells = <0>; |
0dce5454 | 904 | }; |
8e181633 | 905 | /* Variable factor clocks */ |
337f6bef | 906 | sd2_clk: sd2@e6150078 { |
8e181633 SU |
907 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
908 | reg = <0 0xe6150078 0 4>; | |
909 | clocks = <&pll1_div2_clk>; | |
910 | #clock-cells = <0>; | |
8e181633 | 911 | }; |
337f6bef | 912 | sd3_clk: sd3@e615026c { |
8e181633 | 913 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
5e7e1554 | 914 | reg = <0 0xe615026c 0 4>; |
8e181633 SU |
915 | clocks = <&pll1_div2_clk>; |
916 | #clock-cells = <0>; | |
8e181633 | 917 | }; |
337f6bef | 918 | mmc0_clk: mmc0@e6150240 { |
deac150c SU |
919 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
920 | reg = <0 0xe6150240 0 4>; | |
921 | clocks = <&pll1_div2_clk>; | |
922 | #clock-cells = <0>; | |
deac150c | 923 | }; |
0dce5454 UH |
924 | |
925 | /* Fixed factor clocks */ | |
337f6bef | 926 | pll1_div2_clk: pll1_div2 { |
0dce5454 UH |
927 | compatible = "fixed-factor-clock"; |
928 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
929 | #clock-cells = <0>; | |
930 | clock-div = <2>; | |
931 | clock-mult = <1>; | |
0dce5454 | 932 | }; |
337f6bef | 933 | zg_clk: zg { |
0dce5454 UH |
934 | compatible = "fixed-factor-clock"; |
935 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
936 | #clock-cells = <0>; | |
937 | clock-div = <6>; | |
938 | clock-mult = <1>; | |
0dce5454 | 939 | }; |
337f6bef | 940 | zx_clk: zx { |
0dce5454 UH |
941 | compatible = "fixed-factor-clock"; |
942 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
943 | #clock-cells = <0>; | |
944 | clock-div = <3>; | |
945 | clock-mult = <1>; | |
0dce5454 | 946 | }; |
337f6bef | 947 | zs_clk: zs { |
0dce5454 UH |
948 | compatible = "fixed-factor-clock"; |
949 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
950 | #clock-cells = <0>; | |
951 | clock-div = <6>; | |
952 | clock-mult = <1>; | |
0dce5454 | 953 | }; |
337f6bef | 954 | hp_clk: hp { |
0dce5454 UH |
955 | compatible = "fixed-factor-clock"; |
956 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
957 | #clock-cells = <0>; | |
958 | clock-div = <12>; | |
959 | clock-mult = <1>; | |
0dce5454 | 960 | }; |
337f6bef | 961 | i_clk: i { |
0dce5454 UH |
962 | compatible = "fixed-factor-clock"; |
963 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
964 | #clock-cells = <0>; | |
965 | clock-div = <2>; | |
966 | clock-mult = <1>; | |
0dce5454 | 967 | }; |
337f6bef | 968 | b_clk: b { |
0dce5454 UH |
969 | compatible = "fixed-factor-clock"; |
970 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
971 | #clock-cells = <0>; | |
972 | clock-div = <12>; | |
973 | clock-mult = <1>; | |
0dce5454 | 974 | }; |
337f6bef | 975 | p_clk: p { |
0dce5454 UH |
976 | compatible = "fixed-factor-clock"; |
977 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
978 | #clock-cells = <0>; | |
979 | clock-div = <24>; | |
980 | clock-mult = <1>; | |
0dce5454 | 981 | }; |
337f6bef | 982 | cl_clk: cl { |
0dce5454 UH |
983 | compatible = "fixed-factor-clock"; |
984 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
985 | #clock-cells = <0>; | |
986 | clock-div = <48>; | |
987 | clock-mult = <1>; | |
0dce5454 | 988 | }; |
337f6bef | 989 | m2_clk: m2 { |
0dce5454 UH |
990 | compatible = "fixed-factor-clock"; |
991 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
992 | #clock-cells = <0>; | |
993 | clock-div = <8>; | |
994 | clock-mult = <1>; | |
0dce5454 | 995 | }; |
337f6bef | 996 | rclk_clk: rclk { |
0dce5454 UH |
997 | compatible = "fixed-factor-clock"; |
998 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
999 | #clock-cells = <0>; | |
1000 | clock-div = <(48 * 1024)>; | |
1001 | clock-mult = <1>; | |
0dce5454 | 1002 | }; |
337f6bef | 1003 | oscclk_clk: oscclk { |
0dce5454 UH |
1004 | compatible = "fixed-factor-clock"; |
1005 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
1006 | #clock-cells = <0>; | |
1007 | clock-div = <(12 * 1024)>; | |
1008 | clock-mult = <1>; | |
0dce5454 | 1009 | }; |
337f6bef | 1010 | zb3_clk: zb3 { |
0dce5454 UH |
1011 | compatible = "fixed-factor-clock"; |
1012 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
1013 | #clock-cells = <0>; | |
1014 | clock-div = <4>; | |
1015 | clock-mult = <1>; | |
0dce5454 | 1016 | }; |
337f6bef | 1017 | zb3d2_clk: zb3d2 { |
0dce5454 UH |
1018 | compatible = "fixed-factor-clock"; |
1019 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
1020 | #clock-cells = <0>; | |
1021 | clock-div = <8>; | |
1022 | clock-mult = <1>; | |
0dce5454 | 1023 | }; |
337f6bef | 1024 | ddr_clk: ddr { |
0dce5454 UH |
1025 | compatible = "fixed-factor-clock"; |
1026 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
1027 | #clock-cells = <0>; | |
1028 | clock-div = <8>; | |
1029 | clock-mult = <1>; | |
0dce5454 | 1030 | }; |
337f6bef | 1031 | mp_clk: mp { |
0dce5454 UH |
1032 | compatible = "fixed-factor-clock"; |
1033 | clocks = <&pll1_div2_clk>; | |
1034 | #clock-cells = <0>; | |
1035 | clock-div = <15>; | |
1036 | clock-mult = <1>; | |
0dce5454 | 1037 | }; |
337f6bef | 1038 | cp_clk: cp { |
0dce5454 UH |
1039 | compatible = "fixed-factor-clock"; |
1040 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
1041 | #clock-cells = <0>; | |
1042 | clock-div = <48>; | |
1043 | clock-mult = <1>; | |
0dce5454 UH |
1044 | }; |
1045 | ||
337f6bef | 1046 | acp_clk: acp { |
0dce5454 UH |
1047 | compatible = "fixed-factor-clock"; |
1048 | clocks = <&extal_clk>; | |
1049 | #clock-cells = <0>; | |
1050 | clock-div = <2>; | |
1051 | clock-mult = <1>; | |
0dce5454 UH |
1052 | }; |
1053 | ||
1054 | /* Gate clocks */ | |
1055 | mstp0_clks: mstp0_clks@e6150130 { | |
1056 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1057 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
1058 | clocks = <&mp_clk>; | |
1059 | #clock-cells = <1>; | |
1045d065 | 1060 | clock-indices = <R8A7794_CLK_MSIOF0>; |
0dce5454 UH |
1061 | clock-output-names = "msiof0"; |
1062 | }; | |
1063 | mstp1_clks: mstp1_clks@e6150134 { | |
1064 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1065 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
dc3cf93d YH |
1066 | clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, |
1067 | <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, | |
1068 | <&zs_clk>, <&zs_clk>; | |
0dce5454 | 1069 | #clock-cells = <1>; |
1045d065 | 1070 | clock-indices = < |
dc3cf93d YH |
1071 | R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 |
1072 | R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 | |
1073 | R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 | |
1074 | R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S | |
0dce5454 UH |
1075 | >; |
1076 | clock-output-names = | |
dc3cf93d YH |
1077 | "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", |
1078 | "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; | |
0dce5454 UH |
1079 | }; |
1080 | mstp2_clks: mstp2_clks@e6150138 { | |
1081 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1082 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
1083 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
be16cd38 HY |
1084 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
1085 | <&zs_clk>, <&zs_clk>; | |
0dce5454 | 1086 | #clock-cells = <1>; |
1045d065 | 1087 | clock-indices = < |
0dce5454 UH |
1088 | R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 |
1089 | R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 | |
1090 | R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 | |
be16cd38 | 1091 | R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 |
0dce5454 UH |
1092 | >; |
1093 | clock-output-names = | |
1094 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", | |
be16cd38 HY |
1095 | "scifb1", "msiof1", "scifb2", |
1096 | "sys-dmac1", "sys-dmac0"; | |
0dce5454 UH |
1097 | }; |
1098 | mstp3_clks: mstp3_clks@e615013c { | |
1099 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1100 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
5e7e1554 | 1101 | clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, |
a856b195 SH |
1102 | <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>, |
1103 | <&hp_clk>, <&hp_clk>; | |
0dce5454 | 1104 | #clock-cells = <1>; |
1045d065 | 1105 | clock-indices = < |
8e181633 | 1106 | R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 |
a856b195 SH |
1107 | R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0 |
1108 | R8A7794_CLK_IIC1 R8A7794_CLK_CMT1 | |
deac150c | 1109 | R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 |
0dce5454 UH |
1110 | >; |
1111 | clock-output-names = | |
8e181633 | 1112 | "sdhi2", "sdhi1", "sdhi0", |
a856b195 SH |
1113 | "mmcif0", "i2c6", "i2c7", |
1114 | "cmt1", "usbdmac0", "usbdmac1"; | |
0dce5454 | 1115 | }; |
1c5ca5db GU |
1116 | mstp4_clks: mstp4_clks@e6150140 { |
1117 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1118 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; | |
1119 | clocks = <&cp_clk>; | |
1120 | #clock-cells = <1>; | |
1121 | clock-indices = <R8A7794_CLK_IRQC>; | |
1122 | clock-output-names = "irqc"; | |
1123 | }; | |
0dce5454 UH |
1124 | mstp7_clks: mstp7_clks@e615014c { |
1125 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1126 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
c7bab9f9 SU |
1127 | clocks = <&mp_clk>, <&mp_clk>, |
1128 | <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, | |
9859cd3b LP |
1129 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
1130 | <&zx_clk>; | |
0dce5454 | 1131 | #clock-cells = <1>; |
1045d065 | 1132 | clock-indices = < |
c7bab9f9 | 1133 | R8A7794_CLK_EHCI R8A7794_CLK_HSUSB |
0dce5454 UH |
1134 | R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 |
1135 | R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 | |
1136 | R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 | |
9859cd3b | 1137 | R8A7794_CLK_SCIF0 R8A7794_CLK_DU0 |
0dce5454 UH |
1138 | >; |
1139 | clock-output-names = | |
c7bab9f9 | 1140 | "ehci", "hsusb", |
0dce5454 | 1141 | "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
9859cd3b | 1142 | "scif3", "scif2", "scif1", "scif0", "du0"; |
0dce5454 UH |
1143 | }; |
1144 | mstp8_clks: mstp8_clks@e6150990 { | |
1145 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1146 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
255a4042 | 1147 | clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>; |
0dce5454 | 1148 | #clock-cells = <1>; |
1045d065 | 1149 | clock-indices = < |
255a4042 SS |
1150 | R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 |
1151 | R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER | |
0dce5454 UH |
1152 | >; |
1153 | clock-output-names = | |
255a4042 | 1154 | "vin1", "vin0", "etheravb", "ether"; |
0dce5454 | 1155 | }; |
3281480b HN |
1156 | mstp9_clks: mstp9_clks@e6150994 { |
1157 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1158 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
3f37e018 | 1159 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
e980f941 SH |
1160 | <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, |
1161 | <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>, | |
1162 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, | |
1163 | <&hp_clk>, <&hp_clk>; | |
3281480b | 1164 | #clock-cells = <1>; |
3f37e018 SS |
1165 | clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5 |
1166 | R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3 | |
1167 | R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1 | |
e980f941 SH |
1168 | R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1 |
1169 | R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD | |
3f37e018 SS |
1170 | R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 |
1171 | R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 | |
1172 | R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>; | |
c5d82c99 | 1173 | clock-output-names = |
3f37e018 | 1174 | "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", |
e980f941 | 1175 | "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", |
3f37e018 | 1176 | "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; |
3281480b | 1177 | }; |
0dce5454 UH |
1178 | mstp11_clks: mstp11_clks@e615099c { |
1179 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1180 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | |
1181 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; | |
1182 | #clock-cells = <1>; | |
1045d065 | 1183 | clock-indices = < |
0dce5454 UH |
1184 | R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 |
1185 | >; | |
1186 | clock-output-names = "scifa3", "scifa4", "scifa5"; | |
1187 | }; | |
1188 | }; | |
1cb2794f LP |
1189 | |
1190 | ipmmu_sy0: mmu@e6280000 { | |
0da4cfd1 | 1191 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
1cb2794f | 1192 | reg = <0 0xe6280000 0 0x1000>; |
8d47e6af SH |
1193 | interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, |
1194 | <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; | |
1cb2794f LP |
1195 | #iommu-cells = <1>; |
1196 | status = "disabled"; | |
1197 | }; | |
1198 | ||
1199 | ipmmu_sy1: mmu@e6290000 { | |
0da4cfd1 | 1200 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
1cb2794f | 1201 | reg = <0 0xe6290000 0 0x1000>; |
8d47e6af | 1202 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
1cb2794f LP |
1203 | #iommu-cells = <1>; |
1204 | status = "disabled"; | |
1205 | }; | |
1206 | ||
1207 | ipmmu_ds: mmu@e6740000 { | |
0da4cfd1 | 1208 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
1cb2794f | 1209 | reg = <0 0xe6740000 0 0x1000>; |
8d47e6af SH |
1210 | interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
1211 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; | |
1cb2794f | 1212 | #iommu-cells = <1>; |
832d3e4c | 1213 | status = "disabled"; |
1cb2794f LP |
1214 | }; |
1215 | ||
1216 | ipmmu_mp: mmu@ec680000 { | |
0da4cfd1 | 1217 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
1cb2794f | 1218 | reg = <0 0xec680000 0 0x1000>; |
8d47e6af | 1219 | interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
1cb2794f LP |
1220 | #iommu-cells = <1>; |
1221 | status = "disabled"; | |
1222 | }; | |
1223 | ||
1224 | ipmmu_mx: mmu@fe951000 { | |
0da4cfd1 | 1225 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
1cb2794f | 1226 | reg = <0 0xfe951000 0 0x1000>; |
8d47e6af SH |
1227 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, |
1228 | <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; | |
1cb2794f | 1229 | #iommu-cells = <1>; |
832d3e4c | 1230 | status = "disabled"; |
1cb2794f LP |
1231 | }; |
1232 | ||
1233 | ipmmu_gp: mmu@e62a0000 { | |
0da4cfd1 | 1234 | compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; |
1cb2794f | 1235 | reg = <0 0xe62a0000 0 0x1000>; |
8d47e6af SH |
1236 | interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, |
1237 | <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; | |
1cb2794f LP |
1238 | #iommu-cells = <1>; |
1239 | status = "disabled"; | |
1240 | }; | |
0dce5454 | 1241 | }; |