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0dce5454 UH |
1 | /* |
2 | * Device Tree Source for the r8a7794 SoC | |
3 | * | |
4 | * Copyright (C) 2014 Renesas Electronics Corporation | |
5 | * Copyright (C) 2014 Ulrich Hecht | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <dt-bindings/clock/r8a7794-clock.h> | |
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
14 | #include <dt-bindings/interrupt-controller/irq.h> | |
15 | ||
16 | / { | |
17 | compatible = "renesas,r8a7794"; | |
18 | interrupt-parent = <&gic>; | |
19 | #address-cells = <2>; | |
20 | #size-cells = <2>; | |
21 | ||
740b4a9f | 22 | aliases { |
5428521b SS |
23 | i2c0 = &i2c0; |
24 | i2c1 = &i2c1; | |
25 | i2c2 = &i2c2; | |
26 | i2c3 = &i2c3; | |
27 | i2c4 = &i2c4; | |
28 | i2c5 = &i2c5; | |
740b4a9f | 29 | spi0 = &qspi; |
1afe77ca SS |
30 | vin0 = &vin0; |
31 | vin1 = &vin1; | |
740b4a9f SS |
32 | }; |
33 | ||
0dce5454 UH |
34 | cpus { |
35 | #address-cells = <1>; | |
36 | #size-cells = <0>; | |
37 | ||
38 | cpu0: cpu@0 { | |
39 | device_type = "cpu"; | |
40 | compatible = "arm,cortex-a7"; | |
41 | reg = <0>; | |
42 | clock-frequency = <1000000000>; | |
43 | }; | |
44 | ||
45 | cpu1: cpu@1 { | |
46 | device_type = "cpu"; | |
47 | compatible = "arm,cortex-a7"; | |
48 | reg = <1>; | |
49 | clock-frequency = <1000000000>; | |
50 | }; | |
51 | }; | |
52 | ||
53 | gic: interrupt-controller@f1001000 { | |
c73ddf42 | 54 | compatible = "arm,gic-400"; |
0dce5454 UH |
55 | #interrupt-cells = <3>; |
56 | #address-cells = <0>; | |
57 | interrupt-controller; | |
58 | reg = <0 0xf1001000 0 0x1000>, | |
59 | <0 0xf1002000 0 0x1000>, | |
60 | <0 0xf1004000 0 0x2000>, | |
61 | <0 0xf1006000 0 0x2000>; | |
00add867 | 62 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
0dce5454 UH |
63 | }; |
64 | ||
e8f5de3b SS |
65 | gpio0: gpio@e6050000 { |
66 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
67 | reg = <0 0xe6050000 0 0x50>; | |
68 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; | |
69 | #gpio-cells = <2>; | |
70 | gpio-controller; | |
71 | gpio-ranges = <&pfc 0 0 32>; | |
72 | #interrupt-cells = <2>; | |
73 | interrupt-controller; | |
74 | clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; | |
75 | power-domains = <&cpg_clocks>; | |
76 | }; | |
77 | ||
78 | gpio1: gpio@e6051000 { | |
79 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
80 | reg = <0 0xe6051000 0 0x50>; | |
81 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; | |
82 | #gpio-cells = <2>; | |
83 | gpio-controller; | |
84 | gpio-ranges = <&pfc 0 32 26>; | |
85 | #interrupt-cells = <2>; | |
86 | interrupt-controller; | |
87 | clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; | |
88 | power-domains = <&cpg_clocks>; | |
89 | }; | |
90 | ||
91 | gpio2: gpio@e6052000 { | |
92 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
93 | reg = <0 0xe6052000 0 0x50>; | |
94 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; | |
95 | #gpio-cells = <2>; | |
96 | gpio-controller; | |
97 | gpio-ranges = <&pfc 0 64 32>; | |
98 | #interrupt-cells = <2>; | |
99 | interrupt-controller; | |
100 | clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; | |
101 | power-domains = <&cpg_clocks>; | |
102 | }; | |
103 | ||
104 | gpio3: gpio@e6053000 { | |
105 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
106 | reg = <0 0xe6053000 0 0x50>; | |
107 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; | |
108 | #gpio-cells = <2>; | |
109 | gpio-controller; | |
110 | gpio-ranges = <&pfc 0 96 32>; | |
111 | #interrupt-cells = <2>; | |
112 | interrupt-controller; | |
113 | clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; | |
114 | power-domains = <&cpg_clocks>; | |
115 | }; | |
116 | ||
117 | gpio4: gpio@e6054000 { | |
118 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
119 | reg = <0 0xe6054000 0 0x50>; | |
120 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; | |
121 | #gpio-cells = <2>; | |
122 | gpio-controller; | |
123 | gpio-ranges = <&pfc 0 128 32>; | |
124 | #interrupt-cells = <2>; | |
125 | interrupt-controller; | |
126 | clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; | |
127 | power-domains = <&cpg_clocks>; | |
128 | }; | |
129 | ||
130 | gpio5: gpio@e6055000 { | |
131 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
132 | reg = <0 0xe6055000 0 0x50>; | |
133 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; | |
134 | #gpio-cells = <2>; | |
135 | gpio-controller; | |
136 | gpio-ranges = <&pfc 0 160 28>; | |
137 | #interrupt-cells = <2>; | |
138 | interrupt-controller; | |
139 | clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; | |
140 | power-domains = <&cpg_clocks>; | |
141 | }; | |
142 | ||
143 | gpio6: gpio@e6055400 { | |
144 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
145 | reg = <0 0xe6055400 0 0x50>; | |
146 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; | |
147 | #gpio-cells = <2>; | |
148 | gpio-controller; | |
149 | gpio-ranges = <&pfc 0 192 26>; | |
150 | #interrupt-cells = <2>; | |
151 | interrupt-controller; | |
152 | clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; | |
153 | power-domains = <&cpg_clocks>; | |
154 | }; | |
155 | ||
0dce5454 UH |
156 | cmt0: timer@ffca0000 { |
157 | compatible = "renesas,cmt-48-gen2"; | |
158 | reg = <0 0xffca0000 0 0x1004>; | |
159 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, | |
160 | <0 143 IRQ_TYPE_LEVEL_HIGH>; | |
161 | clocks = <&mstp1_clks R8A7794_CLK_CMT0>; | |
162 | clock-names = "fck"; | |
60c0745a | 163 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
164 | |
165 | renesas,channels-mask = <0x60>; | |
166 | ||
167 | status = "disabled"; | |
168 | }; | |
169 | ||
170 | cmt1: timer@e6130000 { | |
171 | compatible = "renesas,cmt-48-gen2"; | |
172 | reg = <0 0xe6130000 0 0x1004>; | |
173 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, | |
174 | <0 121 IRQ_TYPE_LEVEL_HIGH>, | |
175 | <0 122 IRQ_TYPE_LEVEL_HIGH>, | |
176 | <0 123 IRQ_TYPE_LEVEL_HIGH>, | |
177 | <0 124 IRQ_TYPE_LEVEL_HIGH>, | |
178 | <0 125 IRQ_TYPE_LEVEL_HIGH>, | |
179 | <0 126 IRQ_TYPE_LEVEL_HIGH>, | |
180 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
181 | clocks = <&mstp3_clks R8A7794_CLK_CMT1>; | |
182 | clock-names = "fck"; | |
60c0745a | 183 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
184 | |
185 | renesas,channels-mask = <0xff>; | |
186 | ||
187 | status = "disabled"; | |
188 | }; | |
189 | ||
da33648c HN |
190 | timer { |
191 | compatible = "arm,armv7-timer"; | |
00add867 GU |
192 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
193 | <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
194 | <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
195 | <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
da33648c HN |
196 | }; |
197 | ||
0dce5454 UH |
198 | irqc0: interrupt-controller@e61c0000 { |
199 | compatible = "renesas,irqc-r8a7794", "renesas,irqc"; | |
200 | #interrupt-cells = <2>; | |
201 | interrupt-controller; | |
202 | reg = <0 0xe61c0000 0 0x200>; | |
203 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, | |
204 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
205 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
206 | <0 3 IRQ_TYPE_LEVEL_HIGH>, | |
207 | <0 12 IRQ_TYPE_LEVEL_HIGH>, | |
208 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
209 | <0 14 IRQ_TYPE_LEVEL_HIGH>, | |
210 | <0 15 IRQ_TYPE_LEVEL_HIGH>, | |
211 | <0 16 IRQ_TYPE_LEVEL_HIGH>, | |
212 | <0 17 IRQ_TYPE_LEVEL_HIGH>; | |
1c5ca5db | 213 | clocks = <&mstp4_clks R8A7794_CLK_IRQC>; |
60c0745a | 214 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
215 | }; |
216 | ||
fd1683c1 SS |
217 | pfc: pin-controller@e6060000 { |
218 | compatible = "renesas,pfc-r8a7794"; | |
219 | reg = <0 0xe6060000 0 0x11c>; | |
fd1683c1 SS |
220 | }; |
221 | ||
bd847485 | 222 | dmac0: dma-controller@e6700000 { |
0a3d058b | 223 | compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; |
bd847485 LP |
224 | reg = <0 0xe6700000 0 0x20000>; |
225 | interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH | |
226 | 0 200 IRQ_TYPE_LEVEL_HIGH | |
227 | 0 201 IRQ_TYPE_LEVEL_HIGH | |
228 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
229 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
230 | 0 204 IRQ_TYPE_LEVEL_HIGH | |
231 | 0 205 IRQ_TYPE_LEVEL_HIGH | |
232 | 0 206 IRQ_TYPE_LEVEL_HIGH | |
233 | 0 207 IRQ_TYPE_LEVEL_HIGH | |
234 | 0 208 IRQ_TYPE_LEVEL_HIGH | |
235 | 0 209 IRQ_TYPE_LEVEL_HIGH | |
236 | 0 210 IRQ_TYPE_LEVEL_HIGH | |
237 | 0 211 IRQ_TYPE_LEVEL_HIGH | |
238 | 0 212 IRQ_TYPE_LEVEL_HIGH | |
239 | 0 213 IRQ_TYPE_LEVEL_HIGH | |
240 | 0 214 IRQ_TYPE_LEVEL_HIGH>; | |
241 | interrupt-names = "error", | |
242 | "ch0", "ch1", "ch2", "ch3", | |
243 | "ch4", "ch5", "ch6", "ch7", | |
244 | "ch8", "ch9", "ch10", "ch11", | |
245 | "ch12", "ch13", "ch14"; | |
246 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; | |
247 | clock-names = "fck"; | |
60c0745a | 248 | power-domains = <&cpg_clocks>; |
bd847485 LP |
249 | #dma-cells = <1>; |
250 | dma-channels = <15>; | |
251 | }; | |
252 | ||
253 | dmac1: dma-controller@e6720000 { | |
0a3d058b | 254 | compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; |
bd847485 LP |
255 | reg = <0 0xe6720000 0 0x20000>; |
256 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | |
257 | 0 216 IRQ_TYPE_LEVEL_HIGH | |
258 | 0 217 IRQ_TYPE_LEVEL_HIGH | |
259 | 0 218 IRQ_TYPE_LEVEL_HIGH | |
260 | 0 219 IRQ_TYPE_LEVEL_HIGH | |
261 | 0 308 IRQ_TYPE_LEVEL_HIGH | |
262 | 0 309 IRQ_TYPE_LEVEL_HIGH | |
263 | 0 310 IRQ_TYPE_LEVEL_HIGH | |
264 | 0 311 IRQ_TYPE_LEVEL_HIGH | |
265 | 0 312 IRQ_TYPE_LEVEL_HIGH | |
266 | 0 313 IRQ_TYPE_LEVEL_HIGH | |
267 | 0 314 IRQ_TYPE_LEVEL_HIGH | |
268 | 0 315 IRQ_TYPE_LEVEL_HIGH | |
269 | 0 316 IRQ_TYPE_LEVEL_HIGH | |
270 | 0 317 IRQ_TYPE_LEVEL_HIGH | |
271 | 0 318 IRQ_TYPE_LEVEL_HIGH>; | |
272 | interrupt-names = "error", | |
273 | "ch0", "ch1", "ch2", "ch3", | |
274 | "ch4", "ch5", "ch6", "ch7", | |
275 | "ch8", "ch9", "ch10", "ch11", | |
276 | "ch12", "ch13", "ch14"; | |
277 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; | |
278 | clock-names = "fck"; | |
60c0745a | 279 | power-domains = <&cpg_clocks>; |
bd847485 LP |
280 | #dma-cells = <1>; |
281 | dma-channels = <15>; | |
282 | }; | |
283 | ||
0dce5454 UH |
284 | scifa0: serial@e6c40000 { |
285 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
286 | reg = <0 0xe6c40000 0 64>; | |
287 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; | |
288 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; | |
289 | clock-names = "sci_ick"; | |
8233a0de GU |
290 | dmas = <&dmac0 0x21>, <&dmac0 0x22>; |
291 | dma-names = "tx", "rx"; | |
60c0745a | 292 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
293 | status = "disabled"; |
294 | }; | |
295 | ||
296 | scifa1: serial@e6c50000 { | |
297 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
298 | reg = <0 0xe6c50000 0 64>; | |
299 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | |
300 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; | |
301 | clock-names = "sci_ick"; | |
8233a0de GU |
302 | dmas = <&dmac0 0x25>, <&dmac0 0x26>; |
303 | dma-names = "tx", "rx"; | |
60c0745a | 304 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
305 | status = "disabled"; |
306 | }; | |
307 | ||
308 | scifa2: serial@e6c60000 { | |
309 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
310 | reg = <0 0xe6c60000 0 64>; | |
311 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; | |
312 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; | |
313 | clock-names = "sci_ick"; | |
8233a0de GU |
314 | dmas = <&dmac0 0x27>, <&dmac0 0x28>; |
315 | dma-names = "tx", "rx"; | |
60c0745a | 316 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
317 | status = "disabled"; |
318 | }; | |
319 | ||
320 | scifa3: serial@e6c70000 { | |
321 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
322 | reg = <0 0xe6c70000 0 64>; | |
323 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; | |
324 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; | |
325 | clock-names = "sci_ick"; | |
8233a0de GU |
326 | dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; |
327 | dma-names = "tx", "rx"; | |
60c0745a | 328 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
329 | status = "disabled"; |
330 | }; | |
331 | ||
332 | scifa4: serial@e6c78000 { | |
333 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
334 | reg = <0 0xe6c78000 0 64>; | |
335 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; | |
336 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; | |
337 | clock-names = "sci_ick"; | |
8233a0de GU |
338 | dmas = <&dmac0 0x1f>, <&dmac0 0x20>; |
339 | dma-names = "tx", "rx"; | |
60c0745a | 340 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
341 | status = "disabled"; |
342 | }; | |
343 | ||
344 | scifa5: serial@e6c80000 { | |
345 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
346 | reg = <0 0xe6c80000 0 64>; | |
347 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; | |
348 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; | |
349 | clock-names = "sci_ick"; | |
8233a0de GU |
350 | dmas = <&dmac0 0x23>, <&dmac0 0x24>; |
351 | dma-names = "tx", "rx"; | |
60c0745a | 352 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
353 | status = "disabled"; |
354 | }; | |
355 | ||
356 | scifb0: serial@e6c20000 { | |
357 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; | |
358 | reg = <0 0xe6c20000 0 64>; | |
359 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; | |
360 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; | |
361 | clock-names = "sci_ick"; | |
8233a0de GU |
362 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; |
363 | dma-names = "tx", "rx"; | |
60c0745a | 364 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
365 | status = "disabled"; |
366 | }; | |
367 | ||
368 | scifb1: serial@e6c30000 { | |
369 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; | |
370 | reg = <0 0xe6c30000 0 64>; | |
371 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; | |
372 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; | |
373 | clock-names = "sci_ick"; | |
8233a0de GU |
374 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>; |
375 | dma-names = "tx", "rx"; | |
60c0745a | 376 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
377 | status = "disabled"; |
378 | }; | |
379 | ||
380 | scifb2: serial@e6ce0000 { | |
381 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; | |
382 | reg = <0 0xe6ce0000 0 64>; | |
383 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; | |
384 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; | |
385 | clock-names = "sci_ick"; | |
8233a0de GU |
386 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; |
387 | dma-names = "tx", "rx"; | |
60c0745a | 388 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
389 | status = "disabled"; |
390 | }; | |
391 | ||
392 | scif0: serial@e6e60000 { | |
393 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
394 | reg = <0 0xe6e60000 0 64>; | |
395 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; | |
396 | clocks = <&mstp7_clks R8A7794_CLK_SCIF0>; | |
397 | clock-names = "sci_ick"; | |
8233a0de GU |
398 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>; |
399 | dma-names = "tx", "rx"; | |
60c0745a | 400 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
401 | status = "disabled"; |
402 | }; | |
403 | ||
404 | scif1: serial@e6e68000 { | |
405 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
406 | reg = <0 0xe6e68000 0 64>; | |
407 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; | |
408 | clocks = <&mstp7_clks R8A7794_CLK_SCIF1>; | |
409 | clock-names = "sci_ick"; | |
8233a0de GU |
410 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; |
411 | dma-names = "tx", "rx"; | |
60c0745a | 412 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
413 | status = "disabled"; |
414 | }; | |
415 | ||
416 | scif2: serial@e6e58000 { | |
417 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
418 | reg = <0 0xe6e58000 0 64>; | |
419 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; | |
420 | clocks = <&mstp7_clks R8A7794_CLK_SCIF2>; | |
421 | clock-names = "sci_ick"; | |
8233a0de GU |
422 | dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; |
423 | dma-names = "tx", "rx"; | |
60c0745a | 424 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
425 | status = "disabled"; |
426 | }; | |
427 | ||
428 | scif3: serial@e6ea8000 { | |
429 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
430 | reg = <0 0xe6ea8000 0 64>; | |
431 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; | |
432 | clocks = <&mstp7_clks R8A7794_CLK_SCIF3>; | |
433 | clock-names = "sci_ick"; | |
8233a0de GU |
434 | dmas = <&dmac0 0x2f>, <&dmac0 0x30>; |
435 | dma-names = "tx", "rx"; | |
60c0745a | 436 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
437 | status = "disabled"; |
438 | }; | |
439 | ||
440 | scif4: serial@e6ee0000 { | |
441 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
442 | reg = <0 0xe6ee0000 0 64>; | |
443 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; | |
444 | clocks = <&mstp7_clks R8A7794_CLK_SCIF4>; | |
445 | clock-names = "sci_ick"; | |
8233a0de GU |
446 | dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; |
447 | dma-names = "tx", "rx"; | |
60c0745a | 448 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
449 | status = "disabled"; |
450 | }; | |
451 | ||
452 | scif5: serial@e6ee8000 { | |
453 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
454 | reg = <0 0xe6ee8000 0 64>; | |
455 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; | |
456 | clocks = <&mstp7_clks R8A7794_CLK_SCIF5>; | |
457 | clock-names = "sci_ick"; | |
8233a0de GU |
458 | dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; |
459 | dma-names = "tx", "rx"; | |
60c0745a | 460 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
461 | status = "disabled"; |
462 | }; | |
463 | ||
464 | hscif0: serial@e62c0000 { | |
465 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; | |
466 | reg = <0 0xe62c0000 0 96>; | |
467 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; | |
468 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>; | |
469 | clock-names = "sci_ick"; | |
8233a0de GU |
470 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>; |
471 | dma-names = "tx", "rx"; | |
60c0745a | 472 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
473 | status = "disabled"; |
474 | }; | |
475 | ||
476 | hscif1: serial@e62c8000 { | |
477 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; | |
478 | reg = <0 0xe62c8000 0 96>; | |
479 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; | |
480 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>; | |
481 | clock-names = "sci_ick"; | |
8233a0de GU |
482 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; |
483 | dma-names = "tx", "rx"; | |
60c0745a | 484 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
485 | status = "disabled"; |
486 | }; | |
487 | ||
488 | hscif2: serial@e62d0000 { | |
489 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; | |
490 | reg = <0 0xe62d0000 0 96>; | |
491 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; | |
492 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>; | |
493 | clock-names = "sci_ick"; | |
8233a0de GU |
494 | dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; |
495 | dma-names = "tx", "rx"; | |
60c0745a | 496 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
497 | status = "disabled"; |
498 | }; | |
499 | ||
82818d34 LP |
500 | ether: ethernet@ee700000 { |
501 | compatible = "renesas,ether-r8a7794"; | |
502 | reg = <0 0xee700000 0 0x400>; | |
503 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
504 | clocks = <&mstp8_clks R8A7794_CLK_ETHER>; | |
60c0745a | 505 | power-domains = <&cpg_clocks>; |
82818d34 LP |
506 | phy-mode = "rmii"; |
507 | #address-cells = <1>; | |
508 | #size-cells = <0>; | |
509 | status = "disabled"; | |
510 | }; | |
511 | ||
5428521b SS |
512 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
513 | i2c0: i2c@e6508000 { | |
514 | compatible = "renesas,i2c-r8a7794"; | |
515 | reg = <0 0xe6508000 0 0x40>; | |
516 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; | |
517 | clocks = <&mstp9_clks R8A7794_CLK_I2C0>; | |
518 | power-domains = <&cpg_clocks>; | |
519 | #address-cells = <1>; | |
520 | #size-cells = <0>; | |
691cd0a6 | 521 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
522 | status = "disabled"; |
523 | }; | |
524 | ||
525 | i2c1: i2c@e6518000 { | |
526 | compatible = "renesas,i2c-r8a7794"; | |
527 | reg = <0 0xe6518000 0 0x40>; | |
528 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; | |
529 | clocks = <&mstp9_clks R8A7794_CLK_I2C1>; | |
530 | power-domains = <&cpg_clocks>; | |
531 | #address-cells = <1>; | |
532 | #size-cells = <0>; | |
691cd0a6 | 533 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
534 | status = "disabled"; |
535 | }; | |
536 | ||
537 | i2c2: i2c@e6530000 { | |
538 | compatible = "renesas,i2c-r8a7794"; | |
539 | reg = <0 0xe6530000 0 0x40>; | |
540 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; | |
541 | clocks = <&mstp9_clks R8A7794_CLK_I2C2>; | |
542 | power-domains = <&cpg_clocks>; | |
543 | #address-cells = <1>; | |
544 | #size-cells = <0>; | |
691cd0a6 | 545 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
546 | status = "disabled"; |
547 | }; | |
548 | ||
549 | i2c3: i2c@e6540000 { | |
550 | compatible = "renesas,i2c-r8a7794"; | |
551 | reg = <0 0xe6540000 0 0x40>; | |
552 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; | |
553 | clocks = <&mstp9_clks R8A7794_CLK_I2C3>; | |
554 | power-domains = <&cpg_clocks>; | |
555 | #address-cells = <1>; | |
556 | #size-cells = <0>; | |
691cd0a6 | 557 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
558 | status = "disabled"; |
559 | }; | |
560 | ||
561 | i2c4: i2c@e6520000 { | |
562 | compatible = "renesas,i2c-r8a7794"; | |
563 | reg = <0 0xe6520000 0 0x40>; | |
564 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; | |
565 | clocks = <&mstp9_clks R8A7794_CLK_I2C4>; | |
566 | power-domains = <&cpg_clocks>; | |
567 | #address-cells = <1>; | |
568 | #size-cells = <0>; | |
691cd0a6 | 569 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
570 | status = "disabled"; |
571 | }; | |
572 | ||
573 | i2c5: i2c@e6528000 { | |
574 | compatible = "renesas,i2c-r8a7794"; | |
575 | reg = <0 0xe6528000 0 0x40>; | |
576 | interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
577 | clocks = <&mstp9_clks R8A7794_CLK_I2C5>; | |
578 | power-domains = <&cpg_clocks>; | |
579 | #address-cells = <1>; | |
580 | #size-cells = <0>; | |
691cd0a6 | 581 | i2c-scl-internal-delay-ns = <6>; |
5428521b SS |
582 | status = "disabled"; |
583 | }; | |
584 | ||
6cdf6ba1 SS |
585 | mmcif0: mmc@ee200000 { |
586 | compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; | |
587 | reg = <0 0xee200000 0 0x80>; | |
588 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; | |
589 | clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; | |
590 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; | |
591 | dma-names = "tx", "rx"; | |
60c0745a | 592 | power-domains = <&cpg_clocks>; |
6cdf6ba1 SS |
593 | reg-io-width = <4>; |
594 | status = "disabled"; | |
595 | }; | |
596 | ||
b8e8ea12 SS |
597 | sdhi0: sd@ee100000 { |
598 | compatible = "renesas,sdhi-r8a7794"; | |
599 | reg = <0 0xee100000 0 0x200>; | |
600 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; | |
601 | clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; | |
60c0745a | 602 | power-domains = <&cpg_clocks>; |
b8e8ea12 SS |
603 | status = "disabled"; |
604 | }; | |
605 | ||
606 | sdhi1: sd@ee140000 { | |
607 | compatible = "renesas,sdhi-r8a7794"; | |
608 | reg = <0 0xee140000 0 0x100>; | |
609 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; | |
610 | clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; | |
60c0745a | 611 | power-domains = <&cpg_clocks>; |
b8e8ea12 SS |
612 | status = "disabled"; |
613 | }; | |
614 | ||
615 | sdhi2: sd@ee160000 { | |
616 | compatible = "renesas,sdhi-r8a7794"; | |
617 | reg = <0 0xee160000 0 0x100>; | |
618 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; | |
619 | clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; | |
60c0745a | 620 | power-domains = <&cpg_clocks>; |
b8e8ea12 SS |
621 | status = "disabled"; |
622 | }; | |
623 | ||
740b4a9f SS |
624 | qspi: spi@e6b10000 { |
625 | compatible = "renesas,qspi-r8a7794", "renesas,qspi"; | |
626 | reg = <0 0xe6b10000 0 0x2c>; | |
627 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; | |
628 | clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; | |
629 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; | |
630 | dma-names = "tx", "rx"; | |
631 | power-domains = <&cpg_clocks>; | |
632 | num-cs = <1>; | |
633 | #address-cells = <1>; | |
634 | #size-cells = <0>; | |
635 | status = "disabled"; | |
636 | }; | |
637 | ||
1afe77ca SS |
638 | vin0: video@e6ef0000 { |
639 | compatible = "renesas,vin-r8a7794"; | |
640 | reg = <0 0xe6ef0000 0 0x1000>; | |
641 | interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; | |
642 | clocks = <&mstp8_clks R8A7794_CLK_VIN0>; | |
643 | power-domains = <&cpg_clocks>; | |
644 | status = "disabled"; | |
645 | }; | |
646 | ||
647 | vin1: video@e6ef1000 { | |
648 | compatible = "renesas,vin-r8a7794"; | |
649 | reg = <0 0xe6ef1000 0 0x1000>; | |
650 | interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; | |
651 | clocks = <&mstp8_clks R8A7794_CLK_VIN1>; | |
652 | power-domains = <&cpg_clocks>; | |
653 | status = "disabled"; | |
654 | }; | |
655 | ||
a6a130b3 SS |
656 | pci0: pci@ee090000 { |
657 | compatible = "renesas,pci-r8a7794"; | |
658 | device_type = "pci"; | |
659 | reg = <0 0xee090000 0 0xc00>, | |
660 | <0 0xee080000 0 0x1100>; | |
661 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
662 | clocks = <&mstp7_clks R8A7794_CLK_EHCI>; | |
663 | power-domains = <&cpg_clocks>; | |
664 | status = "disabled"; | |
665 | ||
666 | bus-range = <0 0>; | |
667 | #address-cells = <3>; | |
668 | #size-cells = <2>; | |
669 | #interrupt-cells = <1>; | |
670 | ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; | |
671 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
672 | interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
673 | 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
674 | 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; | |
45cb0bd7 SS |
675 | |
676 | usb@0,1 { | |
677 | reg = <0x800 0 0 0 0>; | |
678 | device_type = "pci"; | |
679 | phys = <&usb0 0>; | |
680 | phy-names = "usb"; | |
681 | }; | |
682 | ||
683 | usb@0,2 { | |
684 | reg = <0x1000 0 0 0 0>; | |
685 | device_type = "pci"; | |
686 | phys = <&usb0 0>; | |
687 | phy-names = "usb"; | |
688 | }; | |
a6a130b3 SS |
689 | }; |
690 | ||
691 | pci1: pci@ee0d0000 { | |
692 | compatible = "renesas,pci-r8a7794"; | |
693 | device_type = "pci"; | |
694 | reg = <0 0xee0d0000 0 0xc00>, | |
695 | <0 0xee0c0000 0 0x1100>; | |
696 | interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; | |
697 | clocks = <&mstp7_clks R8A7794_CLK_EHCI>; | |
698 | power-domains = <&cpg_clocks>; | |
699 | status = "disabled"; | |
700 | ||
701 | bus-range = <1 1>; | |
702 | #address-cells = <3>; | |
703 | #size-cells = <2>; | |
704 | #interrupt-cells = <1>; | |
705 | ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; | |
706 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
707 | interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH | |
708 | 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH | |
709 | 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; | |
45cb0bd7 SS |
710 | |
711 | usb@0,1 { | |
712 | reg = <0x800 0 0 0 0>; | |
713 | device_type = "pci"; | |
714 | phys = <&usb2 0>; | |
715 | phy-names = "usb"; | |
716 | }; | |
717 | ||
718 | usb@0,2 { | |
719 | reg = <0x1000 0 0 0 0>; | |
720 | device_type = "pci"; | |
721 | phys = <&usb2 0>; | |
722 | phy-names = "usb"; | |
723 | }; | |
a6a130b3 SS |
724 | }; |
725 | ||
2f33b9f7 SS |
726 | hsusb: usb@e6590000 { |
727 | compatible = "renesas,usbhs-r8a7794"; | |
728 | reg = <0 0xe6590000 0 0x100>; | |
729 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | |
730 | clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; | |
731 | power-domains = <&cpg_clocks>; | |
732 | renesas,buswait = <4>; | |
733 | phys = <&usb0 1>; | |
734 | phy-names = "usb"; | |
735 | status = "disabled"; | |
736 | }; | |
737 | ||
74ef4572 SS |
738 | usbphy: usb-phy@e6590100 { |
739 | compatible = "renesas,usb-phy-r8a7794"; | |
740 | reg = <0 0xe6590100 0 0x100>; | |
741 | #address-cells = <1>; | |
742 | #size-cells = <0>; | |
743 | clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; | |
744 | clock-names = "usbhs"; | |
745 | power-domains = <&cpg_clocks>; | |
746 | status = "disabled"; | |
747 | ||
748 | usb0: usb-channel@0 { | |
749 | reg = <0>; | |
750 | #phy-cells = <1>; | |
751 | }; | |
752 | usb2: usb-channel@2 { | |
753 | reg = <2>; | |
754 | #phy-cells = <1>; | |
755 | }; | |
756 | }; | |
757 | ||
46c4f13d LP |
758 | du: display@feb00000 { |
759 | compatible = "renesas,du-r8a7794"; | |
760 | reg = <0 0xfeb00000 0 0x40000>; | |
761 | reg-names = "du"; | |
762 | interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, | |
763 | <0 268 IRQ_TYPE_LEVEL_HIGH>; | |
764 | clocks = <&mstp7_clks R8A7794_CLK_DU0>, | |
765 | <&mstp7_clks R8A7794_CLK_DU0>; | |
766 | clock-names = "du.0", "du.1"; | |
767 | status = "disabled"; | |
768 | ||
769 | ports { | |
770 | #address-cells = <1>; | |
771 | #size-cells = <0>; | |
772 | ||
773 | port@0 { | |
774 | reg = <0>; | |
775 | du_out_rgb0: endpoint { | |
776 | }; | |
777 | }; | |
778 | port@1 { | |
779 | reg = <1>; | |
780 | du_out_rgb1: endpoint { | |
781 | }; | |
782 | }; | |
783 | }; | |
784 | }; | |
785 | ||
0dce5454 UH |
786 | clocks { |
787 | #address-cells = <2>; | |
788 | #size-cells = <2>; | |
789 | ranges; | |
790 | ||
791 | /* External root clock */ | |
792 | extal_clk: extal_clk { | |
793 | compatible = "fixed-clock"; | |
794 | #clock-cells = <0>; | |
795 | /* This value must be overriden by the board. */ | |
796 | clock-frequency = <0>; | |
797 | clock-output-names = "extal"; | |
798 | }; | |
799 | ||
800 | /* Special CPG clocks */ | |
801 | cpg_clocks: cpg_clocks@e6150000 { | |
802 | compatible = "renesas,r8a7794-cpg-clocks", | |
803 | "renesas,rcar-gen2-cpg-clocks"; | |
804 | reg = <0 0xe6150000 0 0x1000>; | |
805 | clocks = <&extal_clk>; | |
806 | #clock-cells = <1>; | |
807 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
808 | "lb", "qspi", "sdh", "sd0", "z"; | |
60c0745a | 809 | #power-domain-cells = <0>; |
0dce5454 | 810 | }; |
8e181633 | 811 | /* Variable factor clocks */ |
5e7e1554 | 812 | sd2_clk: sd2_clk@e6150078 { |
8e181633 SU |
813 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
814 | reg = <0 0xe6150078 0 4>; | |
815 | clocks = <&pll1_div2_clk>; | |
816 | #clock-cells = <0>; | |
5e7e1554 | 817 | clock-output-names = "sd2"; |
8e181633 | 818 | }; |
5e7e1554 | 819 | sd3_clk: sd3_clk@e615026c { |
8e181633 | 820 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
5e7e1554 | 821 | reg = <0 0xe615026c 0 4>; |
8e181633 SU |
822 | clocks = <&pll1_div2_clk>; |
823 | #clock-cells = <0>; | |
5e7e1554 | 824 | clock-output-names = "sd3"; |
8e181633 | 825 | }; |
deac150c SU |
826 | mmc0_clk: mmc0_clk@e6150240 { |
827 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; | |
828 | reg = <0 0xe6150240 0 4>; | |
829 | clocks = <&pll1_div2_clk>; | |
830 | #clock-cells = <0>; | |
831 | clock-output-names = "mmc0"; | |
832 | }; | |
0dce5454 UH |
833 | |
834 | /* Fixed factor clocks */ | |
835 | pll1_div2_clk: pll1_div2_clk { | |
836 | compatible = "fixed-factor-clock"; | |
837 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
838 | #clock-cells = <0>; | |
839 | clock-div = <2>; | |
840 | clock-mult = <1>; | |
841 | clock-output-names = "pll1_div2"; | |
842 | }; | |
843 | zg_clk: zg_clk { | |
844 | compatible = "fixed-factor-clock"; | |
845 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
846 | #clock-cells = <0>; | |
847 | clock-div = <6>; | |
848 | clock-mult = <1>; | |
849 | clock-output-names = "zg"; | |
850 | }; | |
851 | zx_clk: zx_clk { | |
852 | compatible = "fixed-factor-clock"; | |
853 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
854 | #clock-cells = <0>; | |
855 | clock-div = <3>; | |
856 | clock-mult = <1>; | |
857 | clock-output-names = "zx"; | |
858 | }; | |
859 | zs_clk: zs_clk { | |
860 | compatible = "fixed-factor-clock"; | |
861 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
862 | #clock-cells = <0>; | |
863 | clock-div = <6>; | |
864 | clock-mult = <1>; | |
865 | clock-output-names = "zs"; | |
866 | }; | |
867 | hp_clk: hp_clk { | |
868 | compatible = "fixed-factor-clock"; | |
869 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
870 | #clock-cells = <0>; | |
871 | clock-div = <12>; | |
872 | clock-mult = <1>; | |
873 | clock-output-names = "hp"; | |
874 | }; | |
875 | i_clk: i_clk { | |
876 | compatible = "fixed-factor-clock"; | |
877 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
878 | #clock-cells = <0>; | |
879 | clock-div = <2>; | |
880 | clock-mult = <1>; | |
881 | clock-output-names = "i"; | |
882 | }; | |
883 | b_clk: b_clk { | |
884 | compatible = "fixed-factor-clock"; | |
885 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
886 | #clock-cells = <0>; | |
887 | clock-div = <12>; | |
888 | clock-mult = <1>; | |
889 | clock-output-names = "b"; | |
890 | }; | |
891 | p_clk: p_clk { | |
892 | compatible = "fixed-factor-clock"; | |
893 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
894 | #clock-cells = <0>; | |
895 | clock-div = <24>; | |
896 | clock-mult = <1>; | |
897 | clock-output-names = "p"; | |
898 | }; | |
899 | cl_clk: cl_clk { | |
900 | compatible = "fixed-factor-clock"; | |
901 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
902 | #clock-cells = <0>; | |
903 | clock-div = <48>; | |
904 | clock-mult = <1>; | |
905 | clock-output-names = "cl"; | |
906 | }; | |
907 | m2_clk: m2_clk { | |
908 | compatible = "fixed-factor-clock"; | |
909 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
910 | #clock-cells = <0>; | |
911 | clock-div = <8>; | |
912 | clock-mult = <1>; | |
913 | clock-output-names = "m2"; | |
914 | }; | |
0dce5454 UH |
915 | rclk_clk: rclk_clk { |
916 | compatible = "fixed-factor-clock"; | |
917 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
918 | #clock-cells = <0>; | |
919 | clock-div = <(48 * 1024)>; | |
920 | clock-mult = <1>; | |
921 | clock-output-names = "rclk"; | |
922 | }; | |
923 | oscclk_clk: oscclk_clk { | |
924 | compatible = "fixed-factor-clock"; | |
925 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
926 | #clock-cells = <0>; | |
927 | clock-div = <(12 * 1024)>; | |
928 | clock-mult = <1>; | |
929 | clock-output-names = "oscclk"; | |
930 | }; | |
931 | zb3_clk: zb3_clk { | |
932 | compatible = "fixed-factor-clock"; | |
933 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
934 | #clock-cells = <0>; | |
935 | clock-div = <4>; | |
936 | clock-mult = <1>; | |
937 | clock-output-names = "zb3"; | |
938 | }; | |
939 | zb3d2_clk: zb3d2_clk { | |
940 | compatible = "fixed-factor-clock"; | |
941 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
942 | #clock-cells = <0>; | |
943 | clock-div = <8>; | |
944 | clock-mult = <1>; | |
945 | clock-output-names = "zb3d2"; | |
946 | }; | |
947 | ddr_clk: ddr_clk { | |
948 | compatible = "fixed-factor-clock"; | |
949 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
950 | #clock-cells = <0>; | |
951 | clock-div = <8>; | |
952 | clock-mult = <1>; | |
953 | clock-output-names = "ddr"; | |
954 | }; | |
955 | mp_clk: mp_clk { | |
956 | compatible = "fixed-factor-clock"; | |
957 | clocks = <&pll1_div2_clk>; | |
958 | #clock-cells = <0>; | |
959 | clock-div = <15>; | |
960 | clock-mult = <1>; | |
961 | clock-output-names = "mp"; | |
962 | }; | |
963 | cp_clk: cp_clk { | |
964 | compatible = "fixed-factor-clock"; | |
965 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
966 | #clock-cells = <0>; | |
967 | clock-div = <48>; | |
968 | clock-mult = <1>; | |
969 | clock-output-names = "cp"; | |
970 | }; | |
971 | ||
972 | acp_clk: acp_clk { | |
973 | compatible = "fixed-factor-clock"; | |
974 | clocks = <&extal_clk>; | |
975 | #clock-cells = <0>; | |
976 | clock-div = <2>; | |
977 | clock-mult = <1>; | |
978 | clock-output-names = "acp"; | |
979 | }; | |
980 | ||
981 | /* Gate clocks */ | |
982 | mstp0_clks: mstp0_clks@e6150130 { | |
983 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
984 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
985 | clocks = <&mp_clk>; | |
986 | #clock-cells = <1>; | |
1045d065 | 987 | clock-indices = <R8A7794_CLK_MSIOF0>; |
0dce5454 UH |
988 | clock-output-names = "msiof0"; |
989 | }; | |
990 | mstp1_clks: mstp1_clks@e6150134 { | |
991 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
992 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
dc3cf93d YH |
993 | clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, |
994 | <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, | |
995 | <&zs_clk>, <&zs_clk>; | |
0dce5454 | 996 | #clock-cells = <1>; |
1045d065 | 997 | clock-indices = < |
dc3cf93d YH |
998 | R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 |
999 | R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 | |
1000 | R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 | |
1001 | R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S | |
0dce5454 UH |
1002 | >; |
1003 | clock-output-names = | |
dc3cf93d YH |
1004 | "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", |
1005 | "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; | |
0dce5454 UH |
1006 | }; |
1007 | mstp2_clks: mstp2_clks@e6150138 { | |
1008 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1009 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
1010 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
be16cd38 HY |
1011 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
1012 | <&zs_clk>, <&zs_clk>; | |
0dce5454 | 1013 | #clock-cells = <1>; |
1045d065 | 1014 | clock-indices = < |
0dce5454 UH |
1015 | R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 |
1016 | R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 | |
1017 | R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 | |
be16cd38 | 1018 | R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 |
0dce5454 UH |
1019 | >; |
1020 | clock-output-names = | |
1021 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", | |
be16cd38 HY |
1022 | "scifb1", "msiof1", "scifb2", |
1023 | "sys-dmac1", "sys-dmac0"; | |
0dce5454 UH |
1024 | }; |
1025 | mstp3_clks: mstp3_clks@e615013c { | |
1026 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1027 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
5e7e1554 | 1028 | clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, |
deac150c | 1029 | <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; |
0dce5454 | 1030 | #clock-cells = <1>; |
1045d065 | 1031 | clock-indices = < |
8e181633 | 1032 | R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 |
deac150c SU |
1033 | R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1 |
1034 | R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 | |
0dce5454 UH |
1035 | >; |
1036 | clock-output-names = | |
8e181633 | 1037 | "sdhi2", "sdhi1", "sdhi0", |
deac150c | 1038 | "mmcif0", "cmt1", "usbdmac0", "usbdmac1"; |
0dce5454 | 1039 | }; |
1c5ca5db GU |
1040 | mstp4_clks: mstp4_clks@e6150140 { |
1041 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1042 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; | |
1043 | clocks = <&cp_clk>; | |
1044 | #clock-cells = <1>; | |
1045 | clock-indices = <R8A7794_CLK_IRQC>; | |
1046 | clock-output-names = "irqc"; | |
1047 | }; | |
0dce5454 UH |
1048 | mstp7_clks: mstp7_clks@e615014c { |
1049 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1050 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
c7bab9f9 SU |
1051 | clocks = <&mp_clk>, <&mp_clk>, |
1052 | <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, | |
9859cd3b LP |
1053 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
1054 | <&zx_clk>; | |
0dce5454 | 1055 | #clock-cells = <1>; |
1045d065 | 1056 | clock-indices = < |
c7bab9f9 | 1057 | R8A7794_CLK_EHCI R8A7794_CLK_HSUSB |
0dce5454 UH |
1058 | R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 |
1059 | R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 | |
1060 | R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 | |
9859cd3b | 1061 | R8A7794_CLK_SCIF0 R8A7794_CLK_DU0 |
0dce5454 UH |
1062 | >; |
1063 | clock-output-names = | |
c7bab9f9 | 1064 | "ehci", "hsusb", |
0dce5454 | 1065 | "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
9859cd3b | 1066 | "scif3", "scif2", "scif1", "scif0", "du0"; |
0dce5454 UH |
1067 | }; |
1068 | mstp8_clks: mstp8_clks@e6150990 { | |
1069 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1070 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
148ebf47 | 1071 | clocks = <&zg_clk>, <&zg_clk>, <&p_clk>; |
0dce5454 | 1072 | #clock-cells = <1>; |
1045d065 | 1073 | clock-indices = < |
148ebf47 | 1074 | R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER |
0dce5454 UH |
1075 | >; |
1076 | clock-output-names = | |
148ebf47 | 1077 | "vin1", "vin0", "ether"; |
0dce5454 | 1078 | }; |
3281480b HN |
1079 | mstp9_clks: mstp9_clks@e6150994 { |
1080 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1081 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
3f37e018 SS |
1082 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
1083 | <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
1084 | <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>, | |
1085 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; | |
3281480b | 1086 | #clock-cells = <1>; |
3f37e018 SS |
1087 | clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5 |
1088 | R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3 | |
1089 | R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1 | |
1090 | R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD | |
1091 | R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 | |
1092 | R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 | |
1093 | R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>; | |
c5d82c99 | 1094 | clock-output-names = |
3f37e018 SS |
1095 | "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", |
1096 | "gpio1", "gpio0", "qspi_mod", | |
1097 | "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; | |
3281480b | 1098 | }; |
0dce5454 UH |
1099 | mstp11_clks: mstp11_clks@e615099c { |
1100 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1101 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | |
1102 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; | |
1103 | #clock-cells = <1>; | |
1045d065 | 1104 | clock-indices = < |
0dce5454 UH |
1105 | R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 |
1106 | >; | |
1107 | clock-output-names = "scifa3", "scifa4", "scifa5"; | |
1108 | }; | |
1109 | }; | |
1cb2794f LP |
1110 | |
1111 | ipmmu_sy0: mmu@e6280000 { | |
1112 | compatible = "renesas,ipmmu-vmsa"; | |
1113 | reg = <0 0xe6280000 0 0x1000>; | |
1114 | interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, | |
1115 | <0 224 IRQ_TYPE_LEVEL_HIGH>; | |
1116 | #iommu-cells = <1>; | |
1117 | status = "disabled"; | |
1118 | }; | |
1119 | ||
1120 | ipmmu_sy1: mmu@e6290000 { | |
1121 | compatible = "renesas,ipmmu-vmsa"; | |
1122 | reg = <0 0xe6290000 0 0x1000>; | |
1123 | interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; | |
1124 | #iommu-cells = <1>; | |
1125 | status = "disabled"; | |
1126 | }; | |
1127 | ||
1128 | ipmmu_ds: mmu@e6740000 { | |
1129 | compatible = "renesas,ipmmu-vmsa"; | |
1130 | reg = <0 0xe6740000 0 0x1000>; | |
1131 | interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, | |
1132 | <0 199 IRQ_TYPE_LEVEL_HIGH>; | |
1133 | #iommu-cells = <1>; | |
832d3e4c | 1134 | status = "disabled"; |
1cb2794f LP |
1135 | }; |
1136 | ||
1137 | ipmmu_mp: mmu@ec680000 { | |
1138 | compatible = "renesas,ipmmu-vmsa"; | |
1139 | reg = <0 0xec680000 0 0x1000>; | |
1140 | interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; | |
1141 | #iommu-cells = <1>; | |
1142 | status = "disabled"; | |
1143 | }; | |
1144 | ||
1145 | ipmmu_mx: mmu@fe951000 { | |
1146 | compatible = "renesas,ipmmu-vmsa"; | |
1147 | reg = <0 0xfe951000 0 0x1000>; | |
1148 | interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, | |
1149 | <0 221 IRQ_TYPE_LEVEL_HIGH>; | |
1150 | #iommu-cells = <1>; | |
832d3e4c | 1151 | status = "disabled"; |
1cb2794f LP |
1152 | }; |
1153 | ||
1154 | ipmmu_gp: mmu@e62a0000 { | |
1155 | compatible = "renesas,ipmmu-vmsa"; | |
1156 | reg = <0 0xe62a0000 0 0x1000>; | |
1157 | interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, | |
1158 | <0 261 IRQ_TYPE_LEVEL_HIGH>; | |
1159 | #iommu-cells = <1>; | |
1160 | status = "disabled"; | |
1161 | }; | |
0dce5454 | 1162 | }; |