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Commit | Line | Data |
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0dce5454 UH |
1 | /* |
2 | * Device Tree Source for the r8a7794 SoC | |
3 | * | |
4 | * Copyright (C) 2014 Renesas Electronics Corporation | |
5 | * Copyright (C) 2014 Ulrich Hecht | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <dt-bindings/clock/r8a7794-clock.h> | |
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
14 | #include <dt-bindings/interrupt-controller/irq.h> | |
15 | ||
16 | / { | |
17 | compatible = "renesas,r8a7794"; | |
18 | interrupt-parent = <&gic>; | |
19 | #address-cells = <2>; | |
20 | #size-cells = <2>; | |
21 | ||
740b4a9f | 22 | aliases { |
5428521b SS |
23 | i2c0 = &i2c0; |
24 | i2c1 = &i2c1; | |
25 | i2c2 = &i2c2; | |
26 | i2c3 = &i2c3; | |
27 | i2c4 = &i2c4; | |
28 | i2c5 = &i2c5; | |
740b4a9f SS |
29 | spi0 = &qspi; |
30 | }; | |
31 | ||
0dce5454 UH |
32 | cpus { |
33 | #address-cells = <1>; | |
34 | #size-cells = <0>; | |
35 | ||
36 | cpu0: cpu@0 { | |
37 | device_type = "cpu"; | |
38 | compatible = "arm,cortex-a7"; | |
39 | reg = <0>; | |
40 | clock-frequency = <1000000000>; | |
41 | }; | |
42 | ||
43 | cpu1: cpu@1 { | |
44 | device_type = "cpu"; | |
45 | compatible = "arm,cortex-a7"; | |
46 | reg = <1>; | |
47 | clock-frequency = <1000000000>; | |
48 | }; | |
49 | }; | |
50 | ||
51 | gic: interrupt-controller@f1001000 { | |
c73ddf42 | 52 | compatible = "arm,gic-400"; |
0dce5454 UH |
53 | #interrupt-cells = <3>; |
54 | #address-cells = <0>; | |
55 | interrupt-controller; | |
56 | reg = <0 0xf1001000 0 0x1000>, | |
57 | <0 0xf1002000 0 0x1000>, | |
58 | <0 0xf1004000 0 0x2000>, | |
59 | <0 0xf1006000 0 0x2000>; | |
00add867 | 60 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
0dce5454 UH |
61 | }; |
62 | ||
e8f5de3b SS |
63 | gpio0: gpio@e6050000 { |
64 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
65 | reg = <0 0xe6050000 0 0x50>; | |
66 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; | |
67 | #gpio-cells = <2>; | |
68 | gpio-controller; | |
69 | gpio-ranges = <&pfc 0 0 32>; | |
70 | #interrupt-cells = <2>; | |
71 | interrupt-controller; | |
72 | clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; | |
73 | power-domains = <&cpg_clocks>; | |
74 | }; | |
75 | ||
76 | gpio1: gpio@e6051000 { | |
77 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
78 | reg = <0 0xe6051000 0 0x50>; | |
79 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; | |
80 | #gpio-cells = <2>; | |
81 | gpio-controller; | |
82 | gpio-ranges = <&pfc 0 32 26>; | |
83 | #interrupt-cells = <2>; | |
84 | interrupt-controller; | |
85 | clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; | |
86 | power-domains = <&cpg_clocks>; | |
87 | }; | |
88 | ||
89 | gpio2: gpio@e6052000 { | |
90 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
91 | reg = <0 0xe6052000 0 0x50>; | |
92 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; | |
93 | #gpio-cells = <2>; | |
94 | gpio-controller; | |
95 | gpio-ranges = <&pfc 0 64 32>; | |
96 | #interrupt-cells = <2>; | |
97 | interrupt-controller; | |
98 | clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; | |
99 | power-domains = <&cpg_clocks>; | |
100 | }; | |
101 | ||
102 | gpio3: gpio@e6053000 { | |
103 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
104 | reg = <0 0xe6053000 0 0x50>; | |
105 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; | |
106 | #gpio-cells = <2>; | |
107 | gpio-controller; | |
108 | gpio-ranges = <&pfc 0 96 32>; | |
109 | #interrupt-cells = <2>; | |
110 | interrupt-controller; | |
111 | clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; | |
112 | power-domains = <&cpg_clocks>; | |
113 | }; | |
114 | ||
115 | gpio4: gpio@e6054000 { | |
116 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
117 | reg = <0 0xe6054000 0 0x50>; | |
118 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; | |
119 | #gpio-cells = <2>; | |
120 | gpio-controller; | |
121 | gpio-ranges = <&pfc 0 128 32>; | |
122 | #interrupt-cells = <2>; | |
123 | interrupt-controller; | |
124 | clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; | |
125 | power-domains = <&cpg_clocks>; | |
126 | }; | |
127 | ||
128 | gpio5: gpio@e6055000 { | |
129 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
130 | reg = <0 0xe6055000 0 0x50>; | |
131 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; | |
132 | #gpio-cells = <2>; | |
133 | gpio-controller; | |
134 | gpio-ranges = <&pfc 0 160 28>; | |
135 | #interrupt-cells = <2>; | |
136 | interrupt-controller; | |
137 | clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; | |
138 | power-domains = <&cpg_clocks>; | |
139 | }; | |
140 | ||
141 | gpio6: gpio@e6055400 { | |
142 | compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; | |
143 | reg = <0 0xe6055400 0 0x50>; | |
144 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; | |
145 | #gpio-cells = <2>; | |
146 | gpio-controller; | |
147 | gpio-ranges = <&pfc 0 192 26>; | |
148 | #interrupt-cells = <2>; | |
149 | interrupt-controller; | |
150 | clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; | |
151 | power-domains = <&cpg_clocks>; | |
152 | }; | |
153 | ||
0dce5454 UH |
154 | cmt0: timer@ffca0000 { |
155 | compatible = "renesas,cmt-48-gen2"; | |
156 | reg = <0 0xffca0000 0 0x1004>; | |
157 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, | |
158 | <0 143 IRQ_TYPE_LEVEL_HIGH>; | |
159 | clocks = <&mstp1_clks R8A7794_CLK_CMT0>; | |
160 | clock-names = "fck"; | |
60c0745a | 161 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
162 | |
163 | renesas,channels-mask = <0x60>; | |
164 | ||
165 | status = "disabled"; | |
166 | }; | |
167 | ||
168 | cmt1: timer@e6130000 { | |
169 | compatible = "renesas,cmt-48-gen2"; | |
170 | reg = <0 0xe6130000 0 0x1004>; | |
171 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, | |
172 | <0 121 IRQ_TYPE_LEVEL_HIGH>, | |
173 | <0 122 IRQ_TYPE_LEVEL_HIGH>, | |
174 | <0 123 IRQ_TYPE_LEVEL_HIGH>, | |
175 | <0 124 IRQ_TYPE_LEVEL_HIGH>, | |
176 | <0 125 IRQ_TYPE_LEVEL_HIGH>, | |
177 | <0 126 IRQ_TYPE_LEVEL_HIGH>, | |
178 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
179 | clocks = <&mstp3_clks R8A7794_CLK_CMT1>; | |
180 | clock-names = "fck"; | |
60c0745a | 181 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
182 | |
183 | renesas,channels-mask = <0xff>; | |
184 | ||
185 | status = "disabled"; | |
186 | }; | |
187 | ||
da33648c HN |
188 | timer { |
189 | compatible = "arm,armv7-timer"; | |
00add867 GU |
190 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
191 | <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
192 | <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
193 | <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
da33648c HN |
194 | }; |
195 | ||
0dce5454 UH |
196 | irqc0: interrupt-controller@e61c0000 { |
197 | compatible = "renesas,irqc-r8a7794", "renesas,irqc"; | |
198 | #interrupt-cells = <2>; | |
199 | interrupt-controller; | |
200 | reg = <0 0xe61c0000 0 0x200>; | |
201 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, | |
202 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
203 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
204 | <0 3 IRQ_TYPE_LEVEL_HIGH>, | |
205 | <0 12 IRQ_TYPE_LEVEL_HIGH>, | |
206 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
207 | <0 14 IRQ_TYPE_LEVEL_HIGH>, | |
208 | <0 15 IRQ_TYPE_LEVEL_HIGH>, | |
209 | <0 16 IRQ_TYPE_LEVEL_HIGH>, | |
210 | <0 17 IRQ_TYPE_LEVEL_HIGH>; | |
1c5ca5db | 211 | clocks = <&mstp4_clks R8A7794_CLK_IRQC>; |
60c0745a | 212 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
213 | }; |
214 | ||
fd1683c1 SS |
215 | pfc: pin-controller@e6060000 { |
216 | compatible = "renesas,pfc-r8a7794"; | |
217 | reg = <0 0xe6060000 0 0x11c>; | |
218 | #gpio-range-cells = <3>; | |
219 | }; | |
220 | ||
bd847485 LP |
221 | dmac0: dma-controller@e6700000 { |
222 | compatible = "renesas,rcar-dmac"; | |
223 | reg = <0 0xe6700000 0 0x20000>; | |
224 | interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH | |
225 | 0 200 IRQ_TYPE_LEVEL_HIGH | |
226 | 0 201 IRQ_TYPE_LEVEL_HIGH | |
227 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
228 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
229 | 0 204 IRQ_TYPE_LEVEL_HIGH | |
230 | 0 205 IRQ_TYPE_LEVEL_HIGH | |
231 | 0 206 IRQ_TYPE_LEVEL_HIGH | |
232 | 0 207 IRQ_TYPE_LEVEL_HIGH | |
233 | 0 208 IRQ_TYPE_LEVEL_HIGH | |
234 | 0 209 IRQ_TYPE_LEVEL_HIGH | |
235 | 0 210 IRQ_TYPE_LEVEL_HIGH | |
236 | 0 211 IRQ_TYPE_LEVEL_HIGH | |
237 | 0 212 IRQ_TYPE_LEVEL_HIGH | |
238 | 0 213 IRQ_TYPE_LEVEL_HIGH | |
239 | 0 214 IRQ_TYPE_LEVEL_HIGH>; | |
240 | interrupt-names = "error", | |
241 | "ch0", "ch1", "ch2", "ch3", | |
242 | "ch4", "ch5", "ch6", "ch7", | |
243 | "ch8", "ch9", "ch10", "ch11", | |
244 | "ch12", "ch13", "ch14"; | |
245 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; | |
246 | clock-names = "fck"; | |
60c0745a | 247 | power-domains = <&cpg_clocks>; |
bd847485 LP |
248 | #dma-cells = <1>; |
249 | dma-channels = <15>; | |
250 | }; | |
251 | ||
252 | dmac1: dma-controller@e6720000 { | |
253 | compatible = "renesas,rcar-dmac"; | |
254 | reg = <0 0xe6720000 0 0x20000>; | |
255 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | |
256 | 0 216 IRQ_TYPE_LEVEL_HIGH | |
257 | 0 217 IRQ_TYPE_LEVEL_HIGH | |
258 | 0 218 IRQ_TYPE_LEVEL_HIGH | |
259 | 0 219 IRQ_TYPE_LEVEL_HIGH | |
260 | 0 308 IRQ_TYPE_LEVEL_HIGH | |
261 | 0 309 IRQ_TYPE_LEVEL_HIGH | |
262 | 0 310 IRQ_TYPE_LEVEL_HIGH | |
263 | 0 311 IRQ_TYPE_LEVEL_HIGH | |
264 | 0 312 IRQ_TYPE_LEVEL_HIGH | |
265 | 0 313 IRQ_TYPE_LEVEL_HIGH | |
266 | 0 314 IRQ_TYPE_LEVEL_HIGH | |
267 | 0 315 IRQ_TYPE_LEVEL_HIGH | |
268 | 0 316 IRQ_TYPE_LEVEL_HIGH | |
269 | 0 317 IRQ_TYPE_LEVEL_HIGH | |
270 | 0 318 IRQ_TYPE_LEVEL_HIGH>; | |
271 | interrupt-names = "error", | |
272 | "ch0", "ch1", "ch2", "ch3", | |
273 | "ch4", "ch5", "ch6", "ch7", | |
274 | "ch8", "ch9", "ch10", "ch11", | |
275 | "ch12", "ch13", "ch14"; | |
276 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; | |
277 | clock-names = "fck"; | |
60c0745a | 278 | power-domains = <&cpg_clocks>; |
bd847485 LP |
279 | #dma-cells = <1>; |
280 | dma-channels = <15>; | |
281 | }; | |
282 | ||
0dce5454 UH |
283 | scifa0: serial@e6c40000 { |
284 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
285 | reg = <0 0xe6c40000 0 64>; | |
286 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; | |
287 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; | |
288 | clock-names = "sci_ick"; | |
8233a0de GU |
289 | dmas = <&dmac0 0x21>, <&dmac0 0x22>; |
290 | dma-names = "tx", "rx"; | |
60c0745a | 291 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
292 | status = "disabled"; |
293 | }; | |
294 | ||
295 | scifa1: serial@e6c50000 { | |
296 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
297 | reg = <0 0xe6c50000 0 64>; | |
298 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | |
299 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; | |
300 | clock-names = "sci_ick"; | |
8233a0de GU |
301 | dmas = <&dmac0 0x25>, <&dmac0 0x26>; |
302 | dma-names = "tx", "rx"; | |
60c0745a | 303 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
304 | status = "disabled"; |
305 | }; | |
306 | ||
307 | scifa2: serial@e6c60000 { | |
308 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
309 | reg = <0 0xe6c60000 0 64>; | |
310 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; | |
311 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; | |
312 | clock-names = "sci_ick"; | |
8233a0de GU |
313 | dmas = <&dmac0 0x27>, <&dmac0 0x28>; |
314 | dma-names = "tx", "rx"; | |
60c0745a | 315 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
316 | status = "disabled"; |
317 | }; | |
318 | ||
319 | scifa3: serial@e6c70000 { | |
320 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
321 | reg = <0 0xe6c70000 0 64>; | |
322 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; | |
323 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; | |
324 | clock-names = "sci_ick"; | |
8233a0de GU |
325 | dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; |
326 | dma-names = "tx", "rx"; | |
60c0745a | 327 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
328 | status = "disabled"; |
329 | }; | |
330 | ||
331 | scifa4: serial@e6c78000 { | |
332 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
333 | reg = <0 0xe6c78000 0 64>; | |
334 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; | |
335 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; | |
336 | clock-names = "sci_ick"; | |
8233a0de GU |
337 | dmas = <&dmac0 0x1f>, <&dmac0 0x20>; |
338 | dma-names = "tx", "rx"; | |
60c0745a | 339 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
340 | status = "disabled"; |
341 | }; | |
342 | ||
343 | scifa5: serial@e6c80000 { | |
344 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
345 | reg = <0 0xe6c80000 0 64>; | |
346 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; | |
347 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; | |
348 | clock-names = "sci_ick"; | |
8233a0de GU |
349 | dmas = <&dmac0 0x23>, <&dmac0 0x24>; |
350 | dma-names = "tx", "rx"; | |
60c0745a | 351 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
352 | status = "disabled"; |
353 | }; | |
354 | ||
355 | scifb0: serial@e6c20000 { | |
356 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; | |
357 | reg = <0 0xe6c20000 0 64>; | |
358 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; | |
359 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; | |
360 | clock-names = "sci_ick"; | |
8233a0de GU |
361 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; |
362 | dma-names = "tx", "rx"; | |
60c0745a | 363 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
364 | status = "disabled"; |
365 | }; | |
366 | ||
367 | scifb1: serial@e6c30000 { | |
368 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; | |
369 | reg = <0 0xe6c30000 0 64>; | |
370 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; | |
371 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; | |
372 | clock-names = "sci_ick"; | |
8233a0de GU |
373 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>; |
374 | dma-names = "tx", "rx"; | |
60c0745a | 375 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
376 | status = "disabled"; |
377 | }; | |
378 | ||
379 | scifb2: serial@e6ce0000 { | |
380 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; | |
381 | reg = <0 0xe6ce0000 0 64>; | |
382 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; | |
383 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; | |
384 | clock-names = "sci_ick"; | |
8233a0de GU |
385 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; |
386 | dma-names = "tx", "rx"; | |
60c0745a | 387 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
388 | status = "disabled"; |
389 | }; | |
390 | ||
391 | scif0: serial@e6e60000 { | |
392 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
393 | reg = <0 0xe6e60000 0 64>; | |
394 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; | |
395 | clocks = <&mstp7_clks R8A7794_CLK_SCIF0>; | |
396 | clock-names = "sci_ick"; | |
8233a0de GU |
397 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>; |
398 | dma-names = "tx", "rx"; | |
60c0745a | 399 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
400 | status = "disabled"; |
401 | }; | |
402 | ||
403 | scif1: serial@e6e68000 { | |
404 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
405 | reg = <0 0xe6e68000 0 64>; | |
406 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; | |
407 | clocks = <&mstp7_clks R8A7794_CLK_SCIF1>; | |
408 | clock-names = "sci_ick"; | |
8233a0de GU |
409 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; |
410 | dma-names = "tx", "rx"; | |
60c0745a | 411 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
412 | status = "disabled"; |
413 | }; | |
414 | ||
415 | scif2: serial@e6e58000 { | |
416 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
417 | reg = <0 0xe6e58000 0 64>; | |
418 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; | |
419 | clocks = <&mstp7_clks R8A7794_CLK_SCIF2>; | |
420 | clock-names = "sci_ick"; | |
8233a0de GU |
421 | dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; |
422 | dma-names = "tx", "rx"; | |
60c0745a | 423 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
424 | status = "disabled"; |
425 | }; | |
426 | ||
427 | scif3: serial@e6ea8000 { | |
428 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
429 | reg = <0 0xe6ea8000 0 64>; | |
430 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; | |
431 | clocks = <&mstp7_clks R8A7794_CLK_SCIF3>; | |
432 | clock-names = "sci_ick"; | |
8233a0de GU |
433 | dmas = <&dmac0 0x2f>, <&dmac0 0x30>; |
434 | dma-names = "tx", "rx"; | |
60c0745a | 435 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
436 | status = "disabled"; |
437 | }; | |
438 | ||
439 | scif4: serial@e6ee0000 { | |
440 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
441 | reg = <0 0xe6ee0000 0 64>; | |
442 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; | |
443 | clocks = <&mstp7_clks R8A7794_CLK_SCIF4>; | |
444 | clock-names = "sci_ick"; | |
8233a0de GU |
445 | dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; |
446 | dma-names = "tx", "rx"; | |
60c0745a | 447 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
448 | status = "disabled"; |
449 | }; | |
450 | ||
451 | scif5: serial@e6ee8000 { | |
452 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
453 | reg = <0 0xe6ee8000 0 64>; | |
454 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; | |
455 | clocks = <&mstp7_clks R8A7794_CLK_SCIF5>; | |
456 | clock-names = "sci_ick"; | |
8233a0de GU |
457 | dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; |
458 | dma-names = "tx", "rx"; | |
60c0745a | 459 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
460 | status = "disabled"; |
461 | }; | |
462 | ||
463 | hscif0: serial@e62c0000 { | |
464 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; | |
465 | reg = <0 0xe62c0000 0 96>; | |
466 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; | |
467 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>; | |
468 | clock-names = "sci_ick"; | |
8233a0de GU |
469 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>; |
470 | dma-names = "tx", "rx"; | |
60c0745a | 471 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
472 | status = "disabled"; |
473 | }; | |
474 | ||
475 | hscif1: serial@e62c8000 { | |
476 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; | |
477 | reg = <0 0xe62c8000 0 96>; | |
478 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; | |
479 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>; | |
480 | clock-names = "sci_ick"; | |
8233a0de GU |
481 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; |
482 | dma-names = "tx", "rx"; | |
60c0745a | 483 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
484 | status = "disabled"; |
485 | }; | |
486 | ||
487 | hscif2: serial@e62d0000 { | |
488 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; | |
489 | reg = <0 0xe62d0000 0 96>; | |
490 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; | |
491 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>; | |
492 | clock-names = "sci_ick"; | |
8233a0de GU |
493 | dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; |
494 | dma-names = "tx", "rx"; | |
60c0745a | 495 | power-domains = <&cpg_clocks>; |
0dce5454 UH |
496 | status = "disabled"; |
497 | }; | |
498 | ||
82818d34 LP |
499 | ether: ethernet@ee700000 { |
500 | compatible = "renesas,ether-r8a7794"; | |
501 | reg = <0 0xee700000 0 0x400>; | |
502 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
503 | clocks = <&mstp8_clks R8A7794_CLK_ETHER>; | |
60c0745a | 504 | power-domains = <&cpg_clocks>; |
82818d34 LP |
505 | phy-mode = "rmii"; |
506 | #address-cells = <1>; | |
507 | #size-cells = <0>; | |
508 | status = "disabled"; | |
509 | }; | |
510 | ||
5428521b SS |
511 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
512 | i2c0: i2c@e6508000 { | |
513 | compatible = "renesas,i2c-r8a7794"; | |
514 | reg = <0 0xe6508000 0 0x40>; | |
515 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; | |
516 | clocks = <&mstp9_clks R8A7794_CLK_I2C0>; | |
517 | power-domains = <&cpg_clocks>; | |
518 | #address-cells = <1>; | |
519 | #size-cells = <0>; | |
520 | status = "disabled"; | |
521 | }; | |
522 | ||
523 | i2c1: i2c@e6518000 { | |
524 | compatible = "renesas,i2c-r8a7794"; | |
525 | reg = <0 0xe6518000 0 0x40>; | |
526 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; | |
527 | clocks = <&mstp9_clks R8A7794_CLK_I2C1>; | |
528 | power-domains = <&cpg_clocks>; | |
529 | #address-cells = <1>; | |
530 | #size-cells = <0>; | |
531 | status = "disabled"; | |
532 | }; | |
533 | ||
534 | i2c2: i2c@e6530000 { | |
535 | compatible = "renesas,i2c-r8a7794"; | |
536 | reg = <0 0xe6530000 0 0x40>; | |
537 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; | |
538 | clocks = <&mstp9_clks R8A7794_CLK_I2C2>; | |
539 | power-domains = <&cpg_clocks>; | |
540 | #address-cells = <1>; | |
541 | #size-cells = <0>; | |
542 | status = "disabled"; | |
543 | }; | |
544 | ||
545 | i2c3: i2c@e6540000 { | |
546 | compatible = "renesas,i2c-r8a7794"; | |
547 | reg = <0 0xe6540000 0 0x40>; | |
548 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; | |
549 | clocks = <&mstp9_clks R8A7794_CLK_I2C3>; | |
550 | power-domains = <&cpg_clocks>; | |
551 | #address-cells = <1>; | |
552 | #size-cells = <0>; | |
553 | status = "disabled"; | |
554 | }; | |
555 | ||
556 | i2c4: i2c@e6520000 { | |
557 | compatible = "renesas,i2c-r8a7794"; | |
558 | reg = <0 0xe6520000 0 0x40>; | |
559 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; | |
560 | clocks = <&mstp9_clks R8A7794_CLK_I2C4>; | |
561 | power-domains = <&cpg_clocks>; | |
562 | #address-cells = <1>; | |
563 | #size-cells = <0>; | |
564 | status = "disabled"; | |
565 | }; | |
566 | ||
567 | i2c5: i2c@e6528000 { | |
568 | compatible = "renesas,i2c-r8a7794"; | |
569 | reg = <0 0xe6528000 0 0x40>; | |
570 | interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
571 | clocks = <&mstp9_clks R8A7794_CLK_I2C5>; | |
572 | power-domains = <&cpg_clocks>; | |
573 | #address-cells = <1>; | |
574 | #size-cells = <0>; | |
575 | status = "disabled"; | |
576 | }; | |
577 | ||
6cdf6ba1 SS |
578 | mmcif0: mmc@ee200000 { |
579 | compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; | |
580 | reg = <0 0xee200000 0 0x80>; | |
581 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; | |
582 | clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; | |
583 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; | |
584 | dma-names = "tx", "rx"; | |
60c0745a | 585 | power-domains = <&cpg_clocks>; |
6cdf6ba1 SS |
586 | reg-io-width = <4>; |
587 | status = "disabled"; | |
588 | }; | |
589 | ||
b8e8ea12 SS |
590 | sdhi0: sd@ee100000 { |
591 | compatible = "renesas,sdhi-r8a7794"; | |
592 | reg = <0 0xee100000 0 0x200>; | |
593 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; | |
594 | clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; | |
60c0745a | 595 | power-domains = <&cpg_clocks>; |
b8e8ea12 SS |
596 | status = "disabled"; |
597 | }; | |
598 | ||
599 | sdhi1: sd@ee140000 { | |
600 | compatible = "renesas,sdhi-r8a7794"; | |
601 | reg = <0 0xee140000 0 0x100>; | |
602 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; | |
603 | clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; | |
60c0745a | 604 | power-domains = <&cpg_clocks>; |
b8e8ea12 SS |
605 | status = "disabled"; |
606 | }; | |
607 | ||
608 | sdhi2: sd@ee160000 { | |
609 | compatible = "renesas,sdhi-r8a7794"; | |
610 | reg = <0 0xee160000 0 0x100>; | |
611 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; | |
612 | clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; | |
60c0745a | 613 | power-domains = <&cpg_clocks>; |
b8e8ea12 SS |
614 | status = "disabled"; |
615 | }; | |
616 | ||
740b4a9f SS |
617 | qspi: spi@e6b10000 { |
618 | compatible = "renesas,qspi-r8a7794", "renesas,qspi"; | |
619 | reg = <0 0xe6b10000 0 0x2c>; | |
620 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; | |
621 | clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; | |
622 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; | |
623 | dma-names = "tx", "rx"; | |
624 | power-domains = <&cpg_clocks>; | |
625 | num-cs = <1>; | |
626 | #address-cells = <1>; | |
627 | #size-cells = <0>; | |
628 | status = "disabled"; | |
629 | }; | |
630 | ||
0dce5454 UH |
631 | clocks { |
632 | #address-cells = <2>; | |
633 | #size-cells = <2>; | |
634 | ranges; | |
635 | ||
636 | /* External root clock */ | |
637 | extal_clk: extal_clk { | |
638 | compatible = "fixed-clock"; | |
639 | #clock-cells = <0>; | |
640 | /* This value must be overriden by the board. */ | |
641 | clock-frequency = <0>; | |
642 | clock-output-names = "extal"; | |
643 | }; | |
644 | ||
645 | /* Special CPG clocks */ | |
646 | cpg_clocks: cpg_clocks@e6150000 { | |
647 | compatible = "renesas,r8a7794-cpg-clocks", | |
648 | "renesas,rcar-gen2-cpg-clocks"; | |
649 | reg = <0 0xe6150000 0 0x1000>; | |
650 | clocks = <&extal_clk>; | |
651 | #clock-cells = <1>; | |
652 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
653 | "lb", "qspi", "sdh", "sd0", "z"; | |
60c0745a | 654 | #power-domain-cells = <0>; |
0dce5454 | 655 | }; |
8e181633 | 656 | /* Variable factor clocks */ |
5e7e1554 | 657 | sd2_clk: sd2_clk@e6150078 { |
8e181633 SU |
658 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
659 | reg = <0 0xe6150078 0 4>; | |
660 | clocks = <&pll1_div2_clk>; | |
661 | #clock-cells = <0>; | |
5e7e1554 | 662 | clock-output-names = "sd2"; |
8e181633 | 663 | }; |
5e7e1554 | 664 | sd3_clk: sd3_clk@e615026c { |
8e181633 | 665 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
5e7e1554 | 666 | reg = <0 0xe615026c 0 4>; |
8e181633 SU |
667 | clocks = <&pll1_div2_clk>; |
668 | #clock-cells = <0>; | |
5e7e1554 | 669 | clock-output-names = "sd3"; |
8e181633 | 670 | }; |
deac150c SU |
671 | mmc0_clk: mmc0_clk@e6150240 { |
672 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; | |
673 | reg = <0 0xe6150240 0 4>; | |
674 | clocks = <&pll1_div2_clk>; | |
675 | #clock-cells = <0>; | |
676 | clock-output-names = "mmc0"; | |
677 | }; | |
0dce5454 UH |
678 | |
679 | /* Fixed factor clocks */ | |
680 | pll1_div2_clk: pll1_div2_clk { | |
681 | compatible = "fixed-factor-clock"; | |
682 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
683 | #clock-cells = <0>; | |
684 | clock-div = <2>; | |
685 | clock-mult = <1>; | |
686 | clock-output-names = "pll1_div2"; | |
687 | }; | |
688 | zg_clk: zg_clk { | |
689 | compatible = "fixed-factor-clock"; | |
690 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
691 | #clock-cells = <0>; | |
692 | clock-div = <6>; | |
693 | clock-mult = <1>; | |
694 | clock-output-names = "zg"; | |
695 | }; | |
696 | zx_clk: zx_clk { | |
697 | compatible = "fixed-factor-clock"; | |
698 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
699 | #clock-cells = <0>; | |
700 | clock-div = <3>; | |
701 | clock-mult = <1>; | |
702 | clock-output-names = "zx"; | |
703 | }; | |
704 | zs_clk: zs_clk { | |
705 | compatible = "fixed-factor-clock"; | |
706 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
707 | #clock-cells = <0>; | |
708 | clock-div = <6>; | |
709 | clock-mult = <1>; | |
710 | clock-output-names = "zs"; | |
711 | }; | |
712 | hp_clk: hp_clk { | |
713 | compatible = "fixed-factor-clock"; | |
714 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
715 | #clock-cells = <0>; | |
716 | clock-div = <12>; | |
717 | clock-mult = <1>; | |
718 | clock-output-names = "hp"; | |
719 | }; | |
720 | i_clk: i_clk { | |
721 | compatible = "fixed-factor-clock"; | |
722 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
723 | #clock-cells = <0>; | |
724 | clock-div = <2>; | |
725 | clock-mult = <1>; | |
726 | clock-output-names = "i"; | |
727 | }; | |
728 | b_clk: b_clk { | |
729 | compatible = "fixed-factor-clock"; | |
730 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
731 | #clock-cells = <0>; | |
732 | clock-div = <12>; | |
733 | clock-mult = <1>; | |
734 | clock-output-names = "b"; | |
735 | }; | |
736 | p_clk: p_clk { | |
737 | compatible = "fixed-factor-clock"; | |
738 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
739 | #clock-cells = <0>; | |
740 | clock-div = <24>; | |
741 | clock-mult = <1>; | |
742 | clock-output-names = "p"; | |
743 | }; | |
744 | cl_clk: cl_clk { | |
745 | compatible = "fixed-factor-clock"; | |
746 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
747 | #clock-cells = <0>; | |
748 | clock-div = <48>; | |
749 | clock-mult = <1>; | |
750 | clock-output-names = "cl"; | |
751 | }; | |
752 | m2_clk: m2_clk { | |
753 | compatible = "fixed-factor-clock"; | |
754 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
755 | #clock-cells = <0>; | |
756 | clock-div = <8>; | |
757 | clock-mult = <1>; | |
758 | clock-output-names = "m2"; | |
759 | }; | |
760 | imp_clk: imp_clk { | |
761 | compatible = "fixed-factor-clock"; | |
762 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
763 | #clock-cells = <0>; | |
764 | clock-div = <4>; | |
765 | clock-mult = <1>; | |
766 | clock-output-names = "imp"; | |
767 | }; | |
768 | rclk_clk: rclk_clk { | |
769 | compatible = "fixed-factor-clock"; | |
770 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
771 | #clock-cells = <0>; | |
772 | clock-div = <(48 * 1024)>; | |
773 | clock-mult = <1>; | |
774 | clock-output-names = "rclk"; | |
775 | }; | |
776 | oscclk_clk: oscclk_clk { | |
777 | compatible = "fixed-factor-clock"; | |
778 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
779 | #clock-cells = <0>; | |
780 | clock-div = <(12 * 1024)>; | |
781 | clock-mult = <1>; | |
782 | clock-output-names = "oscclk"; | |
783 | }; | |
784 | zb3_clk: zb3_clk { | |
785 | compatible = "fixed-factor-clock"; | |
786 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
787 | #clock-cells = <0>; | |
788 | clock-div = <4>; | |
789 | clock-mult = <1>; | |
790 | clock-output-names = "zb3"; | |
791 | }; | |
792 | zb3d2_clk: zb3d2_clk { | |
793 | compatible = "fixed-factor-clock"; | |
794 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
795 | #clock-cells = <0>; | |
796 | clock-div = <8>; | |
797 | clock-mult = <1>; | |
798 | clock-output-names = "zb3d2"; | |
799 | }; | |
800 | ddr_clk: ddr_clk { | |
801 | compatible = "fixed-factor-clock"; | |
802 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
803 | #clock-cells = <0>; | |
804 | clock-div = <8>; | |
805 | clock-mult = <1>; | |
806 | clock-output-names = "ddr"; | |
807 | }; | |
808 | mp_clk: mp_clk { | |
809 | compatible = "fixed-factor-clock"; | |
810 | clocks = <&pll1_div2_clk>; | |
811 | #clock-cells = <0>; | |
812 | clock-div = <15>; | |
813 | clock-mult = <1>; | |
814 | clock-output-names = "mp"; | |
815 | }; | |
816 | cp_clk: cp_clk { | |
817 | compatible = "fixed-factor-clock"; | |
818 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
819 | #clock-cells = <0>; | |
820 | clock-div = <48>; | |
821 | clock-mult = <1>; | |
822 | clock-output-names = "cp"; | |
823 | }; | |
824 | ||
825 | acp_clk: acp_clk { | |
826 | compatible = "fixed-factor-clock"; | |
827 | clocks = <&extal_clk>; | |
828 | #clock-cells = <0>; | |
829 | clock-div = <2>; | |
830 | clock-mult = <1>; | |
831 | clock-output-names = "acp"; | |
832 | }; | |
833 | ||
834 | /* Gate clocks */ | |
835 | mstp0_clks: mstp0_clks@e6150130 { | |
836 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
837 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
838 | clocks = <&mp_clk>; | |
839 | #clock-cells = <1>; | |
1045d065 | 840 | clock-indices = <R8A7794_CLK_MSIOF0>; |
0dce5454 UH |
841 | clock-output-names = "msiof0"; |
842 | }; | |
843 | mstp1_clks: mstp1_clks@e6150134 { | |
844 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
845 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
dc3cf93d YH |
846 | clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, |
847 | <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, | |
848 | <&zs_clk>, <&zs_clk>; | |
0dce5454 | 849 | #clock-cells = <1>; |
1045d065 | 850 | clock-indices = < |
dc3cf93d YH |
851 | R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 |
852 | R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 | |
853 | R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 | |
854 | R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S | |
0dce5454 UH |
855 | >; |
856 | clock-output-names = | |
dc3cf93d YH |
857 | "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", |
858 | "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; | |
0dce5454 UH |
859 | }; |
860 | mstp2_clks: mstp2_clks@e6150138 { | |
861 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
862 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
863 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
be16cd38 HY |
864 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
865 | <&zs_clk>, <&zs_clk>; | |
0dce5454 | 866 | #clock-cells = <1>; |
1045d065 | 867 | clock-indices = < |
0dce5454 UH |
868 | R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 |
869 | R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 | |
870 | R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 | |
be16cd38 | 871 | R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 |
0dce5454 UH |
872 | >; |
873 | clock-output-names = | |
874 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", | |
be16cd38 HY |
875 | "scifb1", "msiof1", "scifb2", |
876 | "sys-dmac1", "sys-dmac0"; | |
0dce5454 UH |
877 | }; |
878 | mstp3_clks: mstp3_clks@e615013c { | |
879 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
880 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
5e7e1554 | 881 | clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, |
deac150c | 882 | <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; |
0dce5454 | 883 | #clock-cells = <1>; |
1045d065 | 884 | clock-indices = < |
8e181633 | 885 | R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 |
deac150c SU |
886 | R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1 |
887 | R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 | |
0dce5454 UH |
888 | >; |
889 | clock-output-names = | |
8e181633 | 890 | "sdhi2", "sdhi1", "sdhi0", |
deac150c | 891 | "mmcif0", "cmt1", "usbdmac0", "usbdmac1"; |
0dce5454 | 892 | }; |
1c5ca5db GU |
893 | mstp4_clks: mstp4_clks@e6150140 { |
894 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
895 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; | |
896 | clocks = <&cp_clk>; | |
897 | #clock-cells = <1>; | |
898 | clock-indices = <R8A7794_CLK_IRQC>; | |
899 | clock-output-names = "irqc"; | |
900 | }; | |
0dce5454 UH |
901 | mstp7_clks: mstp7_clks@e615014c { |
902 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
903 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
c7bab9f9 SU |
904 | clocks = <&mp_clk>, <&mp_clk>, |
905 | <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, | |
0dce5454 UH |
906 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; |
907 | #clock-cells = <1>; | |
1045d065 | 908 | clock-indices = < |
c7bab9f9 | 909 | R8A7794_CLK_EHCI R8A7794_CLK_HSUSB |
0dce5454 UH |
910 | R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 |
911 | R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 | |
912 | R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 | |
913 | R8A7794_CLK_SCIF0 | |
914 | >; | |
915 | clock-output-names = | |
c7bab9f9 | 916 | "ehci", "hsusb", |
0dce5454 UH |
917 | "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
918 | "scif3", "scif2", "scif1", "scif0"; | |
919 | }; | |
920 | mstp8_clks: mstp8_clks@e6150990 { | |
921 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
922 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
148ebf47 | 923 | clocks = <&zg_clk>, <&zg_clk>, <&p_clk>; |
0dce5454 | 924 | #clock-cells = <1>; |
1045d065 | 925 | clock-indices = < |
148ebf47 | 926 | R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER |
0dce5454 UH |
927 | >; |
928 | clock-output-names = | |
148ebf47 | 929 | "vin1", "vin0", "ether"; |
0dce5454 | 930 | }; |
3281480b HN |
931 | mstp9_clks: mstp9_clks@e6150994 { |
932 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
933 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
3f37e018 SS |
934 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
935 | <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
936 | <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>, | |
937 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; | |
3281480b | 938 | #clock-cells = <1>; |
3f37e018 SS |
939 | clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5 |
940 | R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3 | |
941 | R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1 | |
942 | R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD | |
943 | R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 | |
944 | R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 | |
945 | R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>; | |
c5d82c99 | 946 | clock-output-names = |
3f37e018 SS |
947 | "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", |
948 | "gpio1", "gpio0", "qspi_mod", | |
949 | "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; | |
3281480b | 950 | }; |
0dce5454 UH |
951 | mstp11_clks: mstp11_clks@e615099c { |
952 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
953 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | |
954 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; | |
955 | #clock-cells = <1>; | |
1045d065 | 956 | clock-indices = < |
0dce5454 UH |
957 | R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 |
958 | >; | |
959 | clock-output-names = "scifa3", "scifa4", "scifa5"; | |
960 | }; | |
961 | }; | |
1cb2794f LP |
962 | |
963 | ipmmu_sy0: mmu@e6280000 { | |
964 | compatible = "renesas,ipmmu-vmsa"; | |
965 | reg = <0 0xe6280000 0 0x1000>; | |
966 | interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, | |
967 | <0 224 IRQ_TYPE_LEVEL_HIGH>; | |
968 | #iommu-cells = <1>; | |
969 | status = "disabled"; | |
970 | }; | |
971 | ||
972 | ipmmu_sy1: mmu@e6290000 { | |
973 | compatible = "renesas,ipmmu-vmsa"; | |
974 | reg = <0 0xe6290000 0 0x1000>; | |
975 | interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; | |
976 | #iommu-cells = <1>; | |
977 | status = "disabled"; | |
978 | }; | |
979 | ||
980 | ipmmu_ds: mmu@e6740000 { | |
981 | compatible = "renesas,ipmmu-vmsa"; | |
982 | reg = <0 0xe6740000 0 0x1000>; | |
983 | interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, | |
984 | <0 199 IRQ_TYPE_LEVEL_HIGH>; | |
985 | #iommu-cells = <1>; | |
986 | }; | |
987 | ||
988 | ipmmu_mp: mmu@ec680000 { | |
989 | compatible = "renesas,ipmmu-vmsa"; | |
990 | reg = <0 0xec680000 0 0x1000>; | |
991 | interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; | |
992 | #iommu-cells = <1>; | |
993 | status = "disabled"; | |
994 | }; | |
995 | ||
996 | ipmmu_mx: mmu@fe951000 { | |
997 | compatible = "renesas,ipmmu-vmsa"; | |
998 | reg = <0 0xfe951000 0 0x1000>; | |
999 | interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, | |
1000 | <0 221 IRQ_TYPE_LEVEL_HIGH>; | |
1001 | #iommu-cells = <1>; | |
1002 | }; | |
1003 | ||
1004 | ipmmu_gp: mmu@e62a0000 { | |
1005 | compatible = "renesas,ipmmu-vmsa"; | |
1006 | reg = <0 0xe62a0000 0 0x1000>; | |
1007 | interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, | |
1008 | <0 261 IRQ_TYPE_LEVEL_HIGH>; | |
1009 | #iommu-cells = <1>; | |
1010 | status = "disabled"; | |
1011 | }; | |
0dce5454 | 1012 | }; |