projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| faea098e XZ |
1 | /* |
| 2 | * This file is dual-licensed: you can use it either under the terms | |
| 3 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 4 | * licensing only applies to this file, and not this project as a | |
| 5 | * whole. | |
| 6 | * | |
| 7 | * a) This file is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of the | |
| 10 | * License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This file is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * Or, alternatively, | |
| 18 | * | |
| 19 | * b) Permission is hereby granted, free of charge, to any person | |
| 20 | * obtaining a copy of this software and associated documentation | |
| 21 | * files (the "Software"), to deal in the Software without | |
| 22 | * restriction, including without limitation the rights to use, | |
| 23 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 24 | * sell copies of the Software, and to permit persons to whom the | |
| 25 | * Software is furnished to do so, subject to the following | |
| 26 | * conditions: | |
| 27 | * | |
| 28 | * The above copyright notice and this permission notice shall be | |
| 29 | * included in all copies or substantial portions of the Software. | |
| 30 | * | |
| 31 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 32 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 33 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 34 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 35 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 36 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 37 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 38 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 39 | */ | |
| 40 | ||
| 41 | #include <dt-bindings/gpio/gpio.h> | |
| 42 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 43 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 44 | #include <dt-bindings/pinctrl/rockchip.h> | |
| 45 | #include <dt-bindings/clock/rk3036-cru.h> | |
| b60ab70b | 46 | #include <dt-bindings/soc/rockchip,boot-mode.h> |
| faea098e XZ |
47 | |
| 48 | / { | |
| 5418e460 JMC |
49 | #address-cells = <1>; |
| 50 | #size-cells = <1>; | |
| 51 | ||
| faea098e XZ |
52 | compatible = "rockchip,rk3036"; |
| 53 | ||
| 54 | interrupt-parent = <&gic>; | |
| 55 | ||
| 56 | aliases { | |
| 57 | i2c0 = &i2c0; | |
| 58 | i2c1 = &i2c1; | |
| 59 | i2c2 = &i2c2; | |
| 60 | mshc0 = &emmc; | |
| 187d7967 CW |
61 | mshc1 = &sdmmc; |
| 62 | mshc2 = &sdio; | |
| faea098e XZ |
63 | serial0 = &uart0; |
| 64 | serial1 = &uart1; | |
| 65 | serial2 = &uart2; | |
| f629fcfa | 66 | spi = &spi; |
| faea098e XZ |
67 | }; |
| 68 | ||
| faea098e XZ |
69 | cpus { |
| 70 | #address-cells = <1>; | |
| 71 | #size-cells = <0>; | |
| 72 | enable-method = "rockchip,rk3036-smp"; | |
| 73 | ||
| 74 | cpu0: cpu@f00 { | |
| 75 | device_type = "cpu"; | |
| 76 | compatible = "arm,cortex-a7"; | |
| 77 | reg = <0xf00>; | |
| 78 | resets = <&cru SRST_CORE0>; | |
| 79 | operating-points = < | |
| 80 | /* KHz uV */ | |
| 81 | 816000 1000000 | |
| 82 | >; | |
| 83 | clock-latency = <40000>; | |
| 84 | clocks = <&cru ARMCLK>; | |
| 85 | }; | |
| 86 | ||
| 87 | cpu1: cpu@f01 { | |
| 88 | device_type = "cpu"; | |
| 89 | compatible = "arm,cortex-a7"; | |
| 90 | reg = <0xf01>; | |
| 91 | resets = <&cru SRST_CORE1>; | |
| 92 | }; | |
| 93 | }; | |
| 94 | ||
| 95 | amba { | |
| 2ef7d5f3 | 96 | compatible = "simple-bus"; |
| faea098e XZ |
97 | #address-cells = <1>; |
| 98 | #size-cells = <1>; | |
| 99 | ranges; | |
| 100 | ||
| 101 | pdma: pdma@20078000 { | |
| 102 | compatible = "arm,pl330", "arm,primecell"; | |
| 103 | reg = <0x20078000 0x4000>; | |
| 104 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
| 105 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
| 106 | #dma-cells = <1>; | |
| 29f12bba | 107 | arm,pl330-broken-no-flushp; |
| faea098e XZ |
108 | clocks = <&cru ACLK_DMAC2>; |
| 109 | clock-names = "apb_pclk"; | |
| 110 | }; | |
| 111 | }; | |
| 112 | ||
| 113 | arm-pmu { | |
| 114 | compatible = "arm,cortex-a7-pmu"; | |
| 115 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, | |
| 116 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 117 | interrupt-affinity = <&cpu0>, <&cpu1>; | |
| 118 | }; | |
| 119 | ||
| d9abae3c CW |
120 | display-subsystem { |
| 121 | compatible = "rockchip,display-subsystem"; | |
| 122 | ports = <&vop_out>; | |
| 123 | }; | |
| 124 | ||
| faea098e XZ |
125 | timer { |
| 126 | compatible = "arm,armv7-timer"; | |
| 127 | arm,cpu-registers-not-fw-configured; | |
| 128 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 129 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 130 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 131 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 132 | clock-frequency = <24000000>; | |
| 133 | }; | |
| 134 | ||
| 135 | xin24m: oscillator { | |
| 136 | compatible = "fixed-clock"; | |
| 137 | clock-frequency = <24000000>; | |
| 138 | clock-output-names = "xin24m"; | |
| 139 | #clock-cells = <0>; | |
| 140 | }; | |
| 141 | ||
| 142 | bus_intmem@10080000 { | |
| 143 | compatible = "mmio-sram"; | |
| 144 | reg = <0x10080000 0x2000>; | |
| 145 | #address-cells = <1>; | |
| 146 | #size-cells = <1>; | |
| 147 | ranges = <0 0x10080000 0x2000>; | |
| 148 | ||
| 149 | smp-sram@0 { | |
| 150 | compatible = "rockchip,rk3066-smp-sram"; | |
| 151 | reg = <0x00 0x10>; | |
| 152 | }; | |
| 153 | }; | |
| 154 | ||
| d9abae3c CW |
155 | vop: vop@10118000 { |
| 156 | compatible = "rockchip,rk3036-vop"; | |
| 157 | reg = <0x10118000 0x19c>; | |
| 158 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
| 159 | clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; | |
| 160 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
| 161 | resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; | |
| 162 | reset-names = "axi", "ahb", "dclk"; | |
| 163 | iommus = <&vop_mmu>; | |
| 164 | status = "disabled"; | |
| 165 | ||
| 166 | vop_out: port { | |
| 167 | #address-cells = <1>; | |
| 168 | #size-cells = <0>; | |
| b7217cf1 CW |
169 | vop_out_hdmi: endpoint@0 { |
| 170 | reg = <0>; | |
| 171 | remote-endpoint = <&hdmi_in_vop>; | |
| 172 | }; | |
| d9abae3c CW |
173 | }; |
| 174 | }; | |
| 175 | ||
| 176 | vop_mmu: iommu@10118300 { | |
| 177 | compatible = "rockchip,iommu"; | |
| 178 | reg = <0x10118300 0x100>; | |
| 179 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
| 180 | interrupt-names = "vop_mmu"; | |
| 181 | #iommu-cells = <0>; | |
| 182 | status = "disabled"; | |
| 183 | }; | |
| 184 | ||
| faea098e XZ |
185 | gic: interrupt-controller@10139000 { |
| 186 | compatible = "arm,gic-400"; | |
| 187 | interrupt-controller; | |
| 188 | #interrupt-cells = <3>; | |
| 189 | #address-cells = <0>; | |
| 190 | ||
| 191 | reg = <0x10139000 0x1000>, | |
| 192 | <0x1013a000 0x1000>, | |
| 193 | <0x1013c000 0x2000>, | |
| 194 | <0x1013e000 0x2000>; | |
| 195 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 196 | }; | |
| 197 | ||
| 198 | usb_otg: usb@10180000 { | |
| 0082180c | 199 | compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", |
| faea098e XZ |
200 | "snps,dwc2"; |
| 201 | reg = <0x10180000 0x40000>; | |
| 202 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 203 | clocks = <&cru HCLK_OTG0>; | |
| 204 | clock-names = "otg"; | |
| 205 | dr_mode = "otg"; | |
| 206 | g-np-tx-fifo-size = <16>; | |
| 207 | g-rx-fifo-size = <275>; | |
| 208 | g-tx-fifo-size = <256 128 128 64 64 32>; | |
| faea098e XZ |
209 | status = "disabled"; |
| 210 | }; | |
| 211 | ||
| 212 | usb_host: usb@101c0000 { | |
| 0082180c | 213 | compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", |
| faea098e XZ |
214 | "snps,dwc2"; |
| 215 | reg = <0x101c0000 0x40000>; | |
| 216 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 217 | clocks = <&cru HCLK_OTG1>; | |
| 218 | clock-names = "otg"; | |
| 219 | dr_mode = "host"; | |
| 220 | status = "disabled"; | |
| 221 | }; | |
| 222 | ||
| af671e7b XZ |
223 | emac: ethernet@10200000 { |
| 224 | compatible = "rockchip,rk3036-emac", "snps,arc-emac"; | |
| 225 | reg = <0x10200000 0x4000>; | |
| 226 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 227 | #address-cells = <1>; | |
| 228 | #size-cells = <0>; | |
| 229 | rockchip,grf = <&grf>; | |
| 230 | clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; | |
| 231 | clock-names = "hclk", "macref", "macclk"; | |
| 232 | /* | |
| 233 | * Fix the emac parent clock is DPLL instead of APLL. | |
| 234 | * since that will cause some unstable things if the cpufreq | |
| 235 | * is working. (e.g: the accurate 50MHz what mac_ref need) | |
| 236 | */ | |
| 237 | assigned-clocks = <&cru SCLK_MACPLL>; | |
| 238 | assigned-clock-parents = <&cru PLL_DPLL>; | |
| 239 | max-speed = <100>; | |
| 240 | phy-mode = "rmii"; | |
| 241 | status = "disabled"; | |
| 242 | }; | |
| 243 | ||
| 187d7967 CW |
244 | sdmmc: dwmmc@10214000 { |
| 245 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
| 246 | reg = <0x10214000 0x4000>; | |
| 247 | clock-frequency = <37500000>; | |
| 6a8883d6 | 248 | max-frequency = <37500000>; |
| 187d7967 CW |
249 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; |
| 250 | clock-names = "biu", "ciu"; | |
| 251 | fifo-depth = <0x100>; | |
| 252 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 253 | status = "disabled"; | |
| 254 | }; | |
| 255 | ||
| 256 | sdio: dwmmc@10218000 { | |
| 257 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
| 258 | reg = <0x10218000 0x4000>; | |
| 6a8883d6 | 259 | max-frequency = <37500000>; |
| 187d7967 CW |
260 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, |
| 261 | <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; | |
| 262 | clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; | |
| 263 | fifo-depth = <0x100>; | |
| 264 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
| 265 | status = "disabled"; | |
| 266 | }; | |
| 267 | ||
| faea098e | 268 | emmc: dwmmc@1021c000 { |
| 0082180c | 269 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; |
| faea098e XZ |
270 | reg = <0x1021c000 0x4000>; |
| 271 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| faea098e XZ |
272 | bus-width = <8>; |
| 273 | cap-mmc-highspeed; | |
| 274 | clock-frequency = <37500000>; | |
| 6a8883d6 | 275 | max-frequency = <37500000>; |
| faea098e XZ |
276 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, |
| 277 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; | |
| 278 | clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; | |
| 279 | default-sample-phase = <158>; | |
| 280 | disable-wp; | |
| 281 | dmas = <&pdma 12>; | |
| 282 | dma-names = "rx-tx"; | |
| 283 | fifo-depth = <0x100>; | |
| 284 | mmc-ddr-1_8v; | |
| 285 | non-removable; | |
| 286 | num-slots = <1>; | |
| 287 | pinctrl-names = "default"; | |
| 288 | pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; | |
| 289 | status = "disabled"; | |
| 290 | }; | |
| 291 | ||
| 292 | i2s: i2s@10220000 { | |
| 293 | compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; | |
| 294 | reg = <0x10220000 0x4000>; | |
| 295 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
| 296 | #address-cells = <1>; | |
| 297 | #size-cells = <0>; | |
| 3860aa1c HS |
298 | clock-names = "i2s_clk", "i2s_hclk"; |
| 299 | clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; | |
| faea098e XZ |
300 | dmas = <&pdma 0>, <&pdma 1>; |
| 301 | dma-names = "tx", "rx"; | |
| 302 | pinctrl-names = "default"; | |
| 303 | pinctrl-0 = <&i2s_bus>; | |
| 304 | status = "disabled"; | |
| 305 | }; | |
| 306 | ||
| 307 | cru: clock-controller@20000000 { | |
| 308 | compatible = "rockchip,rk3036-cru"; | |
| 309 | reg = <0x20000000 0x1000>; | |
| 310 | rockchip,grf = <&grf>; | |
| 311 | #clock-cells = <1>; | |
| 312 | #reset-cells = <1>; | |
| 313 | assigned-clocks = <&cru PLL_GPLL>; | |
| 314 | assigned-clock-rates = <594000000>; | |
| 315 | }; | |
| 316 | ||
| 317 | grf: syscon@20008000 { | |
| b60ab70b | 318 | compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; |
| faea098e | 319 | reg = <0x20008000 0x1000>; |
| b60ab70b AY |
320 | |
| 321 | reboot-mode { | |
| 322 | compatible = "syscon-reboot-mode"; | |
| 323 | offset = <0x1d8>; | |
| 324 | mode-normal = <BOOT_NORMAL>; | |
| 325 | mode-recovery = <BOOT_RECOVERY>; | |
| 326 | mode-bootloader = <BOOT_FASTBOOT>; | |
| 327 | mode-loader = <BOOT_BL_DOWNLOAD>; | |
| 328 | }; | |
| faea098e XZ |
329 | }; |
| 330 | ||
| 331 | acodec: acodec-ana@20030000 { | |
| 332 | compatible = "rk3036-codec"; | |
| 333 | reg = <0x20030000 0x4000>; | |
| 334 | rockchip,grf = <&grf>; | |
| 335 | clock-names = "acodec_pclk"; | |
| 336 | clocks = <&cru PCLK_ACODEC>; | |
| 337 | status = "disabled"; | |
| 338 | }; | |
| 339 | ||
| b7217cf1 CW |
340 | hdmi: hdmi@20034000 { |
| 341 | compatible = "rockchip,rk3036-inno-hdmi"; | |
| 342 | reg = <0x20034000 0x4000>; | |
| 343 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
| 344 | clocks = <&cru PCLK_HDMI>; | |
| 345 | clock-names = "pclk"; | |
| 346 | rockchip,grf = <&grf>; | |
| 347 | pinctrl-names = "default"; | |
| 348 | pinctrl-0 = <&hdmi_ctl>; | |
| 349 | status = "disabled"; | |
| 350 | ||
| 351 | hdmi_in: port { | |
| 352 | #address-cells = <1>; | |
| 353 | #size-cells = <0>; | |
| 354 | hdmi_in_vop: endpoint@0 { | |
| 355 | reg = <0>; | |
| 356 | remote-endpoint = <&vop_out_hdmi>; | |
| 357 | }; | |
| 358 | }; | |
| 359 | }; | |
| 360 | ||
| faea098e XZ |
361 | timer: timer@20044000 { |
| 362 | compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; | |
| 363 | reg = <0x20044000 0x20>; | |
| 364 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
| 365 | clocks = <&xin24m>, <&cru PCLK_TIMER>; | |
| 366 | clock-names = "timer", "pclk"; | |
| 367 | }; | |
| 368 | ||
| 369 | pwm0: pwm@20050000 { | |
| 370 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
| 371 | reg = <0x20050000 0x10>; | |
| 372 | #pwm-cells = <3>; | |
| 373 | clocks = <&cru PCLK_PWM>; | |
| 374 | clock-names = "pwm"; | |
| 375 | pinctrl-names = "default"; | |
| 376 | pinctrl-0 = <&pwm0_pin>; | |
| 377 | status = "disabled"; | |
| 378 | }; | |
| 379 | ||
| 380 | pwm1: pwm@20050010 { | |
| 381 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
| 382 | reg = <0x20050010 0x10>; | |
| 383 | #pwm-cells = <3>; | |
| 384 | clocks = <&cru PCLK_PWM>; | |
| 385 | clock-names = "pwm"; | |
| 386 | pinctrl-names = "default"; | |
| 387 | pinctrl-0 = <&pwm1_pin>; | |
| 388 | status = "disabled"; | |
| 389 | }; | |
| 390 | ||
| 391 | pwm2: pwm@20050020 { | |
| 392 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
| 393 | reg = <0x20050020 0x10>; | |
| 394 | #pwm-cells = <3>; | |
| 395 | clocks = <&cru PCLK_PWM>; | |
| 396 | clock-names = "pwm"; | |
| 397 | pinctrl-names = "default"; | |
| 398 | pinctrl-0 = <&pwm2_pin>; | |
| 399 | status = "disabled"; | |
| 400 | }; | |
| 401 | ||
| 402 | pwm3: pwm@20050030 { | |
| 403 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
| 404 | reg = <0x20050030 0x10>; | |
| 405 | #pwm-cells = <2>; | |
| 406 | clocks = <&cru PCLK_PWM>; | |
| 407 | clock-names = "pwm"; | |
| 408 | pinctrl-names = "default"; | |
| 409 | pinctrl-0 = <&pwm3_pin>; | |
| 410 | status = "disabled"; | |
| 411 | }; | |
| 412 | ||
| 413 | i2c1: i2c@20056000 { | |
| 0082180c | 414 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
| faea098e XZ |
415 | reg = <0x20056000 0x1000>; |
| 416 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
| 417 | #address-cells = <1>; | |
| 418 | #size-cells = <0>; | |
| 419 | clock-names = "i2c"; | |
| 420 | clocks = <&cru PCLK_I2C1>; | |
| 421 | pinctrl-names = "default"; | |
| 422 | pinctrl-0 = <&i2c1_xfer>; | |
| 423 | status = "disabled"; | |
| 424 | }; | |
| 425 | ||
| 426 | i2c2: i2c@2005a000 { | |
| 0082180c | 427 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
| faea098e XZ |
428 | reg = <0x2005a000 0x1000>; |
| 429 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
| 430 | #address-cells = <1>; | |
| 431 | #size-cells = <0>; | |
| 432 | clock-names = "i2c"; | |
| 433 | clocks = <&cru PCLK_I2C2>; | |
| 434 | pinctrl-names = "default"; | |
| 435 | pinctrl-0 = <&i2c2_xfer>; | |
| 436 | status = "disabled"; | |
| 437 | }; | |
| 438 | ||
| 439 | uart0: serial@20060000 { | |
| 440 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
| 441 | reg = <0x20060000 0x100>; | |
| 442 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 443 | reg-shift = <2>; | |
| 444 | reg-io-width = <4>; | |
| 445 | clock-frequency = <24000000>; | |
| 446 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
| 447 | clock-names = "baudclk", "apb_pclk"; | |
| 448 | pinctrl-names = "default"; | |
| 449 | pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; | |
| 450 | status = "disabled"; | |
| 451 | }; | |
| 452 | ||
| 453 | uart1: serial@20064000 { | |
| 454 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
| 455 | reg = <0x20064000 0x100>; | |
| 456 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
| 457 | reg-shift = <2>; | |
| 458 | reg-io-width = <4>; | |
| 459 | clock-frequency = <24000000>; | |
| 460 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
| 461 | clock-names = "baudclk", "apb_pclk"; | |
| 462 | pinctrl-names = "default"; | |
| 463 | pinctrl-0 = <&uart1_xfer>; | |
| 464 | status = "disabled"; | |
| 465 | }; | |
| 466 | ||
| 467 | uart2: serial@20068000 { | |
| 468 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
| 469 | reg = <0x20068000 0x100>; | |
| 470 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
| 471 | reg-shift = <2>; | |
| 472 | reg-io-width = <4>; | |
| 473 | clock-frequency = <24000000>; | |
| 474 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
| 475 | clock-names = "baudclk", "apb_pclk"; | |
| 476 | pinctrl-names = "default"; | |
| 477 | pinctrl-0 = <&uart2_xfer>; | |
| 478 | status = "disabled"; | |
| 479 | }; | |
| 480 | ||
| 481 | i2c0: i2c@20072000 { | |
| 0082180c | 482 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
| faea098e XZ |
483 | reg = <0x20072000 0x1000>; |
| 484 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
| 485 | #address-cells = <1>; | |
| 486 | #size-cells = <0>; | |
| 487 | clock-names = "i2c"; | |
| 488 | clocks = <&cru PCLK_I2C0>; | |
| 489 | pinctrl-names = "default"; | |
| 490 | pinctrl-0 = <&i2c0_xfer>; | |
| 491 | status = "disabled"; | |
| 492 | }; | |
| 493 | ||
| f629fcfa CW |
494 | spi: spi@20074000 { |
| 495 | compatible = "rockchip,rockchip-spi"; | |
| 496 | reg = <0x20074000 0x1000>; | |
| 497 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 498 | clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>; | |
| 499 | clock-names = "apb-pclk","spi_pclk"; | |
| 500 | dmas = <&pdma 8>, <&pdma 9>; | |
| 501 | dma-names = "tx", "rx"; | |
| 502 | pinctrl-names = "default"; | |
| 503 | pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; | |
| 504 | #address-cells = <1>; | |
| 505 | #size-cells = <0>; | |
| 506 | status = "disabled"; | |
| 507 | }; | |
| 508 | ||
| faea098e XZ |
509 | pinctrl: pinctrl { |
| 510 | compatible = "rockchip,rk3036-pinctrl"; | |
| 511 | rockchip,grf = <&grf>; | |
| 512 | #address-cells = <1>; | |
| 513 | #size-cells = <1>; | |
| 514 | ranges; | |
| 515 | ||
| 516 | gpio0: gpio0@2007c000 { | |
| 517 | compatible = "rockchip,gpio-bank"; | |
| 518 | reg = <0x2007c000 0x100>; | |
| 519 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 520 | clocks = <&cru PCLK_GPIO0>; | |
| 521 | ||
| 522 | gpio-controller; | |
| 523 | #gpio-cells = <2>; | |
| 524 | ||
| 525 | interrupt-controller; | |
| 526 | #interrupt-cells = <2>; | |
| 527 | }; | |
| 528 | ||
| 529 | gpio1: gpio1@20080000 { | |
| 530 | compatible = "rockchip,gpio-bank"; | |
| 531 | reg = <0x20080000 0x100>; | |
| 532 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 533 | clocks = <&cru PCLK_GPIO1>; | |
| 534 | ||
| 535 | gpio-controller; | |
| 536 | #gpio-cells = <2>; | |
| 537 | ||
| 538 | interrupt-controller; | |
| 539 | #interrupt-cells = <2>; | |
| 540 | }; | |
| 541 | ||
| 542 | gpio2: gpio2@20084000 { | |
| 543 | compatible = "rockchip,gpio-bank"; | |
| 544 | reg = <0x20084000 0x100>; | |
| 545 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
| 546 | clocks = <&cru PCLK_GPIO2>; | |
| 547 | ||
| 548 | gpio-controller; | |
| 549 | #gpio-cells = <2>; | |
| 550 | ||
| 551 | interrupt-controller; | |
| 552 | #interrupt-cells = <2>; | |
| 553 | }; | |
| 554 | ||
| 68556dd7 XZ |
555 | pcfg_pull_default: pcfg_pull_default { |
| 556 | bias-pull-pin-default; | |
| faea098e XZ |
557 | }; |
| 558 | ||
| 559 | pcfg_pull_none: pcfg-pull-none { | |
| 560 | bias-disable; | |
| 561 | }; | |
| 562 | ||
| 563 | pwm0 { | |
| 564 | pwm0_pin: pwm0-pin { | |
| 565 | rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; | |
| 566 | }; | |
| 567 | }; | |
| 568 | ||
| 569 | pwm1 { | |
| 570 | pwm1_pin: pwm1-pin { | |
| 571 | rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; | |
| 572 | }; | |
| 573 | }; | |
| 574 | ||
| 575 | pwm2 { | |
| 576 | pwm2_pin: pwm2-pin { | |
| 577 | rockchip,pins = <0 1 2 &pcfg_pull_none>; | |
| 578 | }; | |
| 579 | }; | |
| 580 | ||
| 581 | pwm3 { | |
| 582 | pwm3_pin: pwm3-pin { | |
| 583 | rockchip,pins = <0 27 1 &pcfg_pull_none>; | |
| 584 | }; | |
| 585 | }; | |
| 586 | ||
| 187d7967 CW |
587 | sdmmc { |
| 588 | sdmmc_clk: sdmmc-clk { | |
| 589 | rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>; | |
| 590 | }; | |
| 591 | ||
| 592 | sdmmc_cmd: sdmmc-cmd { | |
| 593 | rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>; | |
| 594 | }; | |
| 595 | ||
| 596 | sdmmc_cd: sdmcc-cd { | |
| 597 | rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>; | |
| 598 | }; | |
| 599 | ||
| 600 | sdmmc_bus1: sdmmc-bus1 { | |
| 601 | rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>; | |
| 602 | }; | |
| 603 | ||
| 604 | sdmmc_bus4: sdmmc-bus4 { | |
| 605 | rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>, | |
| 606 | <1 19 RK_FUNC_1 &pcfg_pull_default>, | |
| 607 | <1 20 RK_FUNC_1 &pcfg_pull_default>, | |
| 608 | <1 21 RK_FUNC_1 &pcfg_pull_default>; | |
| 609 | }; | |
| 610 | }; | |
| 611 | ||
| 612 | sdio { | |
| 613 | sdio_bus1: sdio-bus1 { | |
| 614 | rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>; | |
| 615 | }; | |
| 616 | ||
| 617 | sdio_bus4: sdio-bus4 { | |
| 618 | rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>, | |
| 619 | <0 12 RK_FUNC_1 &pcfg_pull_default>, | |
| 620 | <0 13 RK_FUNC_1 &pcfg_pull_default>, | |
| 621 | <0 14 RK_FUNC_1 &pcfg_pull_default>; | |
| 622 | }; | |
| 623 | ||
| 624 | sdio_cmd: sdio-cmd { | |
| 625 | rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>; | |
| 626 | }; | |
| 627 | ||
| 628 | sdio_clk: sdio-clk { | |
| 629 | rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>; | |
| 630 | }; | |
| 631 | }; | |
| 632 | ||
| faea098e XZ |
633 | emmc { |
| 634 | /* | |
| 635 | * We run eMMC at max speed; bump up drive strength. | |
| 636 | * We also have external pulls, so disable the internal ones. | |
| 637 | */ | |
| 638 | emmc_clk: emmc-clk { | |
| 639 | rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; | |
| 640 | }; | |
| 641 | ||
| 642 | emmc_cmd: emmc-cmd { | |
| 68556dd7 | 643 | rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>; |
| faea098e XZ |
644 | }; |
| 645 | ||
| 646 | emmc_bus8: emmc-bus8 { | |
| 68556dd7 XZ |
647 | rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>, |
| 648 | <1 25 RK_FUNC_2 &pcfg_pull_default>, | |
| 649 | <1 26 RK_FUNC_2 &pcfg_pull_default>, | |
| 650 | <1 27 RK_FUNC_2 &pcfg_pull_default>, | |
| 651 | <1 28 RK_FUNC_2 &pcfg_pull_default>, | |
| 652 | <1 29 RK_FUNC_2 &pcfg_pull_default>, | |
| 653 | <1 30 RK_FUNC_2 &pcfg_pull_default>, | |
| 654 | <1 31 RK_FUNC_2 &pcfg_pull_default>; | |
| faea098e XZ |
655 | }; |
| 656 | }; | |
| 657 | ||
| af671e7b XZ |
658 | emac { |
| 659 | emac_xfer: emac-xfer { | |
| 660 | rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */ | |
| 661 | <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */ | |
| 662 | <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */ | |
| 663 | <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */ | |
| 664 | <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */ | |
| 665 | <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */ | |
| 666 | <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */ | |
| 667 | <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */ | |
| 668 | }; | |
| 669 | ||
| 670 | emac_mdio: emac-mdio { | |
| 671 | rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */ | |
| 672 | <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */ | |
| 673 | }; | |
| 674 | }; | |
| 675 | ||
| faea098e XZ |
676 | i2c0 { |
| 677 | i2c0_xfer: i2c0-xfer { | |
| 678 | rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, | |
| 679 | <0 1 RK_FUNC_1 &pcfg_pull_none>; | |
| 680 | }; | |
| 681 | }; | |
| 682 | ||
| 683 | i2c1 { | |
| 684 | i2c1_xfer: i2c1-xfer { | |
| 685 | rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, | |
| 686 | <0 3 RK_FUNC_1 &pcfg_pull_none>; | |
| 687 | }; | |
| 688 | }; | |
| 689 | ||
| 690 | i2c2 { | |
| 691 | i2c2_xfer: i2c2-xfer { | |
| 692 | rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, | |
| 693 | <2 21 RK_FUNC_1 &pcfg_pull_none>; | |
| 694 | }; | |
| 695 | }; | |
| 696 | ||
| 697 | i2s { | |
| 698 | i2s_bus: i2s-bus { | |
| f4755332 CW |
699 | rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>, |
| 700 | <1 1 RK_FUNC_1 &pcfg_pull_default>, | |
| 701 | <1 2 RK_FUNC_1 &pcfg_pull_default>, | |
| 702 | <1 3 RK_FUNC_1 &pcfg_pull_default>, | |
| 703 | <1 4 RK_FUNC_1 &pcfg_pull_default>, | |
| 704 | <1 5 RK_FUNC_1 &pcfg_pull_default>; | |
| faea098e XZ |
705 | }; |
| 706 | }; | |
| 707 | ||
| b7217cf1 CW |
708 | hdmi { |
| 709 | hdmi_ctl: hdmi-ctl { | |
| 710 | rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>, | |
| 711 | <1 9 RK_FUNC_1 &pcfg_pull_none>, | |
| 712 | <1 10 RK_FUNC_1 &pcfg_pull_none>, | |
| 713 | <1 11 RK_FUNC_1 &pcfg_pull_none>; | |
| 714 | }; | |
| 715 | }; | |
| 716 | ||
| faea098e XZ |
717 | uart0 { |
| 718 | uart0_xfer: uart0-xfer { | |
| 68556dd7 | 719 | rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>, |
| faea098e XZ |
720 | <0 17 RK_FUNC_1 &pcfg_pull_none>; |
| 721 | }; | |
| 722 | ||
| 723 | uart0_cts: uart0-cts { | |
| 68556dd7 | 724 | rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>; |
| faea098e XZ |
725 | }; |
| 726 | ||
| 727 | uart0_rts: uart0-rts { | |
| 728 | rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; | |
| 729 | }; | |
| 730 | }; | |
| 731 | ||
| 732 | uart1 { | |
| 733 | uart1_xfer: uart1-xfer { | |
| 68556dd7 | 734 | rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>, |
| faea098e XZ |
735 | <2 23 RK_FUNC_1 &pcfg_pull_none>; |
| 736 | }; | |
| 737 | /* no rts / cts for uart1 */ | |
| 738 | }; | |
| 739 | ||
| 740 | uart2 { | |
| 741 | uart2_xfer: uart2-xfer { | |
| 68556dd7 | 742 | rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>, |
| faea098e XZ |
743 | <1 19 RK_FUNC_2 &pcfg_pull_none>; |
| 744 | }; | |
| 745 | /* no rts / cts for uart2 */ | |
| 746 | }; | |
| f629fcfa CW |
747 | |
| 748 | spi { | |
| 749 | spi_txd:spi-txd { | |
| 750 | rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>; | |
| 751 | }; | |
| 752 | ||
| 753 | spi_rxd:spi-rxd { | |
| 754 | rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>; | |
| 755 | }; | |
| 756 | ||
| 757 | spi_clk:spi-clk { | |
| 758 | rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>; | |
| 759 | }; | |
| 760 | ||
| 761 | spi_cs0:spi-cs0 { | |
| 762 | rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>; | |
| 763 | ||
| 764 | }; | |
| 765 | ||
| 766 | spi_cs1:spi-cs1 { | |
| 767 | rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>; | |
| 768 | ||
| 769 | }; | |
| 770 | }; | |
| faea098e XZ |
771 | }; |
| 772 | }; |