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faea098e XZ |
1 | /* |
2 | * This file is dual-licensed: you can use it either under the terms | |
3 | * of the GPL or the X11 license, at your option. Note that this dual | |
4 | * licensing only applies to this file, and not this project as a | |
5 | * whole. | |
6 | * | |
7 | * a) This file is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of the | |
10 | * License, or (at your option) any later version. | |
11 | * | |
12 | * This file is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * Or, alternatively, | |
18 | * | |
19 | * b) Permission is hereby granted, free of charge, to any person | |
20 | * obtaining a copy of this software and associated documentation | |
21 | * files (the "Software"), to deal in the Software without | |
22 | * restriction, including without limitation the rights to use, | |
23 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
24 | * sell copies of the Software, and to permit persons to whom the | |
25 | * Software is furnished to do so, subject to the following | |
26 | * conditions: | |
27 | * | |
28 | * The above copyright notice and this permission notice shall be | |
29 | * included in all copies or substantial portions of the Software. | |
30 | * | |
31 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
32 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
33 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
34 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
35 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
36 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
37 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
38 | * OTHER DEALINGS IN THE SOFTWARE. | |
39 | */ | |
40 | ||
41 | #include <dt-bindings/gpio/gpio.h> | |
42 | #include <dt-bindings/interrupt-controller/irq.h> | |
43 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
44 | #include <dt-bindings/pinctrl/rockchip.h> | |
45 | #include <dt-bindings/clock/rk3036-cru.h> | |
46 | #include "skeleton.dtsi" | |
47 | ||
48 | / { | |
49 | compatible = "rockchip,rk3036"; | |
50 | ||
51 | interrupt-parent = <&gic>; | |
52 | ||
53 | aliases { | |
54 | i2c0 = &i2c0; | |
55 | i2c1 = &i2c1; | |
56 | i2c2 = &i2c2; | |
57 | mshc0 = &emmc; | |
187d7967 CW |
58 | mshc1 = &sdmmc; |
59 | mshc2 = &sdio; | |
faea098e XZ |
60 | serial0 = &uart0; |
61 | serial1 = &uart1; | |
62 | serial2 = &uart2; | |
63 | }; | |
64 | ||
65 | memory { | |
66 | device_type = "memory"; | |
67 | reg = <0x60000000 0x40000000>; | |
68 | }; | |
69 | ||
70 | cpus { | |
71 | #address-cells = <1>; | |
72 | #size-cells = <0>; | |
73 | enable-method = "rockchip,rk3036-smp"; | |
74 | ||
75 | cpu0: cpu@f00 { | |
76 | device_type = "cpu"; | |
77 | compatible = "arm,cortex-a7"; | |
78 | reg = <0xf00>; | |
79 | resets = <&cru SRST_CORE0>; | |
80 | operating-points = < | |
81 | /* KHz uV */ | |
82 | 816000 1000000 | |
83 | >; | |
84 | clock-latency = <40000>; | |
85 | clocks = <&cru ARMCLK>; | |
86 | }; | |
87 | ||
88 | cpu1: cpu@f01 { | |
89 | device_type = "cpu"; | |
90 | compatible = "arm,cortex-a7"; | |
91 | reg = <0xf01>; | |
92 | resets = <&cru SRST_CORE1>; | |
93 | }; | |
94 | }; | |
95 | ||
96 | amba { | |
97 | compatible = "arm,amba-bus"; | |
98 | #address-cells = <1>; | |
99 | #size-cells = <1>; | |
100 | ranges; | |
101 | ||
102 | pdma: pdma@20078000 { | |
103 | compatible = "arm,pl330", "arm,primecell"; | |
104 | reg = <0x20078000 0x4000>; | |
105 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
106 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
107 | #dma-cells = <1>; | |
108 | clocks = <&cru ACLK_DMAC2>; | |
109 | clock-names = "apb_pclk"; | |
110 | }; | |
111 | }; | |
112 | ||
113 | arm-pmu { | |
114 | compatible = "arm,cortex-a7-pmu"; | |
115 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, | |
116 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
117 | interrupt-affinity = <&cpu0>, <&cpu1>; | |
118 | }; | |
119 | ||
120 | timer { | |
121 | compatible = "arm,armv7-timer"; | |
122 | arm,cpu-registers-not-fw-configured; | |
123 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
124 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
125 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
126 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
127 | clock-frequency = <24000000>; | |
128 | }; | |
129 | ||
130 | xin24m: oscillator { | |
131 | compatible = "fixed-clock"; | |
132 | clock-frequency = <24000000>; | |
133 | clock-output-names = "xin24m"; | |
134 | #clock-cells = <0>; | |
135 | }; | |
136 | ||
137 | bus_intmem@10080000 { | |
138 | compatible = "mmio-sram"; | |
139 | reg = <0x10080000 0x2000>; | |
140 | #address-cells = <1>; | |
141 | #size-cells = <1>; | |
142 | ranges = <0 0x10080000 0x2000>; | |
143 | ||
144 | smp-sram@0 { | |
145 | compatible = "rockchip,rk3066-smp-sram"; | |
146 | reg = <0x00 0x10>; | |
147 | }; | |
148 | }; | |
149 | ||
150 | gic: interrupt-controller@10139000 { | |
151 | compatible = "arm,gic-400"; | |
152 | interrupt-controller; | |
153 | #interrupt-cells = <3>; | |
154 | #address-cells = <0>; | |
155 | ||
156 | reg = <0x10139000 0x1000>, | |
157 | <0x1013a000 0x1000>, | |
158 | <0x1013c000 0x2000>, | |
159 | <0x1013e000 0x2000>; | |
160 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
161 | }; | |
162 | ||
163 | usb_otg: usb@10180000 { | |
164 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
165 | "snps,dwc2"; | |
166 | reg = <0x10180000 0x40000>; | |
167 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
168 | clocks = <&cru HCLK_OTG0>; | |
169 | clock-names = "otg"; | |
170 | dr_mode = "otg"; | |
171 | g-np-tx-fifo-size = <16>; | |
172 | g-rx-fifo-size = <275>; | |
173 | g-tx-fifo-size = <256 128 128 64 64 32>; | |
174 | g-use-dma; | |
175 | status = "disabled"; | |
176 | }; | |
177 | ||
178 | usb_host: usb@101c0000 { | |
179 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
180 | "snps,dwc2"; | |
181 | reg = <0x101c0000 0x40000>; | |
182 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
183 | clocks = <&cru HCLK_OTG1>; | |
184 | clock-names = "otg"; | |
185 | dr_mode = "host"; | |
186 | status = "disabled"; | |
187 | }; | |
188 | ||
187d7967 CW |
189 | sdmmc: dwmmc@10214000 { |
190 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
191 | reg = <0x10214000 0x4000>; | |
192 | clock-frequency = <37500000>; | |
193 | clock-freq-min-max = <400000 37500000>; | |
194 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; | |
195 | clock-names = "biu", "ciu"; | |
196 | fifo-depth = <0x100>; | |
197 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
198 | status = "disabled"; | |
199 | }; | |
200 | ||
201 | sdio: dwmmc@10218000 { | |
202 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
203 | reg = <0x10218000 0x4000>; | |
204 | clock-freq-min-max = <400000 37500000>; | |
205 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, | |
206 | <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; | |
207 | clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; | |
208 | fifo-depth = <0x100>; | |
209 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
210 | status = "disabled"; | |
211 | }; | |
212 | ||
faea098e XZ |
213 | emmc: dwmmc@1021c000 { |
214 | compatible = "rockchip,rk3288-dw-mshc"; | |
215 | reg = <0x1021c000 0x4000>; | |
216 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
217 | broken-cd; | |
218 | bus-width = <8>; | |
219 | cap-mmc-highspeed; | |
220 | clock-frequency = <37500000>; | |
221 | clock-freq-min-max = <400000 37500000>; | |
222 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, | |
223 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; | |
224 | clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; | |
225 | default-sample-phase = <158>; | |
226 | disable-wp; | |
227 | dmas = <&pdma 12>; | |
228 | dma-names = "rx-tx"; | |
229 | fifo-depth = <0x100>; | |
230 | mmc-ddr-1_8v; | |
231 | non-removable; | |
232 | num-slots = <1>; | |
233 | pinctrl-names = "default"; | |
234 | pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; | |
235 | status = "disabled"; | |
236 | }; | |
237 | ||
238 | i2s: i2s@10220000 { | |
239 | compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; | |
240 | reg = <0x10220000 0x4000>; | |
241 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
242 | #address-cells = <1>; | |
243 | #size-cells = <0>; | |
3860aa1c HS |
244 | clock-names = "i2s_clk", "i2s_hclk"; |
245 | clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; | |
faea098e XZ |
246 | dmas = <&pdma 0>, <&pdma 1>; |
247 | dma-names = "tx", "rx"; | |
248 | pinctrl-names = "default"; | |
249 | pinctrl-0 = <&i2s_bus>; | |
250 | status = "disabled"; | |
251 | }; | |
252 | ||
253 | cru: clock-controller@20000000 { | |
254 | compatible = "rockchip,rk3036-cru"; | |
255 | reg = <0x20000000 0x1000>; | |
256 | rockchip,grf = <&grf>; | |
257 | #clock-cells = <1>; | |
258 | #reset-cells = <1>; | |
259 | assigned-clocks = <&cru PLL_GPLL>; | |
260 | assigned-clock-rates = <594000000>; | |
261 | }; | |
262 | ||
263 | grf: syscon@20008000 { | |
264 | compatible = "rockchip,rk3036-grf", "syscon"; | |
265 | reg = <0x20008000 0x1000>; | |
266 | }; | |
267 | ||
268 | acodec: acodec-ana@20030000 { | |
269 | compatible = "rk3036-codec"; | |
270 | reg = <0x20030000 0x4000>; | |
271 | rockchip,grf = <&grf>; | |
272 | clock-names = "acodec_pclk"; | |
273 | clocks = <&cru PCLK_ACODEC>; | |
274 | status = "disabled"; | |
275 | }; | |
276 | ||
277 | timer: timer@20044000 { | |
278 | compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; | |
279 | reg = <0x20044000 0x20>; | |
280 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
281 | clocks = <&xin24m>, <&cru PCLK_TIMER>; | |
282 | clock-names = "timer", "pclk"; | |
283 | }; | |
284 | ||
285 | pwm0: pwm@20050000 { | |
286 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
287 | reg = <0x20050000 0x10>; | |
288 | #pwm-cells = <3>; | |
289 | clocks = <&cru PCLK_PWM>; | |
290 | clock-names = "pwm"; | |
291 | pinctrl-names = "default"; | |
292 | pinctrl-0 = <&pwm0_pin>; | |
293 | status = "disabled"; | |
294 | }; | |
295 | ||
296 | pwm1: pwm@20050010 { | |
297 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
298 | reg = <0x20050010 0x10>; | |
299 | #pwm-cells = <3>; | |
300 | clocks = <&cru PCLK_PWM>; | |
301 | clock-names = "pwm"; | |
302 | pinctrl-names = "default"; | |
303 | pinctrl-0 = <&pwm1_pin>; | |
304 | status = "disabled"; | |
305 | }; | |
306 | ||
307 | pwm2: pwm@20050020 { | |
308 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
309 | reg = <0x20050020 0x10>; | |
310 | #pwm-cells = <3>; | |
311 | clocks = <&cru PCLK_PWM>; | |
312 | clock-names = "pwm"; | |
313 | pinctrl-names = "default"; | |
314 | pinctrl-0 = <&pwm2_pin>; | |
315 | status = "disabled"; | |
316 | }; | |
317 | ||
318 | pwm3: pwm@20050030 { | |
319 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
320 | reg = <0x20050030 0x10>; | |
321 | #pwm-cells = <2>; | |
322 | clocks = <&cru PCLK_PWM>; | |
323 | clock-names = "pwm"; | |
324 | pinctrl-names = "default"; | |
325 | pinctrl-0 = <&pwm3_pin>; | |
326 | status = "disabled"; | |
327 | }; | |
328 | ||
329 | i2c1: i2c@20056000 { | |
330 | compatible = "rockchip,rk3288-i2c"; | |
331 | reg = <0x20056000 0x1000>; | |
332 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
333 | #address-cells = <1>; | |
334 | #size-cells = <0>; | |
335 | clock-names = "i2c"; | |
336 | clocks = <&cru PCLK_I2C1>; | |
337 | pinctrl-names = "default"; | |
338 | pinctrl-0 = <&i2c1_xfer>; | |
339 | status = "disabled"; | |
340 | }; | |
341 | ||
342 | i2c2: i2c@2005a000 { | |
343 | compatible = "rockchip,rk3288-i2c"; | |
344 | reg = <0x2005a000 0x1000>; | |
345 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
346 | #address-cells = <1>; | |
347 | #size-cells = <0>; | |
348 | clock-names = "i2c"; | |
349 | clocks = <&cru PCLK_I2C2>; | |
350 | pinctrl-names = "default"; | |
351 | pinctrl-0 = <&i2c2_xfer>; | |
352 | status = "disabled"; | |
353 | }; | |
354 | ||
355 | uart0: serial@20060000 { | |
356 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
357 | reg = <0x20060000 0x100>; | |
358 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
359 | reg-shift = <2>; | |
360 | reg-io-width = <4>; | |
361 | clock-frequency = <24000000>; | |
362 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
363 | clock-names = "baudclk", "apb_pclk"; | |
364 | pinctrl-names = "default"; | |
365 | pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; | |
366 | status = "disabled"; | |
367 | }; | |
368 | ||
369 | uart1: serial@20064000 { | |
370 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
371 | reg = <0x20064000 0x100>; | |
372 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
373 | reg-shift = <2>; | |
374 | reg-io-width = <4>; | |
375 | clock-frequency = <24000000>; | |
376 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
377 | clock-names = "baudclk", "apb_pclk"; | |
378 | pinctrl-names = "default"; | |
379 | pinctrl-0 = <&uart1_xfer>; | |
380 | status = "disabled"; | |
381 | }; | |
382 | ||
383 | uart2: serial@20068000 { | |
384 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
385 | reg = <0x20068000 0x100>; | |
386 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
387 | reg-shift = <2>; | |
388 | reg-io-width = <4>; | |
389 | clock-frequency = <24000000>; | |
390 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
391 | clock-names = "baudclk", "apb_pclk"; | |
392 | pinctrl-names = "default"; | |
393 | pinctrl-0 = <&uart2_xfer>; | |
394 | status = "disabled"; | |
395 | }; | |
396 | ||
397 | i2c0: i2c@20072000 { | |
398 | compatible = "rockchip,rk3288-i2c"; | |
399 | reg = <0x20072000 0x1000>; | |
400 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
401 | #address-cells = <1>; | |
402 | #size-cells = <0>; | |
403 | clock-names = "i2c"; | |
404 | clocks = <&cru PCLK_I2C0>; | |
405 | pinctrl-names = "default"; | |
406 | pinctrl-0 = <&i2c0_xfer>; | |
407 | status = "disabled"; | |
408 | }; | |
409 | ||
410 | pinctrl: pinctrl { | |
411 | compatible = "rockchip,rk3036-pinctrl"; | |
412 | rockchip,grf = <&grf>; | |
413 | #address-cells = <1>; | |
414 | #size-cells = <1>; | |
415 | ranges; | |
416 | ||
417 | gpio0: gpio0@2007c000 { | |
418 | compatible = "rockchip,gpio-bank"; | |
419 | reg = <0x2007c000 0x100>; | |
420 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
421 | clocks = <&cru PCLK_GPIO0>; | |
422 | ||
423 | gpio-controller; | |
424 | #gpio-cells = <2>; | |
425 | ||
426 | interrupt-controller; | |
427 | #interrupt-cells = <2>; | |
428 | }; | |
429 | ||
430 | gpio1: gpio1@20080000 { | |
431 | compatible = "rockchip,gpio-bank"; | |
432 | reg = <0x20080000 0x100>; | |
433 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
434 | clocks = <&cru PCLK_GPIO1>; | |
435 | ||
436 | gpio-controller; | |
437 | #gpio-cells = <2>; | |
438 | ||
439 | interrupt-controller; | |
440 | #interrupt-cells = <2>; | |
441 | }; | |
442 | ||
443 | gpio2: gpio2@20084000 { | |
444 | compatible = "rockchip,gpio-bank"; | |
445 | reg = <0x20084000 0x100>; | |
446 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
447 | clocks = <&cru PCLK_GPIO2>; | |
448 | ||
449 | gpio-controller; | |
450 | #gpio-cells = <2>; | |
451 | ||
452 | interrupt-controller; | |
453 | #interrupt-cells = <2>; | |
454 | }; | |
455 | ||
68556dd7 XZ |
456 | pcfg_pull_default: pcfg_pull_default { |
457 | bias-pull-pin-default; | |
faea098e XZ |
458 | }; |
459 | ||
460 | pcfg_pull_none: pcfg-pull-none { | |
461 | bias-disable; | |
462 | }; | |
463 | ||
464 | pwm0 { | |
465 | pwm0_pin: pwm0-pin { | |
466 | rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; | |
467 | }; | |
468 | }; | |
469 | ||
470 | pwm1 { | |
471 | pwm1_pin: pwm1-pin { | |
472 | rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; | |
473 | }; | |
474 | }; | |
475 | ||
476 | pwm2 { | |
477 | pwm2_pin: pwm2-pin { | |
478 | rockchip,pins = <0 1 2 &pcfg_pull_none>; | |
479 | }; | |
480 | }; | |
481 | ||
482 | pwm3 { | |
483 | pwm3_pin: pwm3-pin { | |
484 | rockchip,pins = <0 27 1 &pcfg_pull_none>; | |
485 | }; | |
486 | }; | |
487 | ||
187d7967 CW |
488 | sdmmc { |
489 | sdmmc_clk: sdmmc-clk { | |
490 | rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>; | |
491 | }; | |
492 | ||
493 | sdmmc_cmd: sdmmc-cmd { | |
494 | rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>; | |
495 | }; | |
496 | ||
497 | sdmmc_cd: sdmcc-cd { | |
498 | rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>; | |
499 | }; | |
500 | ||
501 | sdmmc_bus1: sdmmc-bus1 { | |
502 | rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>; | |
503 | }; | |
504 | ||
505 | sdmmc_bus4: sdmmc-bus4 { | |
506 | rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>, | |
507 | <1 19 RK_FUNC_1 &pcfg_pull_default>, | |
508 | <1 20 RK_FUNC_1 &pcfg_pull_default>, | |
509 | <1 21 RK_FUNC_1 &pcfg_pull_default>; | |
510 | }; | |
511 | }; | |
512 | ||
513 | sdio { | |
514 | sdio_bus1: sdio-bus1 { | |
515 | rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>; | |
516 | }; | |
517 | ||
518 | sdio_bus4: sdio-bus4 { | |
519 | rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>, | |
520 | <0 12 RK_FUNC_1 &pcfg_pull_default>, | |
521 | <0 13 RK_FUNC_1 &pcfg_pull_default>, | |
522 | <0 14 RK_FUNC_1 &pcfg_pull_default>; | |
523 | }; | |
524 | ||
525 | sdio_cmd: sdio-cmd { | |
526 | rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>; | |
527 | }; | |
528 | ||
529 | sdio_clk: sdio-clk { | |
530 | rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>; | |
531 | }; | |
532 | }; | |
533 | ||
faea098e XZ |
534 | emmc { |
535 | /* | |
536 | * We run eMMC at max speed; bump up drive strength. | |
537 | * We also have external pulls, so disable the internal ones. | |
538 | */ | |
539 | emmc_clk: emmc-clk { | |
540 | rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; | |
541 | }; | |
542 | ||
543 | emmc_cmd: emmc-cmd { | |
68556dd7 | 544 | rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>; |
faea098e XZ |
545 | }; |
546 | ||
547 | emmc_bus8: emmc-bus8 { | |
68556dd7 XZ |
548 | rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>, |
549 | <1 25 RK_FUNC_2 &pcfg_pull_default>, | |
550 | <1 26 RK_FUNC_2 &pcfg_pull_default>, | |
551 | <1 27 RK_FUNC_2 &pcfg_pull_default>, | |
552 | <1 28 RK_FUNC_2 &pcfg_pull_default>, | |
553 | <1 29 RK_FUNC_2 &pcfg_pull_default>, | |
554 | <1 30 RK_FUNC_2 &pcfg_pull_default>, | |
555 | <1 31 RK_FUNC_2 &pcfg_pull_default>; | |
faea098e XZ |
556 | }; |
557 | }; | |
558 | ||
559 | i2c0 { | |
560 | i2c0_xfer: i2c0-xfer { | |
561 | rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, | |
562 | <0 1 RK_FUNC_1 &pcfg_pull_none>; | |
563 | }; | |
564 | }; | |
565 | ||
566 | i2c1 { | |
567 | i2c1_xfer: i2c1-xfer { | |
568 | rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, | |
569 | <0 3 RK_FUNC_1 &pcfg_pull_none>; | |
570 | }; | |
571 | }; | |
572 | ||
573 | i2c2 { | |
574 | i2c2_xfer: i2c2-xfer { | |
575 | rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, | |
576 | <2 21 RK_FUNC_1 &pcfg_pull_none>; | |
577 | }; | |
578 | }; | |
579 | ||
580 | i2s { | |
581 | i2s_bus: i2s-bus { | |
f4755332 CW |
582 | rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>, |
583 | <1 1 RK_FUNC_1 &pcfg_pull_default>, | |
584 | <1 2 RK_FUNC_1 &pcfg_pull_default>, | |
585 | <1 3 RK_FUNC_1 &pcfg_pull_default>, | |
586 | <1 4 RK_FUNC_1 &pcfg_pull_default>, | |
587 | <1 5 RK_FUNC_1 &pcfg_pull_default>; | |
faea098e XZ |
588 | }; |
589 | }; | |
590 | ||
591 | uart0 { | |
592 | uart0_xfer: uart0-xfer { | |
68556dd7 | 593 | rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>, |
faea098e XZ |
594 | <0 17 RK_FUNC_1 &pcfg_pull_none>; |
595 | }; | |
596 | ||
597 | uart0_cts: uart0-cts { | |
68556dd7 | 598 | rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>; |
faea098e XZ |
599 | }; |
600 | ||
601 | uart0_rts: uart0-rts { | |
602 | rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; | |
603 | }; | |
604 | }; | |
605 | ||
606 | uart1 { | |
607 | uart1_xfer: uart1-xfer { | |
68556dd7 | 608 | rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>, |
faea098e XZ |
609 | <2 23 RK_FUNC_1 &pcfg_pull_none>; |
610 | }; | |
611 | /* no rts / cts for uart1 */ | |
612 | }; | |
613 | ||
614 | uart2 { | |
615 | uart2_xfer: uart2-xfer { | |
68556dd7 | 616 | rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>, |
faea098e XZ |
617 | <1 19 RK_FUNC_2 &pcfg_pull_none>; |
618 | }; | |
619 | /* no rts / cts for uart2 */ | |
620 | }; | |
621 | }; | |
622 | }; |