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ARM: dts: rockchip: add vop device node for rk3036
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / rk3036.dtsi
CommitLineData
faea098e
XZ		 1/*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41#include <dt-bindings/gpio/gpio.h>
42#include <dt-bindings/interrupt-controller/irq.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/pinctrl/rockchip.h>
45#include <dt-bindings/clock/rk3036-cru.h>
46#include "skeleton.dtsi"
47
48/ {
49 compatible = "rockchip,rk3036";
50
51 interrupt-parent = <&gic>;
52
53 aliases {
54 i2c0 = &i2c0;
55 i2c1 = &i2c1;
56 i2c2 = &i2c2;
57 mshc0 = &emmc;
187d7967
CW		 58 mshc1 = &sdmmc;
59 mshc2 = &sdio;
faea098e
XZ		 60 serial0 = &uart0;
61 serial1 = &uart1;
62 serial2 = &uart2;
f629fcfa 63 spi = &spi;
faea098e
XZ		 64 };
65
66 memory {
67 device_type = "memory";
68 reg = <0x60000000 0x40000000>;
69 };
70
71 cpus {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 enable-method = "rockchip,rk3036-smp";
75
76 cpu0: cpu@f00 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a7";
79 reg = <0xf00>;
80 resets = <&cru SRST_CORE0>;
81 operating-points = <
82 /* KHz uV */
83 816000 1000000
84 >;
85 clock-latency = <40000>;
86 clocks = <&cru ARMCLK>;
87 };
88
89 cpu1: cpu@f01 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a7";
92 reg = <0xf01>;
93 resets = <&cru SRST_CORE1>;
94 };
95 };
96
97 amba {
2ef7d5f3 98 compatible = "simple-bus";
faea098e
XZ		 99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges;
102
103 pdma: pdma@20078000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0x20078000 0x4000>;
106 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
108 #dma-cells = <1>;
29f12bba 109 arm,pl330-broken-no-flushp;
faea098e
XZ		 110 clocks = <&cru ACLK_DMAC2>;
111 clock-names = "apb_pclk";
112 };
113 };
114
115 arm-pmu {
116 compatible = "arm,cortex-a7-pmu";
117 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-affinity = <&cpu0>, <&cpu1>;
120 };
121
d9abae3c
CW		 122 display-subsystem {
123 compatible = "rockchip,display-subsystem";
124 ports = <&vop_out>;
125 };
126
faea098e
XZ		 127 timer {
128 compatible = "arm,armv7-timer";
129 arm,cpu-registers-not-fw-configured;
130 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
131 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
132 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
133 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
134 clock-frequency = <24000000>;
135 };
136
137 xin24m: oscillator {
138 compatible = "fixed-clock";
139 clock-frequency = <24000000>;
140 clock-output-names = "xin24m";
141 #clock-cells = <0>;
142 };
143
144 bus_intmem@10080000 {
145 compatible = "mmio-sram";
146 reg = <0x10080000 0x2000>;
147 #address-cells = <1>;
148 #size-cells = <1>;
149 ranges = <0 0x10080000 0x2000>;
150
151 smp-sram@0 {
152 compatible = "rockchip,rk3066-smp-sram";
153 reg = <0x00 0x10>;
154 };
155 };
156
d9abae3c
CW		 157 vop: vop@10118000 {
158 compatible = "rockchip,rk3036-vop";
159 reg = <0x10118000 0x19c>;
160 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
162 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
163 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
164 reset-names = "axi", "ahb", "dclk";
165 iommus = <&vop_mmu>;
166 status = "disabled";
167
168 vop_out: port {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 };
172 };
173
174 vop_mmu: iommu@10118300 {
175 compatible = "rockchip,iommu";
176 reg = <0x10118300 0x100>;
177 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "vop_mmu";
179 #iommu-cells = <0>;
180 status = "disabled";
181 };
182
faea098e
XZ		 183 gic: interrupt-controller@10139000 {
184 compatible = "arm,gic-400";
185 interrupt-controller;
186 #interrupt-cells = <3>;
187 #address-cells = <0>;
188
189 reg = <0x10139000 0x1000>,
190 <0x1013a000 0x1000>,
191 <0x1013c000 0x2000>,
192 <0x1013e000 0x2000>;
193 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
194 };
195
196 usb_otg: usb@10180000 {
0082180c 197 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
faea098e
XZ		 198 "snps,dwc2";
199 reg = <0x10180000 0x40000>;
200 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&cru HCLK_OTG0>;
202 clock-names = "otg";
203 dr_mode = "otg";
204 g-np-tx-fifo-size = <16>;
205 g-rx-fifo-size = <275>;
206 g-tx-fifo-size = <256 128 128 64 64 32>;
207 g-use-dma;
208 status = "disabled";
209 };
210
211 usb_host: usb@101c0000 {
0082180c 212 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
faea098e
XZ		 213 "snps,dwc2";
214 reg = <0x101c0000 0x40000>;
215 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&cru HCLK_OTG1>;
217 clock-names = "otg";
218 dr_mode = "host";
219 status = "disabled";
220 };
221
af671e7b
XZ		 222 emac: ethernet@10200000 {
223 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
224 reg = <0x10200000 0x4000>;
225 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228 rockchip,grf = <&grf>;
229 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
230 clock-names = "hclk", "macref", "macclk";
231 /*
232 * Fix the emac parent clock is DPLL instead of APLL.
233 * since that will cause some unstable things if the cpufreq
234 * is working. (e.g: the accurate 50MHz what mac_ref need)
235 */
236 assigned-clocks = <&cru SCLK_MACPLL>;
237 assigned-clock-parents = <&cru PLL_DPLL>;
238 max-speed = <100>;
239 phy-mode = "rmii";
240 status = "disabled";
241 };
242
187d7967
CW		 243 sdmmc: dwmmc@10214000 {
244 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
245 reg = <0x10214000 0x4000>;
246 clock-frequency = <37500000>;
247 clock-freq-min-max = <400000 37500000>;
248 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
249 clock-names = "biu", "ciu";
250 fifo-depth = <0x100>;
251 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
252 status = "disabled";
253 };
254
255 sdio: dwmmc@10218000 {
256 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
257 reg = <0x10218000 0x4000>;
258 clock-freq-min-max = <400000 37500000>;
259 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
260 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
261 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
262 fifo-depth = <0x100>;
263 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
264 status = "disabled";
265 };
266
faea098e 267 emmc: dwmmc@1021c000 {
0082180c 268 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
faea098e
XZ		 269 reg = <0x1021c000 0x4000>;
270 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
271 broken-cd;
272 bus-width = <8>;
273 cap-mmc-highspeed;
274 clock-frequency = <37500000>;
275 clock-freq-min-max = <400000 37500000>;
276 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
277 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
278 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
279 default-sample-phase = <158>;
280 disable-wp;
281 dmas = <&pdma 12>;
282 dma-names = "rx-tx";
283 fifo-depth = <0x100>;
284 mmc-ddr-1_8v;
285 non-removable;
286 num-slots = <1>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
289 status = "disabled";
290 };
291
292 i2s: i2s@10220000 {
293 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
294 reg = <0x10220000 0x4000>;
295 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
296 #address-cells = <1>;
297 #size-cells = <0>;
3860aa1c
HS		 298 clock-names = "i2s_clk", "i2s_hclk";
299 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
faea098e
XZ		 300 dmas = <&pdma 0>, <&pdma 1>;
301 dma-names = "tx", "rx";
302 pinctrl-names = "default";
303 pinctrl-0 = <&i2s_bus>;
304 status = "disabled";
305 };
306
307 cru: clock-controller@20000000 {
308 compatible = "rockchip,rk3036-cru";
309 reg = <0x20000000 0x1000>;
310 rockchip,grf = <&grf>;
311 #clock-cells = <1>;
312 #reset-cells = <1>;
313 assigned-clocks = <&cru PLL_GPLL>;
314 assigned-clock-rates = <594000000>;
315 };
316
317 grf: syscon@20008000 {
318 compatible = "rockchip,rk3036-grf", "syscon";
319 reg = <0x20008000 0x1000>;
320 };
321
322 acodec: acodec-ana@20030000 {
323 compatible = "rk3036-codec";
324 reg = <0x20030000 0x4000>;
325 rockchip,grf = <&grf>;
326 clock-names = "acodec_pclk";
327 clocks = <&cru PCLK_ACODEC>;
328 status = "disabled";
329 };
330
331 timer: timer@20044000 {
332 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
333 reg = <0x20044000 0x20>;
334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&xin24m>, <&cru PCLK_TIMER>;
336 clock-names = "timer", "pclk";
337 };
338
339 pwm0: pwm@20050000 {
340 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
341 reg = <0x20050000 0x10>;
342 #pwm-cells = <3>;
343 clocks = <&cru PCLK_PWM>;
344 clock-names = "pwm";
345 pinctrl-names = "default";
346 pinctrl-0 = <&pwm0_pin>;
347 status = "disabled";
348 };
349
350 pwm1: pwm@20050010 {
351 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
352 reg = <0x20050010 0x10>;
353 #pwm-cells = <3>;
354 clocks = <&cru PCLK_PWM>;
355 clock-names = "pwm";
356 pinctrl-names = "default";
357 pinctrl-0 = <&pwm1_pin>;
358 status = "disabled";
359 };
360
361 pwm2: pwm@20050020 {
362 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
363 reg = <0x20050020 0x10>;
364 #pwm-cells = <3>;
365 clocks = <&cru PCLK_PWM>;
366 clock-names = "pwm";
367 pinctrl-names = "default";
368 pinctrl-0 = <&pwm2_pin>;
369 status = "disabled";
370 };
371
372 pwm3: pwm@20050030 {
373 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
374 reg = <0x20050030 0x10>;
375 #pwm-cells = <2>;
376 clocks = <&cru PCLK_PWM>;
377 clock-names = "pwm";
378 pinctrl-names = "default";
379 pinctrl-0 = <&pwm3_pin>;
380 status = "disabled";
381 };
382
383 i2c1: i2c@20056000 {
0082180c 384 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
faea098e
XZ		 385 reg = <0x20056000 0x1000>;
386 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 clock-names = "i2c";
390 clocks = <&cru PCLK_I2C1>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&i2c1_xfer>;
393 status = "disabled";
394 };
395
396 i2c2: i2c@2005a000 {
0082180c 397 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
faea098e
XZ		 398 reg = <0x2005a000 0x1000>;
399 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
400 #address-cells = <1>;
401 #size-cells = <0>;
402 clock-names = "i2c";
403 clocks = <&cru PCLK_I2C2>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&i2c2_xfer>;
406 status = "disabled";
407 };
408
409 uart0: serial@20060000 {
410 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
411 reg = <0x20060000 0x100>;
412 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
413 reg-shift = <2>;
414 reg-io-width = <4>;
415 clock-frequency = <24000000>;
416 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
417 clock-names = "baudclk", "apb_pclk";
418 pinctrl-names = "default";
419 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
420 status = "disabled";
421 };
422
423 uart1: serial@20064000 {
424 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
425 reg = <0x20064000 0x100>;
426 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
427 reg-shift = <2>;
428 reg-io-width = <4>;
429 clock-frequency = <24000000>;
430 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
431 clock-names = "baudclk", "apb_pclk";
432 pinctrl-names = "default";
433 pinctrl-0 = <&uart1_xfer>;
434 status = "disabled";
435 };
436
437 uart2: serial@20068000 {
438 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
439 reg = <0x20068000 0x100>;
440 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
441 reg-shift = <2>;
442 reg-io-width = <4>;
443 clock-frequency = <24000000>;
444 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
445 clock-names = "baudclk", "apb_pclk";
446 pinctrl-names = "default";
447 pinctrl-0 = <&uart2_xfer>;
448 status = "disabled";
449 };
450
451 i2c0: i2c@20072000 {
0082180c 452 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
faea098e
XZ		 453 reg = <0x20072000 0x1000>;
454 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
455 #address-cells = <1>;
456 #size-cells = <0>;
457 clock-names = "i2c";
458 clocks = <&cru PCLK_I2C0>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&i2c0_xfer>;
461 status = "disabled";
462 };
463
f629fcfa
CW		 464 spi: spi@20074000 {
465 compatible = "rockchip,rockchip-spi";
466 reg = <0x20074000 0x1000>;
467 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
468 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
469 clock-names = "apb-pclk","spi_pclk";
470 dmas = <&pdma 8>, <&pdma 9>;
471 dma-names = "tx", "rx";
472 pinctrl-names = "default";
473 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 status = "disabled";
477 };
478
faea098e
XZ		 479 pinctrl: pinctrl {
480 compatible = "rockchip,rk3036-pinctrl";
481 rockchip,grf = <&grf>;
482 #address-cells = <1>;
483 #size-cells = <1>;
484 ranges;
485
486 gpio0: gpio0@2007c000 {
487 compatible = "rockchip,gpio-bank";
488 reg = <0x2007c000 0x100>;
489 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&cru PCLK_GPIO0>;
491
492 gpio-controller;
493 #gpio-cells = <2>;
494
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 };
498
499 gpio1: gpio1@20080000 {
500 compatible = "rockchip,gpio-bank";
501 reg = <0x20080000 0x100>;
502 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru PCLK_GPIO1>;
504
505 gpio-controller;
506 #gpio-cells = <2>;
507
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 };
511
512 gpio2: gpio2@20084000 {
513 compatible = "rockchip,gpio-bank";
514 reg = <0x20084000 0x100>;
515 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&cru PCLK_GPIO2>;
517
518 gpio-controller;
519 #gpio-cells = <2>;
520
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 };
524
68556dd7
XZ		 525 pcfg_pull_default: pcfg_pull_default {
526 bias-pull-pin-default;
faea098e
XZ		 527 };
528
529 pcfg_pull_none: pcfg-pull-none {
530 bias-disable;
531 };
532
533 pwm0 {
534 pwm0_pin: pwm0-pin {
535 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
536 };
537 };
538
539 pwm1 {
540 pwm1_pin: pwm1-pin {
541 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
542 };
543 };
544
545 pwm2 {
546 pwm2_pin: pwm2-pin {
547 rockchip,pins = <0 1 2 &pcfg_pull_none>;
548 };
549 };
550
551 pwm3 {
552 pwm3_pin: pwm3-pin {
553 rockchip,pins = <0 27 1 &pcfg_pull_none>;
554 };
555 };
556
187d7967
CW		 557 sdmmc {
558 sdmmc_clk: sdmmc-clk {
559 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
560 };
561
562 sdmmc_cmd: sdmmc-cmd {
563 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
564 };
565
566 sdmmc_cd: sdmcc-cd {
567 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
568 };
569
570 sdmmc_bus1: sdmmc-bus1 {
571 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
572 };
573
574 sdmmc_bus4: sdmmc-bus4 {
575 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
576 <1 19 RK_FUNC_1 &pcfg_pull_default>,
577 <1 20 RK_FUNC_1 &pcfg_pull_default>,
578 <1 21 RK_FUNC_1 &pcfg_pull_default>;
579 };
580 };
581
582 sdio {
583 sdio_bus1: sdio-bus1 {
584 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
585 };
586
587 sdio_bus4: sdio-bus4 {
588 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
589 <0 12 RK_FUNC_1 &pcfg_pull_default>,
590 <0 13 RK_FUNC_1 &pcfg_pull_default>,
591 <0 14 RK_FUNC_1 &pcfg_pull_default>;
592 };
593
594 sdio_cmd: sdio-cmd {
595 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
596 };
597
598 sdio_clk: sdio-clk {
599 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
600 };
601 };
602
faea098e
XZ		 603 emmc {
604 /*
605 * We run eMMC at max speed; bump up drive strength.
606 * We also have external pulls, so disable the internal ones.
607 */
608 emmc_clk: emmc-clk {
609 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
610 };
611
612 emmc_cmd: emmc-cmd {
68556dd7 613 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
faea098e
XZ		 614 };
615
616 emmc_bus8: emmc-bus8 {
68556dd7
XZ		 617 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
618 <1 25 RK_FUNC_2 &pcfg_pull_default>,
619 <1 26 RK_FUNC_2 &pcfg_pull_default>,
620 <1 27 RK_FUNC_2 &pcfg_pull_default>,
621 <1 28 RK_FUNC_2 &pcfg_pull_default>,
622 <1 29 RK_FUNC_2 &pcfg_pull_default>,
623 <1 30 RK_FUNC_2 &pcfg_pull_default>,
624 <1 31 RK_FUNC_2 &pcfg_pull_default>;
faea098e
XZ		 625 };
626 };
627
af671e7b
XZ		 628 emac {
629 emac_xfer: emac-xfer {
630 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
631 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
632 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
633 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
634 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
635 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
636 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
637 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
638 };
639
640 emac_mdio: emac-mdio {
641 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
642 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
643 };
644 };
645
faea098e
XZ		 646 i2c0 {
647 i2c0_xfer: i2c0-xfer {
648 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
649 <0 1 RK_FUNC_1 &pcfg_pull_none>;
650 };
651 };
652
653 i2c1 {
654 i2c1_xfer: i2c1-xfer {
655 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
656 <0 3 RK_FUNC_1 &pcfg_pull_none>;
657 };
658 };
659
660 i2c2 {
661 i2c2_xfer: i2c2-xfer {
662 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
663 <2 21 RK_FUNC_1 &pcfg_pull_none>;
664 };
665 };
666
667 i2s {
668 i2s_bus: i2s-bus {
f4755332
CW		 669 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
670 <1 1 RK_FUNC_1 &pcfg_pull_default>,
671 <1 2 RK_FUNC_1 &pcfg_pull_default>,
672 <1 3 RK_FUNC_1 &pcfg_pull_default>,
673 <1 4 RK_FUNC_1 &pcfg_pull_default>,
674 <1 5 RK_FUNC_1 &pcfg_pull_default>;
faea098e
XZ		 675 };
676 };
677
678 uart0 {
679 uart0_xfer: uart0-xfer {
68556dd7 680 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
faea098e
XZ		 681 <0 17 RK_FUNC_1 &pcfg_pull_none>;
682 };
683
684 uart0_cts: uart0-cts {
68556dd7 685 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
faea098e
XZ		 686 };
687
688 uart0_rts: uart0-rts {
689 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
690 };
691 };
692
693 uart1 {
694 uart1_xfer: uart1-xfer {
68556dd7 695 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
faea098e
XZ		 696 <2 23 RK_FUNC_1 &pcfg_pull_none>;
697 };
698 /* no rts / cts for uart1 */
699 };
700
701 uart2 {
702 uart2_xfer: uart2-xfer {
68556dd7 703 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
faea098e
XZ		 704 <1 19 RK_FUNC_2 &pcfg_pull_none>;
705 };
706 /* no rts / cts for uart2 */
707 };
f629fcfa
CW		 708
709 spi {
710 spi_txd:spi-txd {
711 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
712 };
713
714 spi_rxd:spi-rxd {
715 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
716 };
717
718 spi_clk:spi-clk {
719 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
720 };
721
722 spi_cs0:spi-cs0 {
723 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
724
725 };
726
727 spi_cs1:spi-cs1 {
728 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
729
730 };
731 };
faea098e
XZ		 732 };
733};
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