[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / rk3066a.dtsi

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3066a-cru.h>
#include "rk3xxx.dtsi"

/ {
	compatible = "rockchip,rk3066a";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
			operating-points = <
				/* kHz    uV */
				1008000 1075000
				 816000 1025000
				 600000 1025000
				 504000 1000000
				 312000  975000
			>;
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x10000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x0 0x50>;
		};
	};

	i2s0: i2s@10118000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x10118000 0x2000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_bus>;
		dmas = <&dmac1_s 4>, <&dmac1_s 5>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
		status = "disabled";
	};

	i2s1: i2s@1011a000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x1011a000 0x2000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1_bus>;
		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
		status = "disabled";
	};

	i2s2: i2s@1011c000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x1011c000 0x2000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s2_bus>;
		dmas = <&dmac1_s 9>, <&dmac1_s 10>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
		status = "disabled";
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3066a-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	timer@2000e000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2000e000 0x100>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
		clock-names = "timer", "pclk";
	};

	timer@20038000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x20038000 0x100>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
		clock-names = "timer", "pclk";
	};

	timer@2003a000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2003a000 0x100>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
		clock-names = "timer", "pclk";
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3066a-pinctrl";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@20034000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20034000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@2003c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003c000 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@2003e000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003e000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio4@20084000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20084000 0x100>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio6@2000a000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2000a000 0x100>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO6>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_default: pcfg_pull_default {
			bias-pull-pin-default;
		};

		pcfg_pull_none: pcfg_pull_none {
			bias-disable;
		};

		emac {
			emac_xfer: emac-xfer {
				rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
						<RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
						<RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
						<RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
						<RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
						<RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
						<RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
						<RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
			};

			emac_mdio: emac-mdio {
				rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
						<RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
			};
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_rst: emmc-rst {
				rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
			};

			/*
			 * The data pins are shared between nandc and emmc and
			 * not accessible through pinctrl. Also they should've
			 * been already set correctly by firmware, as
			 * flash/emmc is the boot-device.
			 */
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c4 {
			i2c4_xfer: i2c4-xfer {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_out: pwm0-out {
				rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_out: pwm1-out {
				rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_out: pwm2-out {
				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_out: pwm3-out {
				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0_clk: spi0-clk {
				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_cs0: spi0-cs0 {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_tx: spi0-tx {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_rx: spi0-rx {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_cs1: spi0-cs1 {
				rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		spi1 {
			spi1_clk: spi1-clk {
				rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_cs0: spi1-cs0 {
				rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_rx: spi1-rx {
				rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_tx: spi1-tx {
				rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_cs1: spi1-cs1 {
				rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
			};
			/* no rts / cts for uart2 */
		};

		uart3 {
			uart3_xfer: uart3-xfer {
				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_cts: uart3-cts {
				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_rts: uart3-rts {
				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd0 {
			sd0_clk: sd0-clk {
				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cmd: sd0-cmd {
				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cd: sd0-cd {
				rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_wp: sd0-wp {
				rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus1: sd0-bus-width1 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus4: sd0-bus-width4 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd1 {
			sd1_clk: sd1-clk {
				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cmd: sd1-cmd {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cd: sd1-cd {
				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_wp: sd1-wp {
				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus1: sd1-bus-width1 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus4: sd1-bus-width4 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s0 {
			i2s0_bus: i2s0-bus {
				rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s1 {
			i2s1_bus: i2s1-bus {
				rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s2 {
			i2s2_bus: i2s2-bus {
				rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
			};
		};
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
};

&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_out>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_out>;
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_out>;
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_out>;
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
};

&wdt {
	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
};

&emac {
	compatible = "rockchip,rk3066-emac";
};
Commit	Line	Data
d63dc051 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
5218c6bc HS	5	* This file is dual-licensed: you can use it either under the terms
	6	* of the GPL or the X11 license, at your option. Note that this dual
	7	* licensing only applies to this file, and not this project as a
	8	* whole.
d63dc051	9	*
5218c6bc HS	10	* a) This file is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of the
	13	* License, or (at your option) any later version.
	14	*
	15	* This file is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* Or, alternatively,
	21	*
	22	* b) Permission is hereby granted, free of charge, to any person
	23	* obtaining a copy of this software and associated documentation
	24	* files (the "Software"), to deal in the Software without
	25	* restriction, including without limitation the rights to use,
	26	* copy, modify, merge, publish, distribute, sublicense, and/or
	27	* sell copies of the Software, and to permit persons to whom the
	28	* Software is furnished to do so, subject to the following
	29	* conditions:
	30	*
	31	* The above copyright notice and this permission notice shall be
	32	* included in all copies or substantial portions of the Software.
	33	*
	34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	35	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	36	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	37	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	38	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	39	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	40	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	41	* OTHER DEALINGS IN THE SOFTWARE.
d63dc051 HS	42	*/
	43
	44	#include <dt-bindings/gpio/gpio.h>
d63dc051	45	#include <dt-bindings/pinctrl/rockchip.h>
b13d2a7b	46	#include <dt-bindings/clock/rk3066a-cru.h>
f75efdd7	47	#include "rk3xxx.dtsi"
d63dc051 HS	48
	49	/ {
	50	compatible = "rockchip,rk3066a";
d63dc051 HS	51
	52	cpus {
	53	#address-cells = <1>;
	54	#size-cells = <0>;
26ab69cb	55	enable-method = "rockchip,rk3066-smp";
d63dc051	56
be8a77c5	57	cpu0: cpu@0 {
d63dc051 HS	58	device_type = "cpu";
	59	compatible = "arm,cortex-a9";
	60	next-level-cache = <&L2>;
	61	reg = <0x0>;
be8a77c5 HS	62	operating-points = <
	63	/* kHz uV */
	64	1008000 1075000
	65	816000 1025000
	66	600000 1025000
	67	504000 1000000
	68	312000 975000
	69	>;
	70	clock-latency = <40000>;
	71	clocks = <&cru ARMCLK>;
d63dc051 HS	72	};
	73	cpu@1 {
	74	device_type = "cpu";
	75	compatible = "arm,cortex-a9";
	76	next-level-cache = <&L2>;
	77	reg = <0x1>;
	78	};
	79	};
	80
c3030d30 HS	81	sram: sram@10080000 {
	82	compatible = "mmio-sram";
	83	reg = <0x10080000 0x10000>;
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	ranges = <0 0x10080000 0x10000>;
	87
	88	smp-sram@0 {
	89	compatible = "rockchip,rk3066-smp-sram";
	90	reg = <0x0 0x50>;
d63dc051	91	};
c3030d30 HS	92	};
c3030d30 HS	93
5fe62b83 JC	94	i2s0: i2s@10118000 {
	95	compatible = "rockchip,rk3066-i2s";
	96	reg = <0x10118000 0x2000>;
	97	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	98	#address-cells = <1>;
	99	#size-cells = <0>;
	100	pinctrl-names = "default";
	101	pinctrl-0 = <&i2s0_bus>;
	102	dmas = <&dmac1_s 4>, <&dmac1_s 5>;
	103	dma-names = "tx", "rx";
	104	clock-names = "i2s_hclk", "i2s_clk";
	105	clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
	106	status = "disabled";
	107	};
	108
	109	i2s1: i2s@1011a000 {
	110	compatible = "rockchip,rk3066-i2s";
	111	reg = <0x1011a000 0x2000>;
	112	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	113	#address-cells = <1>;
	114	#size-cells = <0>;
	115	pinctrl-names = "default";
	116	pinctrl-0 = <&i2s1_bus>;
	117	dmas = <&dmac1_s 6>, <&dmac1_s 7>;
	118	dma-names = "tx", "rx";
	119	clock-names = "i2s_hclk", "i2s_clk";
	120	clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
	121	status = "disabled";
	122	};
	123
	124	i2s2: i2s@1011c000 {
	125	compatible = "rockchip,rk3066-i2s";
	126	reg = <0x1011c000 0x2000>;
	127	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	128	#address-cells = <1>;
	129	#size-cells = <0>;
	130	pinctrl-names = "default";
	131	pinctrl-0 = <&i2s2_bus>;
	132	dmas = <&dmac1_s 9>, <&dmac1_s 10>;
	133	dma-names = "tx", "rx";
	134	clock-names = "i2s_hclk", "i2s_clk";
	135	clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
	136	status = "disabled";
	137	};
	138
c3030d30 HS	139	cru: clock-controller@20000000 {
	140	compatible = "rockchip,rk3066a-cru";
	141	reg = <0x20000000 0x1000>;
	142	rockchip,grf = <&grf>;
	143
	144	#clock-cells = <1>;
	145	#reset-cells = <1>;
	146	};
	147
ff84b90e HS	148	timer@2000e000 {
	149	compatible = "snps,dw-apb-timer-osc";
	150	reg = <0x2000e000 0x100>;
	151	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	152	clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
	153	clock-names = "timer", "pclk";
	154	};
	155
	156	timer@20038000 {
	157	compatible = "snps,dw-apb-timer-osc";
	158	reg = <0x20038000 0x100>;
	159	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	160	clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
	161	clock-names = "timer", "pclk";
	162	};
	163
	164	timer@2003a000 {
	165	compatible = "snps,dw-apb-timer-osc";
	166	reg = <0x2003a000 0x100>;
	167	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	168	clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
	169	clock-names = "timer", "pclk";
	170	};
	171
6e4b3b4b	172	pinctrl: pinctrl {
c3030d30 HS	173	compatible = "rockchip,rk3066a-pinctrl";
	174	rockchip,grf = <&grf>;
	175	#address-cells = <1>;
	176	#size-cells = <1>;
	177	ranges;
d63dc051	178
c3030d30 HS	179	gpio0: gpio0@20034000 {
	180	compatible = "rockchip,gpio-bank";
	181	reg = <0x20034000 0x100>;
	182	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	183	clocks = <&cru PCLK_GPIO0>;
	184
	185	gpio-controller;
	186	#gpio-cells = <2>;
	187
	188	interrupt-controller;
	189	#interrupt-cells = <2>;
d63dc051 HS	190	};
d63dc051 HS	191
c3030d30 HS	192	gpio1: gpio1@2003c000 {
	193	compatible = "rockchip,gpio-bank";
	194	reg = <0x2003c000 0x100>;
	195	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	196	clocks = <&cru PCLK_GPIO1>;
de18e014	197
c3030d30 HS	198	gpio-controller;
	199	#gpio-cells = <2>;
	200
	201	interrupt-controller;
	202	#interrupt-cells = <2>;
de18e014 HS	203	};
de18e014 HS	204
c3030d30 HS	205	gpio2: gpio2@2003e000 {
	206	compatible = "rockchip,gpio-bank";
	207	reg = <0x2003e000 0x100>;
	208	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	209	clocks = <&cru PCLK_GPIO2>;
	210
	211	gpio-controller;
	212	#gpio-cells = <2>;
b13d2a7b	213
c3030d30 HS	214	interrupt-controller;
c3030d30 HS	215	#interrupt-cells = <2>;
b13d2a7b HS	216	};
b13d2a7b HS	217
c3030d30 HS	218	gpio3: gpio3@20080000 {
	219	compatible = "rockchip,gpio-bank";
	220	reg = <0x20080000 0x100>;
	221	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	222	clocks = <&cru PCLK_GPIO3>;
d63dc051	223
c3030d30 HS	224	gpio-controller;
c3030d30 HS	225	#gpio-cells = <2>;
d63dc051	226
c3030d30 HS	227	interrupt-controller;
	228	#interrupt-cells = <2>;
	229	};
d63dc051	230
c3030d30 HS	231	gpio4: gpio4@20084000 {
	232	compatible = "rockchip,gpio-bank";
	233	reg = <0x20084000 0x100>;
	234	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	235	clocks = <&cru PCLK_GPIO4>;
d63dc051	236
c3030d30 HS	237	gpio-controller;
c3030d30 HS	238	#gpio-cells = <2>;
d63dc051	239
c3030d30 HS	240	interrupt-controller;
	241	#interrupt-cells = <2>;
	242	};
d63dc051	243
c3030d30 HS	244	gpio6: gpio6@2000a000 {
	245	compatible = "rockchip,gpio-bank";
	246	reg = <0x2000a000 0x100>;
	247	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	248	clocks = <&cru PCLK_GPIO6>;
d63dc051	249
c3030d30 HS	250	gpio-controller;
c3030d30 HS	251	#gpio-cells = <2>;
d63dc051	252
c3030d30 HS	253	interrupt-controller;
	254	#interrupt-cells = <2>;
	255	};
d63dc051	256
c3030d30 HS	257	pcfg_pull_default: pcfg_pull_default {
	258	bias-pull-pin-default;
	259	};
d63dc051	260
c3030d30 HS	261	pcfg_pull_none: pcfg_pull_none {
	262	bias-disable;
	263	};
d63dc051	264
89f66876 RP	265	emac {
	266	emac_xfer: emac-xfer {
	267	rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
	268	<RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
	269	<RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
	270	<RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
	271	<RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
	272	<RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
	273	<RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
	274	<RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
	275	};
	276
	277	emac_mdio: emac-mdio {
	278	rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
	279	<RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
	280	};
	281	};
	282
4ff4ae12 HS	283	emmc {
	284	emmc_clk: emmc-clk {
	285	rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
	286	};
	287
	288	emmc_cmd: emmc-cmd {
	289	rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
	290	};
	291
	292	emmc_rst: emmc-rst {
	293	rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
	294	};
	295
	296	/*
	297	* The data pins are shared between nandc and emmc and
	298	* not accessible through pinctrl. Also they should've
	299	* been already set correctly by firmware, as
	300	* flash/emmc is the boot-device.
	301	*/
	302	};
	303
9cdffd8c HS	304	i2c0 {
	305	i2c0_xfer: i2c0-xfer {
	306	rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
	307	<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
	308	};
	309	};
	310
	311	i2c1 {
	312	i2c1_xfer: i2c1-xfer {
	313	rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
	314	<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
	315	};
	316	};
	317
	318	i2c2 {
	319	i2c2_xfer: i2c2-xfer {
	320	rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
	321	<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
	322	};
	323	};
	324
	325	i2c3 {
	326	i2c3_xfer: i2c3-xfer {
	327	rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
	328	<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
	329	};
	330	};
	331
	332	i2c4 {
	333	i2c4_xfer: i2c4-xfer {
	334	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
	335	<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
	336	};
	337	};
	338
550c7f4e BG	339	pwm0 {
	340	pwm0_out: pwm0-out {
	341	rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
	342	};
	343	};
	344
	345	pwm1 {
	346	pwm1_out: pwm1-out {
	347	rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
	348	};
	349	};
	350
	351	pwm2 {
	352	pwm2_out: pwm2-out {
	353	rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
	354	};
	355	};
	356
	357	pwm3 {
	358	pwm3_out: pwm3-out {
	359	rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
	360	};
	361	};
	362
39c2bd78 HS	363	spi0 {
	364	spi0_clk: spi0-clk {
	365	rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
	366	};
	367	spi0_cs0: spi0-cs0 {
	368	rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
	369	};
	370	spi0_tx: spi0-tx {
	371	rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
	372	};
	373	spi0_rx: spi0-rx {
	374	rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
	375	};
	376	spi0_cs1: spi0-cs1 {
	377	rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
	378	};
	379	};
	380
	381	spi1 {
	382	spi1_clk: spi1-clk {
	383	rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
	384	};
	385	spi1_cs0: spi1-cs0 {
	386	rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
	387	};
	388	spi1_rx: spi1-rx {
	389	rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
	390	};
	391	spi1_tx: spi1-tx {
	392	rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
	393	};
	394	spi1_cs1: spi1-cs1 {
	395	rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
	396	};
	397	};
	398
c3030d30 HS	399	uart0 {
	400	uart0_xfer: uart0-xfer {
	401	rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
	402	<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
	403	};
d63dc051	404
c3030d30 HS	405	uart0_cts: uart0-cts {
c3030d30 HS	406	rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	407	};
d63dc051 HS	408
c3030d30 HS	409	uart0_rts: uart0-rts {
	410	rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
	411	};
	412	};
d63dc051	413
c3030d30 HS	414	uart1 {
	415	uart1_xfer: uart1-xfer {
	416	rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
	417	<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
	418	};
d63dc051	419
c3030d30 HS	420	uart1_cts: uart1-cts {
c3030d30 HS	421	rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	422	};
d63dc051 HS	423
c3030d30 HS	424	uart1_rts: uart1-rts {
	425	rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
	426	};
	427	};
d63dc051	428
c3030d30 HS	429	uart2 {
	430	uart2_xfer: uart2-xfer {
	431	rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
	432	<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
	433	};
	434	/* no rts / cts for uart2 */
	435	};
d63dc051	436
c3030d30 HS	437	uart3 {
	438	uart3_xfer: uart3-xfer {
	439	rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
	440	<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	441	};
d63dc051 HS	442
c3030d30 HS	443	uart3_cts: uart3-cts {
c3030d30 HS	444	rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	445	};
d63dc051 HS	446
c3030d30 HS	447	uart3_rts: uart3-rts {
c3030d30 HS	448	rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
d63dc051	449	};
c3030d30	450	};
d63dc051	451
c3030d30 HS	452	sd0 {
	453	sd0_clk: sd0-clk {
	454	rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
	455	};
d63dc051	456
c3030d30 HS	457	sd0_cmd: sd0-cmd {
	458	rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
	459	};
d63dc051	460
c3030d30 HS	461	sd0_cd: sd0-cd {
c3030d30 HS	462	rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	463	};
d63dc051 HS	464
c3030d30 HS	465	sd0_wp: sd0-wp {
	466	rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
	467	};
d63dc051	468
c3030d30 HS	469	sd0_bus1: sd0-bus-width1 {
	470	rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
	471	};
d63dc051	472
c3030d30 HS	473	sd0_bus4: sd0-bus-width4 {
	474	rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
	475	<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
	476	<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
	477	<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
d63dc051	478	};
c3030d30	479	};
d63dc051	480
c3030d30 HS	481	sd1 {
	482	sd1_clk: sd1-clk {
	483	rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	484	};
d63dc051 HS	485
c3030d30 HS	486	sd1_cmd: sd1-cmd {
	487	rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
	488	};
d63dc051	489
c3030d30 HS	490	sd1_cd: sd1-cd {
	491	rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
	492	};
d63dc051	493
c3030d30 HS	494	sd1_wp: sd1-wp {
c3030d30 HS	495	rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	496	};
d63dc051 HS	497
c3030d30 HS	498	sd1_bus1: sd1-bus-width1 {
c3030d30 HS	499	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	500	};
d63dc051 HS	501
c3030d30 HS	502	sd1_bus4: sd1-bus-width4 {
	503	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
	504	<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
	505	<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
	506	<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	507	};
d63dc051 HS	508	};
5fe62b83 JC	509
	510	i2s0 {
	511	i2s0_bus: i2s0-bus {
	512	rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
	513	<RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
	514	<RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
	515	<RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
	516	<RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
	517	<RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
	518	<RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
	519	<RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
	520	<RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
	521	};
	522	};
	523
	524	i2s1 {
	525	i2s1_bus: i2s1-bus {
	526	rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
	527	<RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
	528	<RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
	529	<RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
	530	<RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
	531	<RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
	532	};
	533	};
	534
	535	i2s2 {
	536	i2s2_bus: i2s2-bus {
	537	rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
	538	<RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
	539	<RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
	540	<RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
	541	<RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
	542	<RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
	543	};
	544	};
d63dc051 HS	545	};
d63dc051 HS	546	};
fcbbf965	547
9cdffd8c HS	548	&i2c0 {
	549	pinctrl-names = "default";
	550	pinctrl-0 = <&i2c0_xfer>;
	551	};
	552
	553	&i2c1 {
	554	pinctrl-names = "default";
	555	pinctrl-0 = <&i2c1_xfer>;
	556	};
	557
	558	&i2c2 {
	559	pinctrl-names = "default";
	560	pinctrl-0 = <&i2c2_xfer>;
	561	};
	562
	563	&i2c3 {
	564	pinctrl-names = "default";
	565	pinctrl-0 = <&i2c3_xfer>;
	566	};
	567
	568	&i2c4 {
	569	pinctrl-names = "default";
	570	pinctrl-0 = <&i2c4_xfer>;
	571	};
	572
fcbbf965 HS	573	&mmc0 {
	574	pinctrl-names = "default";
	575	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
	576	};
	577
	578	&mmc1 {
	579	pinctrl-names = "default";
	580	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
	581	};
	582
550c7f4e BG	583	&pwm0 {
	584	pinctrl-names = "default";
	585	pinctrl-0 = <&pwm0_out>;
	586	};
	587
	588	&pwm1 {
	589	pinctrl-names = "default";
	590	pinctrl-0 = <&pwm1_out>;
	591	};
	592
	593	&pwm2 {
	594	pinctrl-names = "default";
	595	pinctrl-0 = <&pwm2_out>;
	596	};
	597
	598	&pwm3 {
	599	pinctrl-names = "default";
	600	pinctrl-0 = <&pwm3_out>;
	601	};
	602
39c2bd78 HS	603	&spi0 {
	604	pinctrl-names = "default";
	605	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	606	};
	607
	608	&spi1 {
	609	pinctrl-names = "default";
	610	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	611	};
	612
fcbbf965 HS	613	&uart0 {
	614	pinctrl-names = "default";
	615	pinctrl-0 = <&uart0_xfer>;
	616	};
	617
	618	&uart1 {
	619	pinctrl-names = "default";
	620	pinctrl-0 = <&uart1_xfer>;
	621	};
	622
	623	&uart2 {
	624	pinctrl-names = "default";
	625	pinctrl-0 = <&uart2_xfer>;
	626	};
	627
	628	&uart3 {
	629	pinctrl-names = "default";
	630	pinctrl-0 = <&uart3_xfer>;
	631	};
eb2b9d47 HS	632
	633	&wdt {
	634	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
	635	};
89f66876 RP	636
	637	&emac {
	638	compatible = "rockchip,rk3066-emac";
	639	};