[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / rk3066a.dtsi

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3066a-cru.h>
#include "rk3xxx.dtsi"

/ {
	compatible = "rockchip,rk3066a";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
			operating-points = <
				/* kHz    uV */
				1008000 1075000
				 816000 1025000
				 600000 1025000
				 504000 1000000
				 312000  975000
			>;
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x10000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x0 0x50>;
		};
	};

	i2s0: i2s@10118000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x10118000 0x2000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_bus>;
		dmas = <&dmac1_s 4>, <&dmac1_s 5>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
		status = "disabled";
	};

	i2s1: i2s@1011a000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x1011a000 0x2000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1_bus>;
		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
		status = "disabled";
	};

	i2s2: i2s@1011c000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x1011c000 0x2000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s2_bus>;
		dmas = <&dmac1_s 9>, <&dmac1_s 10>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
		status = "disabled";
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3066a-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	timer@2000e000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2000e000 0x100>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
		clock-names = "timer", "pclk";
	};

	timer@20038000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x20038000 0x100>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
		clock-names = "timer", "pclk";
	};

	timer@2003a000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2003a000 0x100>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
		clock-names = "timer", "pclk";
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3066a-pinctrl";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@20034000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20034000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@2003c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003c000 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@2003e000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003e000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio4@20084000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20084000 0x100>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio6@2000a000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2000a000 0x100>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO6>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_default: pcfg_pull_default {
			bias-pull-pin-default;
		};

		pcfg_pull_none: pcfg_pull_none {
			bias-disable;
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_rst: emmc-rst {
				rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
			};

			/*
			 * The data pins are shared between nandc and emmc and
			 * not accessible through pinctrl. Also they should've
			 * been already set correctly by firmware, as
			 * flash/emmc is the boot-device.
			 */
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c4 {
			i2c4_xfer: i2c4-xfer {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_out: pwm0-out {
				rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_out: pwm1-out {
				rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_out: pwm2-out {
				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_out: pwm3-out {
				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0_clk: spi0-clk {
				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_cs0: spi0-cs0 {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_tx: spi0-tx {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_rx: spi0-rx {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_cs1: spi0-cs1 {
				rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		spi1 {
			spi1_clk: spi1-clk {
				rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_cs0: spi1-cs0 {
				rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_rx: spi1-rx {
				rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_tx: spi1-tx {
				rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_cs1: spi1-cs1 {
				rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
			};
			/* no rts / cts for uart2 */
		};

		uart3 {
			uart3_xfer: uart3-xfer {
				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_cts: uart3-cts {
				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_rts: uart3-rts {
				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd0 {
			sd0_clk: sd0-clk {
				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cmd: sd0-cmd {
				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cd: sd0-cd {
				rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_wp: sd0-wp {
				rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus1: sd0-bus-width1 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus4: sd0-bus-width4 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd1 {
			sd1_clk: sd1-clk {
				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cmd: sd1-cmd {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cd: sd1-cd {
				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_wp: sd1-wp {
				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus1: sd1-bus-width1 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus4: sd1-bus-width4 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s0 {
			i2s0_bus: i2s0-bus {
				rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s1 {
			i2s1_bus: i2s1-bus {
				rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s2 {
			i2s2_bus: i2s2-bus {
				rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
			};
		};
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
};

&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_out>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_out>;
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_out>;
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_out>;
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
};

&wdt {
	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
};
Commit	Line	Data
d63dc051 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <dt-bindings/gpio/gpio.h>
d63dc051	17	#include <dt-bindings/pinctrl/rockchip.h>
b13d2a7b	18	#include <dt-bindings/clock/rk3066a-cru.h>
f75efdd7	19	#include "rk3xxx.dtsi"
d63dc051 HS	20
	21	/ {
	22	compatible = "rockchip,rk3066a";
d63dc051 HS	23
	24	cpus {
	25	#address-cells = <1>;
	26	#size-cells = <0>;
26ab69cb	27	enable-method = "rockchip,rk3066-smp";
d63dc051	28
be8a77c5	29	cpu0: cpu@0 {
d63dc051 HS	30	device_type = "cpu";
	31	compatible = "arm,cortex-a9";
	32	next-level-cache = <&L2>;
	33	reg = <0x0>;
be8a77c5 HS	34	operating-points = <
	35	/* kHz uV */
	36	1008000 1075000
	37	816000 1025000
	38	600000 1025000
	39	504000 1000000
	40	312000 975000
	41	>;
	42	clock-latency = <40000>;
	43	clocks = <&cru ARMCLK>;
d63dc051 HS	44	};
	45	cpu@1 {
	46	device_type = "cpu";
	47	compatible = "arm,cortex-a9";
	48	next-level-cache = <&L2>;
	49	reg = <0x1>;
	50	};
	51	};
	52
c3030d30 HS	53	sram: sram@10080000 {
	54	compatible = "mmio-sram";
	55	reg = <0x10080000 0x10000>;
	56	#address-cells = <1>;
	57	#size-cells = <1>;
	58	ranges = <0 0x10080000 0x10000>;
	59
	60	smp-sram@0 {
	61	compatible = "rockchip,rk3066-smp-sram";
	62	reg = <0x0 0x50>;
d63dc051	63	};
c3030d30 HS	64	};
c3030d30 HS	65
5fe62b83 JC	66	i2s0: i2s@10118000 {
	67	compatible = "rockchip,rk3066-i2s";
	68	reg = <0x10118000 0x2000>;
	69	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	70	#address-cells = <1>;
	71	#size-cells = <0>;
	72	pinctrl-names = "default";
	73	pinctrl-0 = <&i2s0_bus>;
	74	dmas = <&dmac1_s 4>, <&dmac1_s 5>;
	75	dma-names = "tx", "rx";
	76	clock-names = "i2s_hclk", "i2s_clk";
	77	clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
	78	status = "disabled";
	79	};
	80
	81	i2s1: i2s@1011a000 {
	82	compatible = "rockchip,rk3066-i2s";
	83	reg = <0x1011a000 0x2000>;
	84	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	85	#address-cells = <1>;
	86	#size-cells = <0>;
	87	pinctrl-names = "default";
	88	pinctrl-0 = <&i2s1_bus>;
	89	dmas = <&dmac1_s 6>, <&dmac1_s 7>;
	90	dma-names = "tx", "rx";
	91	clock-names = "i2s_hclk", "i2s_clk";
	92	clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
	93	status = "disabled";
	94	};
	95
	96	i2s2: i2s@1011c000 {
	97	compatible = "rockchip,rk3066-i2s";
	98	reg = <0x1011c000 0x2000>;
	99	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	100	#address-cells = <1>;
	101	#size-cells = <0>;
	102	pinctrl-names = "default";
	103	pinctrl-0 = <&i2s2_bus>;
	104	dmas = <&dmac1_s 9>, <&dmac1_s 10>;
	105	dma-names = "tx", "rx";
	106	clock-names = "i2s_hclk", "i2s_clk";
	107	clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
	108	status = "disabled";
	109	};
	110
c3030d30 HS	111	cru: clock-controller@20000000 {
	112	compatible = "rockchip,rk3066a-cru";
	113	reg = <0x20000000 0x1000>;
	114	rockchip,grf = <&grf>;
	115
	116	#clock-cells = <1>;
	117	#reset-cells = <1>;
	118	};
	119
ff84b90e HS	120	timer@2000e000 {
	121	compatible = "snps,dw-apb-timer-osc";
	122	reg = <0x2000e000 0x100>;
	123	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	124	clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
	125	clock-names = "timer", "pclk";
	126	};
	127
	128	timer@20038000 {
	129	compatible = "snps,dw-apb-timer-osc";
	130	reg = <0x20038000 0x100>;
	131	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	132	clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
	133	clock-names = "timer", "pclk";
	134	};
	135
	136	timer@2003a000 {
	137	compatible = "snps,dw-apb-timer-osc";
	138	reg = <0x2003a000 0x100>;
	139	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	140	clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
	141	clock-names = "timer", "pclk";
	142	};
	143
6e4b3b4b	144	pinctrl: pinctrl {
c3030d30 HS	145	compatible = "rockchip,rk3066a-pinctrl";
	146	rockchip,grf = <&grf>;
	147	#address-cells = <1>;
	148	#size-cells = <1>;
	149	ranges;
d63dc051	150
c3030d30 HS	151	gpio0: gpio0@20034000 {
	152	compatible = "rockchip,gpio-bank";
	153	reg = <0x20034000 0x100>;
	154	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	155	clocks = <&cru PCLK_GPIO0>;
	156
	157	gpio-controller;
	158	#gpio-cells = <2>;
	159
	160	interrupt-controller;
	161	#interrupt-cells = <2>;
d63dc051 HS	162	};
d63dc051 HS	163
c3030d30 HS	164	gpio1: gpio1@2003c000 {
	165	compatible = "rockchip,gpio-bank";
	166	reg = <0x2003c000 0x100>;
	167	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	168	clocks = <&cru PCLK_GPIO1>;
de18e014	169
c3030d30 HS	170	gpio-controller;
	171	#gpio-cells = <2>;
	172
	173	interrupt-controller;
	174	#interrupt-cells = <2>;
de18e014 HS	175	};
de18e014 HS	176
c3030d30 HS	177	gpio2: gpio2@2003e000 {
	178	compatible = "rockchip,gpio-bank";
	179	reg = <0x2003e000 0x100>;
	180	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	181	clocks = <&cru PCLK_GPIO2>;
	182
	183	gpio-controller;
	184	#gpio-cells = <2>;
b13d2a7b	185
c3030d30 HS	186	interrupt-controller;
c3030d30 HS	187	#interrupt-cells = <2>;
b13d2a7b HS	188	};
b13d2a7b HS	189
c3030d30 HS	190	gpio3: gpio3@20080000 {
	191	compatible = "rockchip,gpio-bank";
	192	reg = <0x20080000 0x100>;
	193	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	194	clocks = <&cru PCLK_GPIO3>;
d63dc051	195
c3030d30 HS	196	gpio-controller;
c3030d30 HS	197	#gpio-cells = <2>;
d63dc051	198
c3030d30 HS	199	interrupt-controller;
	200	#interrupt-cells = <2>;
	201	};
d63dc051	202
c3030d30 HS	203	gpio4: gpio4@20084000 {
	204	compatible = "rockchip,gpio-bank";
	205	reg = <0x20084000 0x100>;
	206	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	207	clocks = <&cru PCLK_GPIO4>;
d63dc051	208
c3030d30 HS	209	gpio-controller;
c3030d30 HS	210	#gpio-cells = <2>;
d63dc051	211
c3030d30 HS	212	interrupt-controller;
	213	#interrupt-cells = <2>;
	214	};
d63dc051	215
c3030d30 HS	216	gpio6: gpio6@2000a000 {
	217	compatible = "rockchip,gpio-bank";
	218	reg = <0x2000a000 0x100>;
	219	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	220	clocks = <&cru PCLK_GPIO6>;
d63dc051	221
c3030d30 HS	222	gpio-controller;
c3030d30 HS	223	#gpio-cells = <2>;
d63dc051	224
c3030d30 HS	225	interrupt-controller;
	226	#interrupt-cells = <2>;
	227	};
d63dc051	228
c3030d30 HS	229	pcfg_pull_default: pcfg_pull_default {
	230	bias-pull-pin-default;
	231	};
d63dc051	232
c3030d30 HS	233	pcfg_pull_none: pcfg_pull_none {
	234	bias-disable;
	235	};
d63dc051	236
4ff4ae12 HS	237	emmc {
	238	emmc_clk: emmc-clk {
	239	rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
	240	};
	241
	242	emmc_cmd: emmc-cmd {
	243	rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
	244	};
	245
	246	emmc_rst: emmc-rst {
	247	rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
	248	};
	249
	250	/*
	251	* The data pins are shared between nandc and emmc and
	252	* not accessible through pinctrl. Also they should've
	253	* been already set correctly by firmware, as
	254	* flash/emmc is the boot-device.
	255	*/
	256	};
	257
9cdffd8c HS	258	i2c0 {
	259	i2c0_xfer: i2c0-xfer {
	260	rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
	261	<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
	262	};
	263	};
	264
	265	i2c1 {
	266	i2c1_xfer: i2c1-xfer {
	267	rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
	268	<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
	269	};
	270	};
	271
	272	i2c2 {
	273	i2c2_xfer: i2c2-xfer {
	274	rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
	275	<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
	276	};
	277	};
	278
	279	i2c3 {
	280	i2c3_xfer: i2c3-xfer {
	281	rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
	282	<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
	283	};
	284	};
	285
	286	i2c4 {
	287	i2c4_xfer: i2c4-xfer {
	288	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
	289	<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
	290	};
	291	};
	292
550c7f4e BG	293	pwm0 {
	294	pwm0_out: pwm0-out {
	295	rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
	296	};
	297	};
	298
	299	pwm1 {
	300	pwm1_out: pwm1-out {
	301	rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
	302	};
	303	};
	304
	305	pwm2 {
	306	pwm2_out: pwm2-out {
	307	rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
	308	};
	309	};
	310
	311	pwm3 {
	312	pwm3_out: pwm3-out {
	313	rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
	314	};
	315	};
	316
39c2bd78 HS	317	spi0 {
	318	spi0_clk: spi0-clk {
	319	rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
	320	};
	321	spi0_cs0: spi0-cs0 {
	322	rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
	323	};
	324	spi0_tx: spi0-tx {
	325	rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
	326	};
	327	spi0_rx: spi0-rx {
	328	rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
	329	};
	330	spi0_cs1: spi0-cs1 {
	331	rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
	332	};
	333	};
	334
	335	spi1 {
	336	spi1_clk: spi1-clk {
	337	rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
	338	};
	339	spi1_cs0: spi1-cs0 {
	340	rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
	341	};
	342	spi1_rx: spi1-rx {
	343	rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
	344	};
	345	spi1_tx: spi1-tx {
	346	rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
	347	};
	348	spi1_cs1: spi1-cs1 {
	349	rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
	350	};
	351	};
	352
c3030d30 HS	353	uart0 {
	354	uart0_xfer: uart0-xfer {
	355	rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
	356	<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
	357	};
d63dc051	358
c3030d30 HS	359	uart0_cts: uart0-cts {
c3030d30 HS	360	rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	361	};
d63dc051 HS	362
c3030d30 HS	363	uart0_rts: uart0-rts {
	364	rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
	365	};
	366	};
d63dc051	367
c3030d30 HS	368	uart1 {
	369	uart1_xfer: uart1-xfer {
	370	rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
	371	<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
	372	};
d63dc051	373
c3030d30 HS	374	uart1_cts: uart1-cts {
c3030d30 HS	375	rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	376	};
d63dc051 HS	377
c3030d30 HS	378	uart1_rts: uart1-rts {
	379	rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
	380	};
	381	};
d63dc051	382
c3030d30 HS	383	uart2 {
	384	uart2_xfer: uart2-xfer {
	385	rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
	386	<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
	387	};
	388	/* no rts / cts for uart2 */
	389	};
d63dc051	390
c3030d30 HS	391	uart3 {
	392	uart3_xfer: uart3-xfer {
	393	rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
	394	<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	395	};
d63dc051 HS	396
c3030d30 HS	397	uart3_cts: uart3-cts {
c3030d30 HS	398	rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	399	};
d63dc051 HS	400
c3030d30 HS	401	uart3_rts: uart3-rts {
c3030d30 HS	402	rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
d63dc051	403	};
c3030d30	404	};
d63dc051	405
c3030d30 HS	406	sd0 {
	407	sd0_clk: sd0-clk {
	408	rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
	409	};
d63dc051	410
c3030d30 HS	411	sd0_cmd: sd0-cmd {
	412	rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
	413	};
d63dc051	414
c3030d30 HS	415	sd0_cd: sd0-cd {
c3030d30 HS	416	rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	417	};
d63dc051 HS	418
c3030d30 HS	419	sd0_wp: sd0-wp {
	420	rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
	421	};
d63dc051	422
c3030d30 HS	423	sd0_bus1: sd0-bus-width1 {
	424	rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
	425	};
d63dc051	426
c3030d30 HS	427	sd0_bus4: sd0-bus-width4 {
	428	rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
	429	<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
	430	<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
	431	<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
d63dc051	432	};
c3030d30	433	};
d63dc051	434
c3030d30 HS	435	sd1 {
	436	sd1_clk: sd1-clk {
	437	rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	438	};
d63dc051 HS	439
c3030d30 HS	440	sd1_cmd: sd1-cmd {
	441	rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
	442	};
d63dc051	443
c3030d30 HS	444	sd1_cd: sd1-cd {
	445	rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
	446	};
d63dc051	447
c3030d30 HS	448	sd1_wp: sd1-wp {
c3030d30 HS	449	rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	450	};
d63dc051 HS	451
c3030d30 HS	452	sd1_bus1: sd1-bus-width1 {
c3030d30 HS	453	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	454	};
d63dc051 HS	455
c3030d30 HS	456	sd1_bus4: sd1-bus-width4 {
	457	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
	458	<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
	459	<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
	460	<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	461	};
d63dc051 HS	462	};
5fe62b83 JC	463
	464	i2s0 {
	465	i2s0_bus: i2s0-bus {
	466	rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
	467	<RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
	468	<RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
	469	<RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
	470	<RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
	471	<RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
	472	<RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
	473	<RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
	474	<RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
	475	};
	476	};
	477
	478	i2s1 {
	479	i2s1_bus: i2s1-bus {
	480	rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
	481	<RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
	482	<RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
	483	<RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
	484	<RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
	485	<RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
	486	};
	487	};
	488
	489	i2s2 {
	490	i2s2_bus: i2s2-bus {
	491	rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
	492	<RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
	493	<RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
	494	<RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
	495	<RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
	496	<RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
	497	};
	498	};
d63dc051 HS	499	};
d63dc051 HS	500	};
fcbbf965	501
9cdffd8c HS	502	&i2c0 {
	503	pinctrl-names = "default";
	504	pinctrl-0 = <&i2c0_xfer>;
	505	};
	506
	507	&i2c1 {
	508	pinctrl-names = "default";
	509	pinctrl-0 = <&i2c1_xfer>;
	510	};
	511
	512	&i2c2 {
	513	pinctrl-names = "default";
	514	pinctrl-0 = <&i2c2_xfer>;
	515	};
	516
	517	&i2c3 {
	518	pinctrl-names = "default";
	519	pinctrl-0 = <&i2c3_xfer>;
	520	};
	521
	522	&i2c4 {
	523	pinctrl-names = "default";
	524	pinctrl-0 = <&i2c4_xfer>;
	525	};
	526
fcbbf965 HS	527	&mmc0 {
	528	pinctrl-names = "default";
	529	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
	530	};
	531
	532	&mmc1 {
	533	pinctrl-names = "default";
	534	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
	535	};
	536
550c7f4e BG	537	&pwm0 {
	538	pinctrl-names = "default";
	539	pinctrl-0 = <&pwm0_out>;
	540	};
	541
	542	&pwm1 {
	543	pinctrl-names = "default";
	544	pinctrl-0 = <&pwm1_out>;
	545	};
	546
	547	&pwm2 {
	548	pinctrl-names = "default";
	549	pinctrl-0 = <&pwm2_out>;
	550	};
	551
	552	&pwm3 {
	553	pinctrl-names = "default";
	554	pinctrl-0 = <&pwm3_out>;
	555	};
	556
39c2bd78 HS	557	&spi0 {
	558	pinctrl-names = "default";
	559	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	560	};
	561
	562	&spi1 {
	563	pinctrl-names = "default";
	564	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	565	};
	566
fcbbf965 HS	567	&uart0 {
	568	pinctrl-names = "default";
	569	pinctrl-0 = <&uart0_xfer>;
	570	};
	571
	572	&uart1 {
	573	pinctrl-names = "default";
	574	pinctrl-0 = <&uart1_xfer>;
	575	};
	576
	577	&uart2 {
	578	pinctrl-names = "default";
	579	pinctrl-0 = <&uart2_xfer>;
	580	};
	581
	582	&uart3 {
	583	pinctrl-names = "default";
	584	pinctrl-0 = <&uart3_xfer>;
	585	};
eb2b9d47 HS	586
	587	&wdt {
	588	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
	589	};