[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / rk3066a.dtsi

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3066a-cru.h>
#include "rk3xxx.dtsi"

/ {
	compatible = "rockchip,rk3066a";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
			operating-points = <
				/* kHz    uV */
				1008000 1075000
				 816000 1025000
				 600000 1025000
				 504000 1000000
				 312000  975000
			>;
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x10000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x0 0x50>;
		};
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3066a-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	timer@2000e000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2000e000 0x100>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
		clock-names = "timer", "pclk";
	};

	timer@20038000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x20038000 0x100>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
		clock-names = "timer", "pclk";
	};

	timer@2003a000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2003a000 0x100>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
		clock-names = "timer", "pclk";
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3066a-pinctrl";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@20034000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20034000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@2003c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003c000 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@2003e000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003e000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio4@20084000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20084000 0x100>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio6@2000a000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2000a000 0x100>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO6>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_default: pcfg_pull_default {
			bias-pull-pin-default;
		};

		pcfg_pull_none: pcfg_pull_none {
			bias-disable;
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_rst: emmc-rst {
				rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
			};

			/*
			 * The data pins are shared between nandc and emmc and
			 * not accessible through pinctrl. Also they should've
			 * been already set correctly by firmware, as
			 * flash/emmc is the boot-device.
			 */
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c4 {
			i2c4_xfer: i2c4-xfer {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_out: pwm0-out {
				rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_out: pwm1-out {
				rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_out: pwm2-out {
				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_out: pwm3-out {
				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0_clk: spi0-clk {
				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_cs0: spi0-cs0 {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_tx: spi0-tx {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_rx: spi0-rx {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_cs1: spi0-cs1 {
				rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		spi1 {
			spi1_clk: spi1-clk {
				rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_cs0: spi1-cs0 {
				rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_rx: spi1-rx {
				rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_tx: spi1-tx {
				rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_cs1: spi1-cs1 {
				rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
			};
			/* no rts / cts for uart2 */
		};

		uart3 {
			uart3_xfer: uart3-xfer {
				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_cts: uart3-cts {
				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_rts: uart3-rts {
				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd0 {
			sd0_clk: sd0-clk {
				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cmd: sd0-cmd {
				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cd: sd0-cd {
				rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_wp: sd0-wp {
				rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus1: sd0-bus-width1 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus4: sd0-bus-width4 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd1 {
			sd1_clk: sd1-clk {
				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cmd: sd1-cmd {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cd: sd1-cd {
				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_wp: sd1-wp {
				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus1: sd1-bus-width1 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus4: sd1-bus-width4 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
			};
		};
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
};

&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_out>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_out>;
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_out>;
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_out>;
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
};

&wdt {
	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
};
Commit	Line	Data
d63dc051 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <dt-bindings/gpio/gpio.h>
d63dc051	17	#include <dt-bindings/pinctrl/rockchip.h>
b13d2a7b	18	#include <dt-bindings/clock/rk3066a-cru.h>
f75efdd7	19	#include "rk3xxx.dtsi"
d63dc051 HS	20
	21	/ {
	22	compatible = "rockchip,rk3066a";
d63dc051 HS	23
	24	cpus {
	25	#address-cells = <1>;
	26	#size-cells = <0>;
26ab69cb	27	enable-method = "rockchip,rk3066-smp";
d63dc051	28
be8a77c5	29	cpu0: cpu@0 {
d63dc051 HS	30	device_type = "cpu";
	31	compatible = "arm,cortex-a9";
	32	next-level-cache = <&L2>;
	33	reg = <0x0>;
be8a77c5 HS	34	operating-points = <
	35	/* kHz uV */
	36	1008000 1075000
	37	816000 1025000
	38	600000 1025000
	39	504000 1000000
	40	312000 975000
	41	>;
	42	clock-latency = <40000>;
	43	clocks = <&cru ARMCLK>;
d63dc051 HS	44	};
	45	cpu@1 {
	46	device_type = "cpu";
	47	compatible = "arm,cortex-a9";
	48	next-level-cache = <&L2>;
	49	reg = <0x1>;
	50	};
	51	};
	52
c3030d30 HS	53	sram: sram@10080000 {
	54	compatible = "mmio-sram";
	55	reg = <0x10080000 0x10000>;
	56	#address-cells = <1>;
	57	#size-cells = <1>;
	58	ranges = <0 0x10080000 0x10000>;
	59
	60	smp-sram@0 {
	61	compatible = "rockchip,rk3066-smp-sram";
	62	reg = <0x0 0x50>;
d63dc051	63	};
c3030d30 HS	64	};
	65
	66	cru: clock-controller@20000000 {
	67	compatible = "rockchip,rk3066a-cru";
	68	reg = <0x20000000 0x1000>;
	69	rockchip,grf = <&grf>;
	70
	71	#clock-cells = <1>;
	72	#reset-cells = <1>;
	73	};
	74
ff84b90e HS	75	timer@2000e000 {
	76	compatible = "snps,dw-apb-timer-osc";
	77	reg = <0x2000e000 0x100>;
	78	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	79	clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
	80	clock-names = "timer", "pclk";
	81	};
	82
	83	timer@20038000 {
	84	compatible = "snps,dw-apb-timer-osc";
	85	reg = <0x20038000 0x100>;
	86	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	87	clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
	88	clock-names = "timer", "pclk";
	89	};
	90
	91	timer@2003a000 {
	92	compatible = "snps,dw-apb-timer-osc";
	93	reg = <0x2003a000 0x100>;
	94	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	95	clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
	96	clock-names = "timer", "pclk";
	97	};
	98
6e4b3b4b	99	pinctrl: pinctrl {
c3030d30 HS	100	compatible = "rockchip,rk3066a-pinctrl";
	101	rockchip,grf = <&grf>;
	102	#address-cells = <1>;
	103	#size-cells = <1>;
	104	ranges;
d63dc051	105
c3030d30 HS	106	gpio0: gpio0@20034000 {
	107	compatible = "rockchip,gpio-bank";
	108	reg = <0x20034000 0x100>;
	109	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	110	clocks = <&cru PCLK_GPIO0>;
	111
	112	gpio-controller;
	113	#gpio-cells = <2>;
	114
	115	interrupt-controller;
	116	#interrupt-cells = <2>;
d63dc051 HS	117	};
d63dc051 HS	118
c3030d30 HS	119	gpio1: gpio1@2003c000 {
	120	compatible = "rockchip,gpio-bank";
	121	reg = <0x2003c000 0x100>;
	122	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	123	clocks = <&cru PCLK_GPIO1>;
de18e014	124
c3030d30 HS	125	gpio-controller;
	126	#gpio-cells = <2>;
	127
	128	interrupt-controller;
	129	#interrupt-cells = <2>;
de18e014 HS	130	};
de18e014 HS	131
c3030d30 HS	132	gpio2: gpio2@2003e000 {
	133	compatible = "rockchip,gpio-bank";
	134	reg = <0x2003e000 0x100>;
	135	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	136	clocks = <&cru PCLK_GPIO2>;
	137
	138	gpio-controller;
	139	#gpio-cells = <2>;
b13d2a7b	140
c3030d30 HS	141	interrupt-controller;
c3030d30 HS	142	#interrupt-cells = <2>;
b13d2a7b HS	143	};
b13d2a7b HS	144
c3030d30 HS	145	gpio3: gpio3@20080000 {
	146	compatible = "rockchip,gpio-bank";
	147	reg = <0x20080000 0x100>;
	148	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	149	clocks = <&cru PCLK_GPIO3>;
d63dc051	150
c3030d30 HS	151	gpio-controller;
c3030d30 HS	152	#gpio-cells = <2>;
d63dc051	153
c3030d30 HS	154	interrupt-controller;
	155	#interrupt-cells = <2>;
	156	};
d63dc051	157
c3030d30 HS	158	gpio4: gpio4@20084000 {
	159	compatible = "rockchip,gpio-bank";
	160	reg = <0x20084000 0x100>;
	161	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	162	clocks = <&cru PCLK_GPIO4>;
d63dc051	163
c3030d30 HS	164	gpio-controller;
c3030d30 HS	165	#gpio-cells = <2>;
d63dc051	166
c3030d30 HS	167	interrupt-controller;
	168	#interrupt-cells = <2>;
	169	};
d63dc051	170
c3030d30 HS	171	gpio6: gpio6@2000a000 {
	172	compatible = "rockchip,gpio-bank";
	173	reg = <0x2000a000 0x100>;
	174	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	175	clocks = <&cru PCLK_GPIO6>;
d63dc051	176
c3030d30 HS	177	gpio-controller;
c3030d30 HS	178	#gpio-cells = <2>;
d63dc051	179
c3030d30 HS	180	interrupt-controller;
	181	#interrupt-cells = <2>;
	182	};
d63dc051	183
c3030d30 HS	184	pcfg_pull_default: pcfg_pull_default {
	185	bias-pull-pin-default;
	186	};
d63dc051	187
c3030d30 HS	188	pcfg_pull_none: pcfg_pull_none {
	189	bias-disable;
	190	};
d63dc051	191
4ff4ae12 HS	192	emmc {
	193	emmc_clk: emmc-clk {
	194	rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
	195	};
	196
	197	emmc_cmd: emmc-cmd {
	198	rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
	199	};
	200
	201	emmc_rst: emmc-rst {
	202	rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
	203	};
	204
	205	/*
	206	* The data pins are shared between nandc and emmc and
	207	* not accessible through pinctrl. Also they should've
	208	* been already set correctly by firmware, as
	209	* flash/emmc is the boot-device.
	210	*/
	211	};
	212
9cdffd8c HS	213	i2c0 {
	214	i2c0_xfer: i2c0-xfer {
	215	rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
	216	<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
	217	};
	218	};
	219
	220	i2c1 {
	221	i2c1_xfer: i2c1-xfer {
	222	rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
	223	<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
	224	};
	225	};
	226
	227	i2c2 {
	228	i2c2_xfer: i2c2-xfer {
	229	rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
	230	<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
	231	};
	232	};
	233
	234	i2c3 {
	235	i2c3_xfer: i2c3-xfer {
	236	rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
	237	<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
	238	};
	239	};
	240
	241	i2c4 {
	242	i2c4_xfer: i2c4-xfer {
	243	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
	244	<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
	245	};
	246	};
	247
550c7f4e BG	248	pwm0 {
	249	pwm0_out: pwm0-out {
	250	rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
	251	};
	252	};
	253
	254	pwm1 {
	255	pwm1_out: pwm1-out {
	256	rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
	257	};
	258	};
	259
	260	pwm2 {
	261	pwm2_out: pwm2-out {
	262	rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
	263	};
	264	};
	265
	266	pwm3 {
	267	pwm3_out: pwm3-out {
	268	rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
	269	};
	270	};
	271
39c2bd78 HS	272	spi0 {
	273	spi0_clk: spi0-clk {
	274	rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
	275	};
	276	spi0_cs0: spi0-cs0 {
	277	rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
	278	};
	279	spi0_tx: spi0-tx {
	280	rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
	281	};
	282	spi0_rx: spi0-rx {
	283	rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
	284	};
	285	spi0_cs1: spi0-cs1 {
	286	rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
	287	};
	288	};
	289
	290	spi1 {
	291	spi1_clk: spi1-clk {
	292	rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
	293	};
	294	spi1_cs0: spi1-cs0 {
	295	rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
	296	};
	297	spi1_rx: spi1-rx {
	298	rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
	299	};
	300	spi1_tx: spi1-tx {
	301	rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
	302	};
	303	spi1_cs1: spi1-cs1 {
	304	rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
	305	};
	306	};
	307
c3030d30 HS	308	uart0 {
	309	uart0_xfer: uart0-xfer {
	310	rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
	311	<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
	312	};
d63dc051	313
c3030d30 HS	314	uart0_cts: uart0-cts {
c3030d30 HS	315	rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	316	};
d63dc051 HS	317
c3030d30 HS	318	uart0_rts: uart0-rts {
	319	rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
	320	};
	321	};
d63dc051	322
c3030d30 HS	323	uart1 {
	324	uart1_xfer: uart1-xfer {
	325	rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
	326	<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
	327	};
d63dc051	328
c3030d30 HS	329	uart1_cts: uart1-cts {
c3030d30 HS	330	rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	331	};
d63dc051 HS	332
c3030d30 HS	333	uart1_rts: uart1-rts {
	334	rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
	335	};
	336	};
d63dc051	337
c3030d30 HS	338	uart2 {
	339	uart2_xfer: uart2-xfer {
	340	rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
	341	<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
	342	};
	343	/* no rts / cts for uart2 */
	344	};
d63dc051	345
c3030d30 HS	346	uart3 {
	347	uart3_xfer: uart3-xfer {
	348	rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
	349	<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	350	};
d63dc051 HS	351
c3030d30 HS	352	uart3_cts: uart3-cts {
c3030d30 HS	353	rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	354	};
d63dc051 HS	355
c3030d30 HS	356	uart3_rts: uart3-rts {
c3030d30 HS	357	rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
d63dc051	358	};
c3030d30	359	};
d63dc051	360
c3030d30 HS	361	sd0 {
	362	sd0_clk: sd0-clk {
	363	rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
	364	};
d63dc051	365
c3030d30 HS	366	sd0_cmd: sd0-cmd {
	367	rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
	368	};
d63dc051	369
c3030d30 HS	370	sd0_cd: sd0-cd {
c3030d30 HS	371	rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	372	};
d63dc051 HS	373
c3030d30 HS	374	sd0_wp: sd0-wp {
	375	rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
	376	};
d63dc051	377
c3030d30 HS	378	sd0_bus1: sd0-bus-width1 {
	379	rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
	380	};
d63dc051	381
c3030d30 HS	382	sd0_bus4: sd0-bus-width4 {
	383	rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
	384	<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
	385	<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
	386	<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
d63dc051	387	};
c3030d30	388	};
d63dc051	389
c3030d30 HS	390	sd1 {
	391	sd1_clk: sd1-clk {
	392	rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	393	};
d63dc051 HS	394
c3030d30 HS	395	sd1_cmd: sd1-cmd {
	396	rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
	397	};
d63dc051	398
c3030d30 HS	399	sd1_cd: sd1-cd {
	400	rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
	401	};
d63dc051	402
c3030d30 HS	403	sd1_wp: sd1-wp {
c3030d30 HS	404	rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	405	};
d63dc051 HS	406
c3030d30 HS	407	sd1_bus1: sd1-bus-width1 {
c3030d30 HS	408	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	409	};
d63dc051 HS	410
c3030d30 HS	411	sd1_bus4: sd1-bus-width4 {
	412	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
	413	<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
	414	<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
	415	<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	416	};
d63dc051 HS	417	};
d63dc051 HS	418	};
d63dc051 HS	419	};
fcbbf965	420
9cdffd8c HS	421	&i2c0 {
	422	pinctrl-names = "default";
	423	pinctrl-0 = <&i2c0_xfer>;
	424	};
	425
	426	&i2c1 {
	427	pinctrl-names = "default";
	428	pinctrl-0 = <&i2c1_xfer>;
	429	};
	430
	431	&i2c2 {
	432	pinctrl-names = "default";
	433	pinctrl-0 = <&i2c2_xfer>;
	434	};
	435
	436	&i2c3 {
	437	pinctrl-names = "default";
	438	pinctrl-0 = <&i2c3_xfer>;
	439	};
	440
	441	&i2c4 {
	442	pinctrl-names = "default";
	443	pinctrl-0 = <&i2c4_xfer>;
	444	};
	445
fcbbf965 HS	446	&mmc0 {
	447	pinctrl-names = "default";
	448	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
	449	};
	450
	451	&mmc1 {
	452	pinctrl-names = "default";
	453	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
	454	};
	455
550c7f4e BG	456	&pwm0 {
	457	pinctrl-names = "default";
	458	pinctrl-0 = <&pwm0_out>;
	459	};
	460
	461	&pwm1 {
	462	pinctrl-names = "default";
	463	pinctrl-0 = <&pwm1_out>;
	464	};
	465
	466	&pwm2 {
	467	pinctrl-names = "default";
	468	pinctrl-0 = <&pwm2_out>;
	469	};
	470
	471	&pwm3 {
	472	pinctrl-names = "default";
	473	pinctrl-0 = <&pwm3_out>;
	474	};
	475
39c2bd78 HS	476	&spi0 {
	477	pinctrl-names = "default";
	478	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	479	};
	480
	481	&spi1 {
	482	pinctrl-names = "default";
	483	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	484	};
	485
fcbbf965 HS	486	&uart0 {
	487	pinctrl-names = "default";
	488	pinctrl-0 = <&uart0_xfer>;
	489	};
	490
	491	&uart1 {
	492	pinctrl-names = "default";
	493	pinctrl-0 = <&uart1_xfer>;
	494	};
	495
	496	&uart2 {
	497	pinctrl-names = "default";
	498	pinctrl-0 = <&uart2_xfer>;
	499	};
	500
	501	&uart3 {
	502	pinctrl-names = "default";
	503	pinctrl-0 = <&uart3_xfer>;
	504	};
eb2b9d47 HS	505
	506	&wdt {
	507	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
	508	};